Commit c7d2a0eb authored by Evan Green's avatar Evan Green Committed by Stephen Boyd

clk: qcom: Base rcg parent rate off plan frequency

_freq_tbl_determine_rate uses the pre_div found in the clock plan
multiplied by the requested rate from the caller to determine the
best parent rate to set. If the requested rate is not exactly equal
to the rate that was found in the clock plan, then using the requested
rate in parent rate calculations is incorrect. For instance, if 150MHz
was requested, but 200MHz was the match found, and that plan had a
pre_div of 3, then the parent should be set to 600MHz, not 450MHz.
Signed-off-by: default avatarEvan Green <evgreen@chromium.org>
Fixes: bcd61c0f ("clk: qcom: Add support for root clock generators (RCGs)")
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 60cc43fc
...@@ -211,6 +211,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, ...@@ -211,6 +211,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
clk_flags = clk_hw_get_flags(hw); clk_flags = clk_hw_get_flags(hw);
p = clk_hw_get_parent_by_index(hw, index); p = clk_hw_get_parent_by_index(hw, index);
if (clk_flags & CLK_SET_RATE_PARENT) { if (clk_flags & CLK_SET_RATE_PARENT) {
rate = f->freq;
if (f->pre_div) { if (f->pre_div) {
rate /= 2; rate /= 2;
rate *= f->pre_div + 1; rate *= f->pre_div + 1;
......
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