Commit c82be9d2 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'pm-turbostat-4.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm

Pull turbostat utility updates from Rafael Wysocki:
 "Power management turbostat utility updates.

  These update turbostat significantly and in particular:

   - default output is now verbose, --debug is no longer required to get
     all counters. As a result, some options have been added to specify
     exactly what output is wanted.

   - added --quiet to skip system configuration output

   - added --list, --show and --hide parameters

   - added --cpu parameter

   - enhanced Baytrail SoC support

   - added Gemini Lake SoC support

   - added sysfs C-state columns

  Also the symbol definitions in arch/x86/include/asm/intel-family.h and
  arch/x86/include/asm/msr-index.h are updated and the intel_idle and
  intel_pstate drivers are modified to use the updated symbols.

  Credits to Len Brown for all of these changes"

* tag 'pm-turbostat-4.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (44 commits)
  tools/power turbostat: version 17.02.24
  tools/power turbostat: bugfix: --add u32 was printed as u64
  tools/power turbostat: show error on exec
  tools/power turbostat: dump p-state software config
  tools/power turbostat: show package number, even without --debug
  tools/power turbostat: support "--hide C1" etc.
  tools/power turbostat: move --Package and --processor into the --cpu option
  tools/power turbostat: turbostat.8 update
  tools/power turbostat: update --list feature
  tools/power turbostat: use wide columns to display large numbers
  tools/power turbostat: Add --list option to show available header names
  tools/power turbostat: fix zero IRQ count shown in one-shot command mode
  tools/power turbostat: add --cpu parameter
  tools/power turbostat: print sysfs C-state stats
  tools/power turbostat: extend --add option to accept /sys path
  tools/power turbostat: skip unused counters on BDX
  tools/power turbostat: fix decoding for GLM, DNV, SKX turbo-ratio limits
  tools/power turbostat: skip unused counters on SKX
  tools/power turbostat: Denverton: use HW CC1 counter, skip C3, C7
  tools/power turbostat: initial Gemini Lake SOC support
  ...
parents 3f80dd67 6bff9c60
...@@ -59,6 +59,7 @@ ...@@ -59,6 +59,7 @@
#define INTEL_FAM6_ATOM_MERRIFIELD 0x4A /* Tangier */ #define INTEL_FAM6_ATOM_MERRIFIELD 0x4A /* Tangier */
#define INTEL_FAM6_ATOM_MOOREFIELD 0x5A /* Anniedale */ #define INTEL_FAM6_ATOM_MOOREFIELD 0x5A /* Anniedale */
#define INTEL_FAM6_ATOM_GOLDMONT 0x5C #define INTEL_FAM6_ATOM_GOLDMONT 0x5C
#define INTEL_FAM6_ATOM_GEMINI_LAKE 0x7A
#define INTEL_FAM6_ATOM_DENVERTON 0x5F /* Goldmont Microserver */ #define INTEL_FAM6_ATOM_DENVERTON 0x5F /* Goldmont Microserver */
/* Xeon Phi */ /* Xeon Phi */
......
...@@ -46,7 +46,7 @@ ...@@ -46,7 +46,7 @@
#define MSR_FSB_FREQ 0x000000cd #define MSR_FSB_FREQ 0x000000cd
#define MSR_PLATFORM_INFO 0x000000ce #define MSR_PLATFORM_INFO 0x000000ce
#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
#define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C3_AUTO_DEMOTE (1UL << 25)
#define NHM_C1_AUTO_DEMOTE (1UL << 26) #define NHM_C1_AUTO_DEMOTE (1UL << 26)
#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
...@@ -147,6 +147,7 @@ ...@@ -147,6 +147,7 @@
/* C-state Residency Counters */ /* C-state Residency Counters */
#define MSR_PKG_C3_RESIDENCY 0x000003f8 #define MSR_PKG_C3_RESIDENCY 0x000003f8
#define MSR_PKG_C6_RESIDENCY 0x000003f9 #define MSR_PKG_C6_RESIDENCY 0x000003f9
#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
#define MSR_PKG_C7_RESIDENCY 0x000003fa #define MSR_PKG_C7_RESIDENCY 0x000003fa
#define MSR_CORE_C3_RESIDENCY 0x000003fc #define MSR_CORE_C3_RESIDENCY 0x000003fc
#define MSR_CORE_C6_RESIDENCY 0x000003fd #define MSR_CORE_C6_RESIDENCY 0x000003fd
...@@ -203,10 +204,17 @@ ...@@ -203,10 +204,17 @@
#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
#define MSR_CORE_C1_RES 0x00000660 #define MSR_CORE_C1_RES 0x00000660
#define MSR_MODULE_C6_RES_MS 0x00000664
#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
#define MSR_ATOM_CORE_RATIOS 0x0000066a
#define MSR_ATOM_CORE_VIDS 0x0000066b
#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c
#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d
#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
...@@ -459,6 +467,7 @@ ...@@ -459,6 +467,7 @@
#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
#define MSR_MISC_FEATURE_CONTROL 0x000001a4
#define MSR_MISC_PWR_MGMT 0x000001aa #define MSR_MISC_PWR_MGMT 0x000001aa
#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
......
...@@ -39,11 +39,6 @@ ...@@ -39,11 +39,6 @@
#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
#define ATOM_RATIOS 0x66a
#define ATOM_VIDS 0x66b
#define ATOM_TURBO_RATIOS 0x66c
#define ATOM_TURBO_VIDS 0x66d
#ifdef CONFIG_ACPI #ifdef CONFIG_ACPI
#include <acpi/processor.h> #include <acpi/processor.h>
#include <acpi/cppc_acpi.h> #include <acpi/cppc_acpi.h>
...@@ -1355,7 +1350,7 @@ static int atom_get_min_pstate(void) ...@@ -1355,7 +1350,7 @@ static int atom_get_min_pstate(void)
{ {
u64 value; u64 value;
rdmsrl(ATOM_RATIOS, value); rdmsrl(MSR_ATOM_CORE_RATIOS, value);
return (value >> 8) & 0x7F; return (value >> 8) & 0x7F;
} }
...@@ -1363,7 +1358,7 @@ static int atom_get_max_pstate(void) ...@@ -1363,7 +1358,7 @@ static int atom_get_max_pstate(void)
{ {
u64 value; u64 value;
rdmsrl(ATOM_RATIOS, value); rdmsrl(MSR_ATOM_CORE_RATIOS, value);
return (value >> 16) & 0x7F; return (value >> 16) & 0x7F;
} }
...@@ -1371,7 +1366,7 @@ static int atom_get_turbo_pstate(void) ...@@ -1371,7 +1366,7 @@ static int atom_get_turbo_pstate(void)
{ {
u64 value; u64 value;
rdmsrl(ATOM_TURBO_RATIOS, value); rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
return value & 0x7F; return value & 0x7F;
} }
...@@ -1433,7 +1428,7 @@ static void atom_get_vid(struct cpudata *cpudata) ...@@ -1433,7 +1428,7 @@ static void atom_get_vid(struct cpudata *cpudata)
{ {
u64 value; u64 value;
rdmsrl(ATOM_VIDS, value); rdmsrl(MSR_ATOM_CORE_VIDS, value);
cpudata->vid.min = int_tofp((value >> 8) & 0x7f); cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
cpudata->vid.max = int_tofp((value >> 16) & 0x7f); cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
cpudata->vid.ratio = div_fp( cpudata->vid.ratio = div_fp(
...@@ -1441,7 +1436,7 @@ static void atom_get_vid(struct cpudata *cpudata) ...@@ -1441,7 +1436,7 @@ static void atom_get_vid(struct cpudata *cpudata)
int_tofp(cpudata->pstate.max_pstate - int_tofp(cpudata->pstate.max_pstate -
cpudata->pstate.min_pstate)); cpudata->pstate.min_pstate));
rdmsrl(ATOM_TURBO_VIDS, value); rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
cpudata->vid.turbo = value & 0x7f; cpudata->vid.turbo = value & 0x7f;
} }
......
...@@ -961,9 +961,9 @@ static void auto_demotion_disable(void) ...@@ -961,9 +961,9 @@ static void auto_demotion_disable(void)
{ {
unsigned long long msr_bits; unsigned long long msr_bits;
rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
msr_bits &= ~(icpu->auto_demotion_disable_flags); msr_bits &= ~(icpu->auto_demotion_disable_flags);
wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
} }
static void c1e_promotion_disable(void) static void c1e_promotion_disable(void)
{ {
...@@ -1273,7 +1273,7 @@ static void sklh_idle_state_table_update(void) ...@@ -1273,7 +1273,7 @@ static void sklh_idle_state_table_update(void)
if ((mwait_substates & (0xF << 28)) == 0) if ((mwait_substates & (0xF << 28)) == 0)
return; return;
rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr); rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
/* PC10 is not enabled in PKG C-state limit */ /* PC10 is not enabled in PKG C-state limit */
if ((msr & 0xF) != 8) if ((msr & 0xF) != 8)
......
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