Commit c858d436 authored by Vladimir Oltean's avatar Vladimir Oltean Committed by David S. Miller

net: phy: introduce PHY_INTERFACE_MODE_REVRMII

The "reverse RMII" protocol name is a personal invention, derived from
"reverse MII".

Just like MII, RMII is an asymmetric protocol in that a PHY behaves
differently than a MAC. In the case of RMII, for example:
- the 50 MHz clock signals are either driven by the MAC or by an
  external oscillator (but never by the PHY).
- the PHY can transmit extra in-band control symbols via RXD[1:0] which
  the MAC is supposed to understand, but a PHY isn't.

The "reverse MII" protocol is not standardized either, except for this
web document:
https://www.eetimes.com/reverse-media-independent-interface-revmii-block-architecture/#

In short, it means that the Ethernet controller speaks the 4-bit data
parallel protocol from the perspective of a PHY (it acts like a PHY).
This might mean that it implements clause 22 compatible registers,
although that is optional - the important bit is that its pins can be
connected to an MII MAC and it will 'just work'.

In this discussion thread:
https://lore.kernel.org/netdev/20210201214515.cx6ivvme2tlquge2@skbuf/

we agreed that it would be an abuse of terms to use the "RevMII" name
for anything than the 4-bit parallel MII protocol. But since all the
same concepts can be applied to the 2-bit Reduced MII protocol as well,
here we are introducing a "Reverse RMII" protocol. This means: "behave
like an RMII PHY".
Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 1a42624a
...@@ -68,6 +68,7 @@ properties: ...@@ -68,6 +68,7 @@ properties:
- tbi - tbi
- rev-mii - rev-mii
- rmii - rmii
- rev-rmii
# RX and TX delays are added by the MAC when required # RX and TX delays are added by the MAC when required
- rgmii - rgmii
......
...@@ -93,6 +93,7 @@ extern const int phy_10gbit_features_array[1]; ...@@ -93,6 +93,7 @@ extern const int phy_10gbit_features_array[1];
* @PHY_INTERFACE_MODE_TBI: Ten Bit Interface * @PHY_INTERFACE_MODE_TBI: Ten Bit Interface
* @PHY_INTERFACE_MODE_REVMII: Reverse Media Independent Interface * @PHY_INTERFACE_MODE_REVMII: Reverse Media Independent Interface
* @PHY_INTERFACE_MODE_RMII: Reduced Media Independent Interface * @PHY_INTERFACE_MODE_RMII: Reduced Media Independent Interface
* @PHY_INTERFACE_MODE_REVRMII: Reduced Media Independent Interface in PHY role
* @PHY_INTERFACE_MODE_RGMII: Reduced gigabit media-independent interface * @PHY_INTERFACE_MODE_RGMII: Reduced gigabit media-independent interface
* @PHY_INTERFACE_MODE_RGMII_ID: RGMII with Internal RX+TX delay * @PHY_INTERFACE_MODE_RGMII_ID: RGMII with Internal RX+TX delay
* @PHY_INTERFACE_MODE_RGMII_RXID: RGMII with Internal RX delay * @PHY_INTERFACE_MODE_RGMII_RXID: RGMII with Internal RX delay
...@@ -126,6 +127,7 @@ typedef enum { ...@@ -126,6 +127,7 @@ typedef enum {
PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_TBI,
PHY_INTERFACE_MODE_REVMII, PHY_INTERFACE_MODE_REVMII,
PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RMII,
PHY_INTERFACE_MODE_REVRMII,
PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_RGMII,
PHY_INTERFACE_MODE_RGMII_ID, PHY_INTERFACE_MODE_RGMII_ID,
PHY_INTERFACE_MODE_RGMII_RXID, PHY_INTERFACE_MODE_RGMII_RXID,
...@@ -185,6 +187,8 @@ static inline const char *phy_modes(phy_interface_t interface) ...@@ -185,6 +187,8 @@ static inline const char *phy_modes(phy_interface_t interface)
return "rev-mii"; return "rev-mii";
case PHY_INTERFACE_MODE_RMII: case PHY_INTERFACE_MODE_RMII:
return "rmii"; return "rmii";
case PHY_INTERFACE_MODE_REVRMII:
return "rev-rmii";
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
return "rgmii"; return "rgmii";
case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_ID:
......
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