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Commit c9ac1361 authored by Paul Mundt's avatar Paul Mundt
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Merge branch 'viafb-next' of git://github.com/schandinat/linux-2.6

parents 53b50314 2563afa9
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Showing with 579 additions and 1025 deletions
drivers/video/via/chip.h
View file @ c9ac1361
......@@ -110,16 +110,13 @@
struct tmds_chip_information {
int tmds_chip_name;
int tmds_chip_slave_addr;
int data_mode;
int output_interface;
int i2c_port;
int device_type;
};
struct lvds_chip_information {
int lvds_chip_name;
int lvds_chip_slave_addr;
int data_mode;
int output_interface;
int i2c_port;
};
......@@ -142,9 +139,6 @@ struct chip_information {
struct crt_setting_information {
int iga_path;
int h_active;
int v_active;
int bpp;
int refresh_rate;
};
......@@ -162,8 +156,6 @@ struct lvds_setting_information {
int h_active;
int v_active;
int bpp;
int refresh_rate;
int lcd_panel_id;
int lcd_panel_hres;
int lcd_panel_vres;
int display_method;
......@@ -188,7 +180,6 @@ struct GFX_DPA_SETTING {
};
struct VT1636_DPA_SETTING {
int PanelSizeID;
u8 CLK_SEL_ST1;
u8 CLK_SEL_ST2;
};
......
drivers/video/via/dvi.c
View file @ c9ac1361
......@@ -195,7 +195,9 @@ void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp,
struct crt_mode_table *pDviTiming;
unsigned long desirePixelClock, maxPixelClock;
pDviTiming = mode->crtc;
desirePixelClock = pDviTiming->clk / 1000000;
desirePixelClock = pDviTiming->refresh_rate
* pDviTiming->crtc.hor_total * pDviTiming->crtc.ver_total
/ 1000000;
maxPixelClock = (unsigned long)viaparinfo->
tmds_setting_info->max_pixel_clock;
......
drivers/video/via/hw.c
View file @ c9ac1361
This diff is collapsed.
drivers/video/via/hw.h
View file @ c9ac1361
......@@ -893,8 +893,6 @@ struct iga2_crtc_timing {
/* VT3410 chipset*/
#define VX900_FUNCTION3 0x3410
#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
struct IODATA {
u8 Index;
u8 Mask;
......
drivers/video/via/lcd.c
View file @ c9ac1361
This diff is collapsed.
drivers/video/via/share.h
View file @ c9ac1361
......@@ -627,77 +627,6 @@
#define M2048x1536_R60_HSP NEGATIVE
#define M2048x1536_R60_VSP POSITIVE
/* define PLL index: */
#define CLK_25_175M 25175000
#define CLK_26_880M 26880000
#define CLK_29_581M 29581000
#define CLK_31_500M 31500000
#define CLK_31_728M 31728000
#define CLK_32_668M 32688000
#define CLK_36_000M 36000000
#define CLK_40_000M 40000000
#define CLK_41_291M 41291000
#define CLK_43_163M 43163000
#define CLK_45_250M 45250000 /* 45.46MHz */
#define CLK_46_000M 46000000
#define CLK_46_996M 46996000
#define CLK_48_000M 48000000
#define CLK_48_875M 48875000
#define CLK_49_500M 49500000
#define CLK_52_406M 52406000
#define CLK_52_977M 52977000
#define CLK_56_250M 56250000
#define CLK_57_275M 57275000
#define CLK_60_466M 60466000
#define CLK_61_500M 61500000
#define CLK_65_000M 65000000
#define CLK_65_178M 65178000
#define CLK_66_750M 66750000 /* 67.116MHz */
#define CLK_68_179M 68179000
#define CLK_69_924M 69924000
#define CLK_70_159M 70159000
#define CLK_72_000M 72000000
#define CLK_74_270M 74270000
#define CLK_78_750M 78750000
#define CLK_80_136M 80136000
#define CLK_83_375M 83375000
#define CLK_83_950M 83950000
#define CLK_84_750M 84750000 /* 84.537Mhz */
#define CLK_85_860M 85860000
#define CLK_88_750M 88750000
#define CLK_94_500M 94500000
#define CLK_97_750M 97750000
#define CLK_101_000M 101000000
#define CLK_106_500M 106500000
#define CLK_108_000M 108000000
#define CLK_113_309M 113309000
#define CLK_118_840M 118840000
#define CLK_119_000M 119000000
#define CLK_121_750M 121750000 /* 121.704MHz */
#define CLK_125_104M 125104000
#define CLK_135_000M 135000000
#define CLK_136_700M 136700000
#define CLK_138_400M 138400000
#define CLK_146_760M 146760000
#define CLK_148_500M 148500000
#define CLK_153_920M 153920000
#define CLK_156_000M 156000000
#define CLK_157_500M 157500000
#define CLK_162_000M 162000000
#define CLK_187_000M 187000000
#define CLK_193_295M 193295000
#define CLK_202_500M 202500000
#define CLK_204_000M 204000000
#define CLK_218_500M 218500000
#define CLK_234_000M 234000000
#define CLK_267_250M 267250000
#define CLK_297_500M 297500000
#define CLK_74_481M 74481000
#define CLK_172_798M 172798000
#define CLK_122_614M 122614000
/* Definition CRTC Timing Index */
#define H_TOTAL_INDEX 0
#define H_ADDR_INDEX 1
......@@ -722,76 +651,7 @@
/* Definition Video Mode Pixel Clock (picoseconds)
*/
#define RES_480X640_60HZ_PIXCLOCK 39722
#define RES_640X480_60HZ_PIXCLOCK 39722
#define RES_640X480_75HZ_PIXCLOCK 31747
#define RES_640X480_85HZ_PIXCLOCK 27777
#define RES_640X480_100HZ_PIXCLOCK 23168
#define RES_640X480_120HZ_PIXCLOCK 19081
#define RES_720X480_60HZ_PIXCLOCK 37020
#define RES_720X576_60HZ_PIXCLOCK 30611
#define RES_800X600_60HZ_PIXCLOCK 25000
#define RES_800X600_75HZ_PIXCLOCK 20203
#define RES_800X600_85HZ_PIXCLOCK 17777
#define RES_800X600_100HZ_PIXCLOCK 14667
#define RES_800X600_120HZ_PIXCLOCK 11912
#define RES_800X480_60HZ_PIXCLOCK 33805
#define RES_848X480_60HZ_PIXCLOCK 31756
#define RES_856X480_60HZ_PIXCLOCK 31518
#define RES_1024X512_60HZ_PIXCLOCK 24218
#define RES_1024X600_60HZ_PIXCLOCK 20460
#define RES_1024X768_60HZ_PIXCLOCK 15385
#define RES_1024X768_75HZ_PIXCLOCK 12699
#define RES_1024X768_85HZ_PIXCLOCK 10582
#define RES_1024X768_100HZ_PIXCLOCK 8825
#define RES_1152X864_75HZ_PIXCLOCK 9259
#define RES_1280X768_60HZ_PIXCLOCK 12480
#define RES_1280X800_60HZ_PIXCLOCK 11994
#define RES_1280X960_60HZ_PIXCLOCK 9259
#define RES_1280X1024_60HZ_PIXCLOCK 9260
#define RES_1280X1024_75HZ_PIXCLOCK 7408
#define RES_1280X768_85HZ_PIXCLOCK 6349
#define RES_1440X1050_60HZ_PIXCLOCK 7993
#define RES_1600X1200_60HZ_PIXCLOCK 6172
#define RES_1600X1200_75HZ_PIXCLOCK 4938
#define RES_1280X720_60HZ_PIXCLOCK 13426
#define RES_1200X900_60HZ_PIXCLOCK 17459
#define RES_1920X1080_60HZ_PIXCLOCK 5787
#define RES_1400X1050_60HZ_PIXCLOCK 8214
#define RES_1400X1050_75HZ_PIXCLOCK 6410
#define RES_1368X768_60HZ_PIXCLOCK 11647
#define RES_960X600_60HZ_PIXCLOCK 22099
#define RES_1000X600_60HZ_PIXCLOCK 20834
#define RES_1024X576_60HZ_PIXCLOCK 21278
#define RES_1088X612_60HZ_PIXCLOCK 18877
#define RES_1152X720_60HZ_PIXCLOCK 14981
#define RES_1200X720_60HZ_PIXCLOCK 14253
#define RES_1280X600_60HZ_PIXCLOCK 16260
#define RES_1280X720_50HZ_PIXCLOCK 16538
#define RES_1280X768_50HZ_PIXCLOCK 15342
#define RES_1366X768_50HZ_PIXCLOCK 14301
#define RES_1366X768_60HZ_PIXCLOCK 11646
#define RES_1360X768_60HZ_PIXCLOCK 11799
#define RES_1440X900_60HZ_PIXCLOCK 9390
#define RES_1440X900_75HZ_PIXCLOCK 7315
#define RES_1600X900_60HZ_PIXCLOCK 8415
#define RES_1600X1024_60HZ_PIXCLOCK 7315
#define RES_1680X1050_60HZ_PIXCLOCK 6814
#define RES_1680X1050_75HZ_PIXCLOCK 5348
#define RES_1792X1344_60HZ_PIXCLOCK 4902
#define RES_1856X1392_60HZ_PIXCLOCK 4577
#define RES_1920X1200_60HZ_PIXCLOCK 5173
#define RES_1920X1440_60HZ_PIXCLOCK 4274
#define RES_1920X1440_75HZ_PIXCLOCK 3367
#define RES_2048X1536_60HZ_PIXCLOCK 3742
#define RES_1360X768_RB_60HZ_PIXCLOCK 13889
#define RES_1400X1050_RB_60HZ_PIXCLOCK 9901
#define RES_1440X900_RB_60HZ_PIXCLOCK 11268
#define RES_1600X900_RB_60HZ_PIXCLOCK 10230
#define RES_1680X1050_RB_60HZ_PIXCLOCK 8403
#define RES_1920X1080_RB_60HZ_PIXCLOCK 7225
#define RES_1920X1200_RB_60HZ_PIXCLOCK 6497
/* LCD display method
*/
......@@ -822,7 +682,6 @@ struct display_timing {
struct crt_mode_table {
int refresh_rate;
unsigned long clk;
int h_sync_polarity;
int v_sync_polarity;
struct display_timing crtc;
......
drivers/video/via/tblDPASetting.c
View file @ c9ac1361
......@@ -20,17 +20,6 @@
*/
#include "global.h"
/* For VT3324: */
struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3324[] = {
/* Panel ID, CLK_SEL_ST1[09], CLK_SEL_ST2[08] */
{LCD_PANEL_ID0_640X480, 0x00, 0x00}, /* For 640x480 */
{LCD_PANEL_ID1_800X600, 0x00, 0x00}, /* For 800x600 */
{LCD_PANEL_ID2_1024X768, 0x00, 0x00}, /* For 1024x768 */
{LCD_PANEL_ID3_1280X768, 0x00, 0x00}, /* For 1280x768 */
{LCD_PANEL_ID4_1280X1024, 0x00, 0x00}, /* For 1280x1024 */
{LCD_PANEL_ID5_1400X1050, 0x00, 0x00}, /* For 1400x1050 */
{LCD_PANEL_ID6_1600X1200, 0x0B, 0x03} /* For 1600x1200 */
};
struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = {
/* ClkRange, DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
......@@ -57,18 +46,6 @@ struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = {
0x00},
};
/* For VT3327: */
struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3327[] = {
/* Panel ID, CLK_SEL_ST1[09], CLK_SEL_ST2[08] */
{LCD_PANEL_ID0_640X480, 0x00, 0x00}, /* For 640x480 */
{LCD_PANEL_ID1_800X600, 0x00, 0x00}, /* For 800x600 */
{LCD_PANEL_ID2_1024X768, 0x00, 0x00}, /* For 1024x768 */
{LCD_PANEL_ID3_1280X768, 0x00, 0x00}, /* For 1280x768 */
{LCD_PANEL_ID4_1280X1024, 0x00, 0x00}, /* For 1280x1024 */
{LCD_PANEL_ID5_1400X1050, 0x00, 0x00}, /* For 1400x1050 */
{LCD_PANEL_ID6_1600X1200, 0x00, 0x00} /* For 1600x1200 */
};
struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[] = {
/* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
DVP1Driving, DFPHigh, DFPLow */
......
drivers/video/via/tblDPASetting.h
View file @ c9ac1361
......@@ -38,9 +38,7 @@ enum DPA_RANGE {
DPA_CLK_RANGE_150M
};
extern struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3324[7];
extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[6];
extern struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3327[7];
extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[];
extern struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3364[6];
......
drivers/video/via/via_i2c.c
View file @ c9ac1361
......@@ -32,7 +32,7 @@
*/
#define VIAFB_NUM_I2C 5
static struct via_i2c_stuff via_i2c_par[VIAFB_NUM_I2C];
struct viafb_dev *i2c_vdev; /* Passed in from core */
static struct viafb_dev *i2c_vdev; /* Passed in from core */
static void via_i2c_setscl(void *data, int state)
{
......@@ -209,7 +209,6 @@ static int create_i2c_bus(struct i2c_adapter *adapter,
sprintf(adapter->name, "viafb i2c io_port idx 0x%02x",
adap_cfg->ioport_index);
adapter->owner = THIS_MODULE;
adapter->id = 0x01FFFF;
adapter->class = I2C_CLASS_DDC;
adapter->algo_data = algo;
if (pdev)
......
drivers/video/via/viafbdev.c
View file @ c9ac1361
......@@ -43,11 +43,11 @@ static int viafb_second_size;
static int viafb_accel = 1;
/* Added for specifying active devices.*/
char *viafb_active_dev;
static char *viafb_active_dev;
/*Added for specify lcd output port*/
char *viafb_lcd_port = "";
char *viafb_dvi_port = "";
static char *viafb_lcd_port = "";
static char *viafb_dvi_port = "";
static void retrieve_device_setting(struct viafb_ioctl_setting
*setting_info);
......
drivers/video/via/viamode.c
View file @ c9ac1361
This diff is collapsed.
drivers/video/via/viamode.h
View file @ c9ac1361
......@@ -41,14 +41,6 @@ struct patch_table {
struct io_reg *io_reg_table;
};
struct res_map_refresh {
int hres;
int vres;
int pixclock;
int vmode_refresh;
};
extern int NUM_TOTAL_RES_MAP_REFRESH;
extern int NUM_TOTAL_CEA_MODES;
extern int NUM_TOTAL_CN400_ModeXregs;
extern int NUM_TOTAL_CN700_ModeXregs;
......@@ -66,7 +58,6 @@ extern struct crt_mode_table CEAM1280x720[];
extern struct crt_mode_table CEAM1920x1080[];
extern struct VideoModeTable CEA_HDMI_Modes[];
extern struct res_map_refresh res_map_refresh_tbl[];
extern struct io_reg CN400_ModeXregs[];
extern struct io_reg CN700_ModeXregs[];
extern struct io_reg KM400_ModeXregs[];
......
drivers/video/via/vt1636.c
View file @ c9ac1361
......@@ -167,22 +167,6 @@ static int get_clk_range_index(u32 Clk)
return DPA_CLK_RANGE_150M;
}
static int get_lvds_dpa_setting_index(int panel_size_id,
struct VT1636_DPA_SETTING *p_vt1636_dpasetting_tbl,
int tbl_size)
{
int i;
for (i = 0; i < tbl_size; i++) {
if (panel_size_id == p_vt1636_dpasetting_tbl->PanelSizeID)
return i;
p_vt1636_dpasetting_tbl++;
}
return 0;
}
static void set_dpa_vt1636(struct lvds_setting_information
*plvds_setting_info, struct lvds_chip_information *plvds_chip_info,
struct VT1636_DPA_SETTING *p_vt1636_dpa_setting)
......@@ -206,7 +190,9 @@ void viafb_vt1636_patch_skew_on_vt3324(
struct lvds_setting_information *plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
int index, size;
struct VT1636_DPA_SETTING dpa = {0x00, 0x00}, dpa_16x12 = {0x0B, 0x03},
*pdpa;
int index;
DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3324.\n");
......@@ -216,19 +202,21 @@ void viafb_vt1636_patch_skew_on_vt3324(
&GFX_DPA_SETTING_TBL_VT3324[index]);
/* LVDS Transmitter DPA settings: */
size = ARRAY_SIZE(VT1636_DPA_SETTING_TBL_VT3324);
index =
get_lvds_dpa_setting_index(plvds_setting_info->lcd_panel_id,
VT1636_DPA_SETTING_TBL_VT3324, size);
set_dpa_vt1636(plvds_setting_info, plvds_chip_info,
&VT1636_DPA_SETTING_TBL_VT3324[index]);
if (plvds_setting_info->lcd_panel_hres == 1600 &&
plvds_setting_info->lcd_panel_vres == 1200)
pdpa = &dpa_16x12;
else
pdpa = &dpa;
set_dpa_vt1636(plvds_setting_info, plvds_chip_info, pdpa);
}
void viafb_vt1636_patch_skew_on_vt3327(
struct lvds_setting_information *plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
int index, size;
struct VT1636_DPA_SETTING dpa = {0x00, 0x00};
int index;
DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3327.\n");
......@@ -238,12 +226,7 @@ void viafb_vt1636_patch_skew_on_vt3327(
&GFX_DPA_SETTING_TBL_VT3327[index]);
/* LVDS Transmitter DPA settings: */
size = ARRAY_SIZE(VT1636_DPA_SETTING_TBL_VT3327);
index =
get_lvds_dpa_setting_index(plvds_setting_info->lcd_panel_id,
VT1636_DPA_SETTING_TBL_VT3327, size);
set_dpa_vt1636(plvds_setting_info, plvds_chip_info,
&VT1636_DPA_SETTING_TBL_VT3327[index]);
set_dpa_vt1636(plvds_setting_info, plvds_chip_info, &dpa);
}
void viafb_vt1636_patch_skew_on_vt3364(
......
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