Commit ca165892 authored by Harro Haan's avatar Harro Haan Committed by Bjorn Helgaas

PCI: designware: Fix missing MSI IRQs

The interrupts were cleared after the IRQ handler was called.  This means
that new interrupts that occur after the handler handled the previous IRQ
but before the interrupt is cleared will be missed.
Tested-by: default avatarMarek Vasut <marex@denx.de>
Tested-by: default avatarMatthias Mann <m.mann@arkona-technologies.de>
Signed-off-by: default avatarHarro Haan <hrhaan@gmail.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarJingoo Han <jg1.han@samsung.com>
Acked-by: default avatarMohit Kumar <mohit.kumar@st.com>
Cc: Richard Zhu <hong-xing.zhu@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Juergen Beisert <jbe@pengutronix.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Siva Reddy Kallam <siva.kallam@samsung.com>
Cc: Srikanth T Shivanand <ts.srikanth@samsung.com>
Cc: Sean Cross <xobs@kosagi.com>
parent 0b8cfb6a
......@@ -167,11 +167,13 @@ void dw_handle_msi_irq(struct pcie_port *pp)
while ((pos = find_next_bit(&val, 32, pos)) != 32) {
irq = irq_find_mapping(pp->irq_domain,
i * 32 + pos);
dw_pcie_wr_own_conf(pp,
PCIE_MSI_INTR0_STATUS + i * 12,
4, 1 << pos);
generic_handle_irq(irq);
pos++;
}
}
dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, val);
}
}
......
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