Commit caf5ef7d authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Catalin Marinas

arm64: fix pmem interface definition

Defining the two functions as 'static inline' and exporting them
leads to the interesting case where we can use the interface
from loadable modules, but not from built-in drivers, as shown
in this link failure:

vers/nvdimm/claim.o: In function `nsio_rw_bytes':
claim.c:(.text+0x1b8): undefined reference to `arch_invalidate_pmem'
drivers/nvdimm/pmem.o: In function `pmem_dax_flush':
pmem.c:(.text+0x11c): undefined reference to `arch_wb_cache_pmem'
drivers/nvdimm/pmem.o: In function `pmem_make_request':
pmem.c:(.text+0x5a4): undefined reference to `arch_invalidate_pmem'
pmem.c:(.text+0x650): undefined reference to `arch_invalidate_pmem'
pmem.c:(.text+0x6d4): undefined reference to `arch_invalidate_pmem'

This removes the bogus 'static inline'.

Fixes: d50e071f ("arm64: Implement pmem API support")
Acked-by: default avatarRobin Murphy <robin.murphy@arm.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 21cfa0e9
...@@ -85,7 +85,7 @@ EXPORT_SYMBOL(flush_dcache_page); ...@@ -85,7 +85,7 @@ EXPORT_SYMBOL(flush_dcache_page);
EXPORT_SYMBOL(flush_icache_range); EXPORT_SYMBOL(flush_icache_range);
#ifdef CONFIG_ARCH_HAS_PMEM_API #ifdef CONFIG_ARCH_HAS_PMEM_API
static inline void arch_wb_cache_pmem(void *addr, size_t size) void arch_wb_cache_pmem(void *addr, size_t size)
{ {
/* Ensure order against any prior non-cacheable writes */ /* Ensure order against any prior non-cacheable writes */
dmb(osh); dmb(osh);
...@@ -93,7 +93,7 @@ static inline void arch_wb_cache_pmem(void *addr, size_t size) ...@@ -93,7 +93,7 @@ static inline void arch_wb_cache_pmem(void *addr, size_t size)
} }
EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); EXPORT_SYMBOL_GPL(arch_wb_cache_pmem);
static inline void arch_invalidate_pmem(void *addr, size_t size) void arch_invalidate_pmem(void *addr, size_t size)
{ {
__inval_dcache_area(addr, size); __inval_dcache_area(addr, size);
} }
......
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