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Commit cbeee6ca authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Fix icelakex cstate metrics 

Apply cstate fix from:

https://github.com/intel/event-converter-for-linux-perf/

so that metrics for cstates that exist on the particular architecture
are generated. This corrects issues with metric testing.

Also correct topic of ASSISTS.ANY event.
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220413210503.3256922-2-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 2c77f36a
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Showing with 33 additions and 127 deletions
tools/perf/pmu-events/arch/x86/icelakex/cache.json
View file @ cbeee6ca
...@@ -665,7 +665,6 @@ ...@@ -665,7 +665,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0004", "MSRValue": "0x3F803C0004",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -677,7 +676,6 @@ ...@@ -677,7 +676,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004", "MSRValue": "0x10003C0004",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -689,7 +687,6 @@ ...@@ -689,7 +687,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000004", "MSRValue": "0x1008000004",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -701,7 +698,6 @@ ...@@ -701,7 +698,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000004", "MSRValue": "0x808000004",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -713,7 +709,6 @@ ...@@ -713,7 +709,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0001", "MSRValue": "0x3F803C0001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -725,7 +720,6 @@ ...@@ -725,7 +720,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001", "MSRValue": "0x10003C0001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -737,7 +731,6 @@ ...@@ -737,7 +731,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001", "MSRValue": "0x4003C0001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -749,7 +742,6 @@ ...@@ -749,7 +742,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001", "MSRValue": "0x8003C0001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -761,7 +753,6 @@ ...@@ -761,7 +753,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1030000001", "MSRValue": "0x1030000001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -773,7 +764,6 @@ ...@@ -773,7 +764,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x830000001", "MSRValue": "0x830000001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -785,7 +775,6 @@ ...@@ -785,7 +775,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000001", "MSRValue": "0x1008000001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -797,7 +786,6 @@ ...@@ -797,7 +786,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000001", "MSRValue": "0x808000001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -809,7 +797,6 @@ ...@@ -809,7 +797,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0002", "MSRValue": "0x3F803C0002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -821,7 +808,6 @@ ...@@ -821,7 +808,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002", "MSRValue": "0x10003C0002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -833,7 +819,6 @@ ...@@ -833,7 +819,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000002", "MSRValue": "0x1008000002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -845,7 +830,6 @@ ...@@ -845,7 +830,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000002", "MSRValue": "0x808000002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -857,7 +841,6 @@ ...@@ -857,7 +841,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0400", "MSRValue": "0x3F803C0400",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -869,7 +852,6 @@ ...@@ -869,7 +852,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80082380", "MSRValue": "0x80082380",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -881,7 +863,6 @@ ...@@ -881,7 +863,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C27F0", "MSRValue": "0x3F803C27F0",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -893,7 +874,6 @@ ...@@ -893,7 +874,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F003C0477", "MSRValue": "0x3F003C0477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -905,7 +885,6 @@ ...@@ -905,7 +885,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0477", "MSRValue": "0x10003C0477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -917,7 +896,6 @@ ...@@ -917,7 +896,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0477", "MSRValue": "0x4003C0477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -929,7 +907,6 @@ ...@@ -929,7 +907,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0477", "MSRValue": "0x8003C0477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -941,7 +918,6 @@ ...@@ -941,7 +918,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1830000477", "MSRValue": "0x1830000477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -953,7 +929,6 @@ ...@@ -953,7 +929,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1030000477", "MSRValue": "0x1030000477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -965,7 +940,6 @@ ...@@ -965,7 +940,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x830000477", "MSRValue": "0x830000477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -977,7 +951,6 @@ ...@@ -977,7 +951,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000477", "MSRValue": "0x1008000477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -989,7 +962,6 @@ ...@@ -989,7 +962,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000477", "MSRValue": "0x808000477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -1001,7 +973,6 @@ ...@@ -1001,7 +973,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080800", "MSRValue": "0x80080800",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -1200,4 +1171,4 @@ ...@@ -1200,4 +1171,4 @@
"Speculative": "1", "Speculative": "1",
"UMask": "0x4" "UMask": "0x4"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
View file @ cbeee6ca
...@@ -475,10 +475,10 @@ ...@@ -475,10 +475,10 @@
"MetricName": "IpFarBranch" "MetricName": "IpFarBranch"
}, },
{ {
"BriefDescription": "C3 residency percent per core", "BriefDescription": "C1 residency percent per core",
"MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C3_Core_Residency" "MetricName": "C1_Core_Residency"
}, },
{ {
"BriefDescription": "C6 residency percent per core", "BriefDescription": "C6 residency percent per core",
...@@ -486,34 +486,16 @@ ...@@ -486,34 +486,16 @@
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C6_Core_Residency" "MetricName": "C6_Core_Residency"
}, },
{
"BriefDescription": "C7 residency percent per core",
"MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
"MetricGroup": "Power",
"MetricName": "C7_Core_Residency"
},
{ {
"BriefDescription": "C2 residency percent per package", "BriefDescription": "C2 residency percent per package",
"MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C2_Pkg_Residency" "MetricName": "C2_Pkg_Residency"
}, },
{
"BriefDescription": "C3 residency percent per package",
"MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
"MetricGroup": "Power",
"MetricName": "C3_Pkg_Residency"
},
{ {
"BriefDescription": "C6 residency percent per package", "BriefDescription": "C6 residency percent per package",
"MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
"MetricGroup": "Power", "MetricGroup": "Power",
"MetricName": "C6_Pkg_Residency" "MetricName": "C6_Pkg_Residency"
},
{
"BriefDescription": "C7 residency percent per package",
"MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
"MetricGroup": "Power",
"MetricName": "C7_Pkg_Residency"
} }
] ]
tools/perf/pmu-events/arch/x86/icelakex/memory.json
View file @ cbeee6ca
...@@ -159,7 +159,6 @@ ...@@ -159,7 +159,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00004", "MSRValue": "0x3FBFC00004",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -171,7 +170,6 @@ ...@@ -171,7 +170,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400004", "MSRValue": "0x3F84400004",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -183,7 +181,6 @@ ...@@ -183,7 +181,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00001", "MSRValue": "0x3FBFC00001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -195,7 +192,6 @@ ...@@ -195,7 +192,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400001", "MSRValue": "0x3F84400001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -207,7 +203,6 @@ ...@@ -207,7 +203,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FC00002", "MSRValue": "0x3F3FC00002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -219,7 +214,6 @@ ...@@ -219,7 +214,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F04400002", "MSRValue": "0x3F04400002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -231,7 +225,6 @@ ...@@ -231,7 +225,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00400", "MSRValue": "0x3FBFC00400",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -243,7 +236,6 @@ ...@@ -243,7 +236,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400400", "MSRValue": "0x3F84400400",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -255,7 +247,6 @@ ...@@ -255,7 +247,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x94002380", "MSRValue": "0x94002380",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -267,7 +258,6 @@ ...@@ -267,7 +258,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84002380", "MSRValue": "0x84002380",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -279,7 +269,6 @@ ...@@ -279,7 +269,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000002", "MSRValue": "0x84000002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -291,7 +280,6 @@ ...@@ -291,7 +280,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC08000", "MSRValue": "0x3FBFC08000",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -303,7 +291,6 @@ ...@@ -303,7 +291,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84408000", "MSRValue": "0x3F84408000",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -315,7 +302,6 @@ ...@@ -315,7 +302,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F844027F0", "MSRValue": "0x3F844027F0",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -327,7 +313,6 @@ ...@@ -327,7 +313,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FC00477", "MSRValue": "0x3F3FC00477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -339,7 +324,6 @@ ...@@ -339,7 +324,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F04400477", "MSRValue": "0x3F04400477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -351,7 +335,6 @@ ...@@ -351,7 +335,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x70CC00477", "MSRValue": "0x70CC00477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -363,7 +346,6 @@ ...@@ -363,7 +346,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x94000800", "MSRValue": "0x94000800",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -375,7 +357,6 @@ ...@@ -375,7 +357,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000800", "MSRValue": "0x84000800",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -565,4 +546,4 @@ ...@@ -565,4 +546,4 @@
"Speculative": "1", "Speculative": "1",
"UMask": "0x1" "UMask": "0x1"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/icelakex/other.json
View file @ cbeee6ca
[ [
{
"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.ANY",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x7"
},
{ {
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
...@@ -139,7 +127,6 @@ ...@@ -139,7 +127,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004", "MSRValue": "0x10004",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -151,7 +138,6 @@ ...@@ -151,7 +138,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000004", "MSRValue": "0x73C000004",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -163,7 +149,6 @@ ...@@ -163,7 +149,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000004", "MSRValue": "0x104000004",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -175,7 +160,6 @@ ...@@ -175,7 +160,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000004", "MSRValue": "0x708000004",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -187,7 +171,6 @@ ...@@ -187,7 +171,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001", "MSRValue": "0x10001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -199,7 +182,6 @@ ...@@ -199,7 +182,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000001", "MSRValue": "0x73C000001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -211,7 +193,6 @@ ...@@ -211,7 +193,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000001", "MSRValue": "0x104000001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -223,7 +204,6 @@ ...@@ -223,7 +204,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400001", "MSRValue": "0x100400001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -235,7 +215,6 @@ ...@@ -235,7 +215,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703C00001", "MSRValue": "0x703C00001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -247,7 +226,6 @@ ...@@ -247,7 +226,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x730000001", "MSRValue": "0x730000001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -259,7 +237,6 @@ ...@@ -259,7 +237,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703000001", "MSRValue": "0x703000001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -271,19 +248,17 @@ ...@@ -271,19 +248,17 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000001", "MSRValue": "0x708000001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts demand data reads that (IC) were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", "BriefDescription": "Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SNC_PMM", "EventName": "OCR.DEMAND_DATA_RD.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700800001", "MSRValue": "0x700800001",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -295,7 +270,6 @@ ...@@ -295,7 +270,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FFC0002", "MSRValue": "0x3F3FFC0002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -307,7 +281,6 @@ ...@@ -307,7 +281,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000002", "MSRValue": "0x73C000002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -319,7 +292,6 @@ ...@@ -319,7 +292,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000002", "MSRValue": "0x104000002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -331,7 +303,6 @@ ...@@ -331,7 +303,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400002", "MSRValue": "0x100400002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -343,7 +314,6 @@ ...@@ -343,7 +314,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703C00002", "MSRValue": "0x703C00002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -355,7 +325,6 @@ ...@@ -355,7 +325,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703000002", "MSRValue": "0x703000002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -367,19 +336,17 @@ ...@@ -367,19 +336,17 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000002", "MSRValue": "0x708000002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that (IC) were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SNC_PMM", "EventName": "OCR.DEMAND_RFO.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700800002", "MSRValue": "0x700800002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -391,7 +358,6 @@ ...@@ -391,7 +358,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000400", "MSRValue": "0x73C000400",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -403,7 +369,17 @@ ...@@ -403,7 +369,17 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000400", "MSRValue": "0x104000400",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch (which bring data to L2) that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10070",
"Offcore": "1",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -415,7 +391,6 @@ ...@@ -415,7 +391,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x12380", "MSRValue": "0x12380",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -427,7 +402,6 @@ ...@@ -427,7 +402,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90002380", "MSRValue": "0x90002380",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -439,7 +413,6 @@ ...@@ -439,7 +413,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000002", "MSRValue": "0x90000002",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -451,7 +424,6 @@ ...@@ -451,7 +424,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18000", "MSRValue": "0x18000",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -463,7 +435,6 @@ ...@@ -463,7 +435,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FFC0477", "MSRValue": "0x3F3FFC0477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -475,7 +446,6 @@ ...@@ -475,7 +446,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000477", "MSRValue": "0x73C000477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -487,7 +457,6 @@ ...@@ -487,7 +457,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000477", "MSRValue": "0x104000477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -499,7 +468,6 @@ ...@@ -499,7 +468,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400477", "MSRValue": "0x100400477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -511,7 +479,6 @@ ...@@ -511,7 +479,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x70C000477", "MSRValue": "0x70C000477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -523,7 +490,6 @@ ...@@ -523,7 +490,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700C00477", "MSRValue": "0x700C00477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -535,7 +501,6 @@ ...@@ -535,7 +501,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F33000477", "MSRValue": "0x3F33000477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -547,7 +512,6 @@ ...@@ -547,7 +512,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x730000477", "MSRValue": "0x730000477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -559,7 +523,6 @@ ...@@ -559,7 +523,6 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703000477", "MSRValue": "0x703000477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -571,19 +534,17 @@ ...@@ -571,19 +534,17 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000477", "MSRValue": "0x708000477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that (IC) were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_PMM", "EventName": "OCR.READS_TO_CORE.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700800477", "MSRValue": "0x700800477",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
}, },
...@@ -595,8 +556,7 @@ ...@@ -595,8 +556,7 @@
"MSRIndex": "0x1a6,0x1a7", "MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800", "MSRValue": "0x10800",
"Offcore": "1", "Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x1" "UMask": "0x1"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
View file @ cbeee6ca
...@@ -12,6 +12,18 @@ ...@@ -12,6 +12,18 @@
"Speculative": "1", "Speculative": "1",
"UMask": "0x9" "UMask": "0x9"
}, },
{
"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.ANY",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x7"
},
{ {
"BriefDescription": "All branch instructions retired.", "BriefDescription": "All branch instructions retired.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
...@@ -1076,4 +1088,4 @@ ...@@ -1076,4 +1088,4 @@
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"UMask": "0x2" "UMask": "0x2"
} }
] ]
\ No newline at end of file
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