Commit cca851d7 authored by Ben Dooks's avatar Ben Dooks Committed by Russell King

[ARM] 4790/1: S3C2412: Fix parent selection for msysclk.

The msysclk clock was checking for the wrong PLL for the
parent in s3c2412_setparent_msysclk(), trying the UPLL instead
of the MPLL output.

Also ensure the mpll and fclks are at the same rate at init time.
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent e95f52cd
...@@ -217,7 +217,7 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) ...@@ -217,7 +217,7 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
if (parent == &clk_mdivclk) if (parent == &clk_mdivclk)
clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL; clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
else if (parent == &clk_upll) else if (parent == &clk_mpll)
clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL; clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
else else
return -EINVAL; return -EINVAL;
......
...@@ -168,6 +168,8 @@ void __init s3c2412_init_clocks(int xtal) ...@@ -168,6 +168,8 @@ void __init s3c2412_init_clocks(int xtal)
fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2); fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
clk_mpll.rate = fclk;
tmp = __raw_readl(S3C2410_CLKDIVN); tmp = __raw_readl(S3C2410_CLKDIVN);
/* work out clock scalings */ /* work out clock scalings */
......
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