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Kirill Smelkov
linux
Commits
ccdf7e28
Commit
ccdf7e28
authored
Dec 02, 2018
by
Rob Clark
Browse files
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Browse Files
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Plain Diff
drm/msm: update generated headers
Signed-off-by:
Rob Clark
<
robdclark@gmail.com
>
parent
01665c64
Changes
8
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8 changed files
with
408 additions
and
45 deletions
+408
-45
drivers/gpu/drm/msm/adreno/a2xx.xml.h
drivers/gpu/drm/msm/adreno/a2xx.xml.h
+289
-9
drivers/gpu/drm/msm/adreno/a3xx.xml.h
drivers/gpu/drm/msm/adreno/a3xx.xml.h
+5
-5
drivers/gpu/drm/msm/adreno/a4xx.xml.h
drivers/gpu/drm/msm/adreno/a4xx.xml.h
+5
-5
drivers/gpu/drm/msm/adreno/a5xx.xml.h
drivers/gpu/drm/msm/adreno/a5xx.xml.h
+5
-5
drivers/gpu/drm/msm/adreno/a6xx.xml.h
drivers/gpu/drm/msm/adreno/a6xx.xml.h
+72
-6
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
+5
-5
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
+14
-5
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
+13
-5
No files found.
drivers/gpu/drm/msm/adreno/a2xx.xml.h
View file @
ccdf7e28
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
36805 bytes, from 2018-07-03 19:37:1
3)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
42463 bytes, from 2018-11-19 13:44:0
3)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
3634 bytes, from 2018-07-03 19:37:13
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
4201 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
2585 bytes, from 2018-10-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
3052 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
0-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
2-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
39581 bytes, from 2018-10-04 19:06:42
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
40790 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
...
@@ -239,7 +239,63 @@ enum sq_tex_swiz {
...
@@ -239,7 +239,63 @@ enum sq_tex_swiz {
enum
sq_tex_filter
{
enum
sq_tex_filter
{
SQ_TEX_FILTER_POINT
=
0
,
SQ_TEX_FILTER_POINT
=
0
,
SQ_TEX_FILTER_BILINEAR
=
1
,
SQ_TEX_FILTER_BILINEAR
=
1
,
SQ_TEX_FILTER_BICUBIC
=
2
,
SQ_TEX_FILTER_BASEMAP
=
2
,
SQ_TEX_FILTER_USE_FETCH_CONST
=
3
,
};
enum
sq_tex_aniso_filter
{
SQ_TEX_ANISO_FILTER_DISABLED
=
0
,
SQ_TEX_ANISO_FILTER_MAX_1_1
=
1
,
SQ_TEX_ANISO_FILTER_MAX_2_1
=
2
,
SQ_TEX_ANISO_FILTER_MAX_4_1
=
3
,
SQ_TEX_ANISO_FILTER_MAX_8_1
=
4
,
SQ_TEX_ANISO_FILTER_MAX_16_1
=
5
,
SQ_TEX_ANISO_FILTER_USE_FETCH_CONST
=
7
,
};
enum
sq_tex_dimension
{
SQ_TEX_DIMENSION_1D
=
0
,
SQ_TEX_DIMENSION_2D
=
1
,
SQ_TEX_DIMENSION_3D
=
2
,
SQ_TEX_DIMENSION_CUBE
=
3
,
};
enum
sq_tex_border_color
{
SQ_TEX_BORDER_COLOR_BLACK
=
0
,
SQ_TEX_BORDER_COLOR_WHITE
=
1
,
SQ_TEX_BORDER_COLOR_ACBYCR_BLACK
=
2
,
SQ_TEX_BORDER_COLOR_ACBCRY_BLACK
=
3
,
};
enum
sq_tex_sign
{
SQ_TEX_SIGN_UNISIGNED
=
0
,
SQ_TEX_SIGN_SIGNED
=
1
,
SQ_TEX_SIGN_UNISIGNED_BIASED
=
2
,
SQ_TEX_SIGN_GAMMA
=
3
,
};
enum
sq_tex_endian
{
SQ_TEX_ENDIAN_NONE
=
0
,
SQ_TEX_ENDIAN_8IN16
=
1
,
SQ_TEX_ENDIAN_8IN32
=
2
,
SQ_TEX_ENDIAN_16IN32
=
3
,
};
enum
sq_tex_clamp_policy
{
SQ_TEX_CLAMP_POLICY_D3D
=
0
,
SQ_TEX_CLAMP_POLICY_OGL
=
1
,
};
enum
sq_tex_num_format
{
SQ_TEX_NUM_FORMAT_FRAC
=
0
,
SQ_TEX_NUM_FORMAT_INT
=
1
,
};
enum
sq_tex_type
{
SQ_TEX_TYPE_0
=
0
,
SQ_TEX_TYPE_1
=
1
,
SQ_TEX_TYPE_2
=
2
,
SQ_TEX_TYPE_3
=
3
,
};
};
#define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001
#define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001
...
@@ -323,6 +379,18 @@ static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_cln
...
@@ -323,6 +379,18 @@ static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_cln
}
}
#define REG_A2XX_MH_MMU_VA_RANGE 0x00000041
#define REG_A2XX_MH_MMU_VA_RANGE 0x00000041
#define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK 0x00000fff
#define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT 0
static
inline
uint32_t
A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS
(
uint32_t
val
)
{
return
((
val
)
<<
A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT
)
&
A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK
;
}
#define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK 0xfffff000
#define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT 12
static
inline
uint32_t
A2XX_MH_MMU_VA_RANGE_VA_BASE
(
uint32_t
val
)
{
return
((
val
)
<<
A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT
)
&
A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK
;
}
#define REG_A2XX_MH_MMU_PT_BASE 0x00000042
#define REG_A2XX_MH_MMU_PT_BASE 0x00000042
...
@@ -331,6 +399,8 @@ static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_cln
...
@@ -331,6 +399,8 @@ static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_cln
#define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044
#define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044
#define REG_A2XX_MH_MMU_INVALIDATE 0x00000045
#define REG_A2XX_MH_MMU_INVALIDATE 0x00000045
#define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00000001
#define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC 0x00000002
#define REG_A2XX_MH_MMU_MPU_BASE 0x00000046
#define REG_A2XX_MH_MMU_MPU_BASE 0x00000046
...
@@ -389,12 +459,19 @@ static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_cln
...
@@ -389,12 +459,19 @@ static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_cln
#define REG_A2XX_RBBM_READ_ERROR 0x000003b3
#define REG_A2XX_RBBM_READ_ERROR 0x000003b3
#define REG_A2XX_RBBM_INT_CNTL 0x000003b4
#define REG_A2XX_RBBM_INT_CNTL 0x000003b4
#define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK 0x00000001
#define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK 0x00000002
#define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK 0x00080000
#define REG_A2XX_RBBM_INT_STATUS 0x000003b5
#define REG_A2XX_RBBM_INT_STATUS 0x000003b5
#define REG_A2XX_RBBM_INT_ACK 0x000003b6
#define REG_A2XX_RBBM_INT_ACK 0x000003b6
#define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7
#define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7
#define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT 0x00000020
#define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT 0x04000000
#define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT 0x40000000
#define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT 0x80000000
#define REG_A2XX_RBBM_PERIPHID1 0x000003f9
#define REG_A2XX_RBBM_PERIPHID1 0x000003f9
...
@@ -467,6 +544,19 @@ static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val)
...
@@ -467,6 +544,19 @@ static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val)
#define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000
#define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000
#define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000
#define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000
#define REG_A2XX_MH_INTERRUPT_MASK 0x00000a42
#define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR 0x00000001
#define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR 0x00000002
#define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT 0x00000004
#define REG_A2XX_MH_INTERRUPT_STATUS 0x00000a43
#define REG_A2XX_MH_INTERRUPT_CLEAR 0x00000a44
#define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1 0x00000a54
#define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2 0x00000a55
#define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01
#define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01
#define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
#define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
#define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0
#define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0
...
@@ -648,6 +738,18 @@ static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val
...
@@ -648,6 +738,18 @@ static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val
#define REG_A2XX_RB_DEBUG_DATA 0x00000f27
#define REG_A2XX_RB_DEBUG_DATA 0x00000f27
#define REG_A2XX_RB_SURFACE_INFO 0x00002000
#define REG_A2XX_RB_SURFACE_INFO 0x00002000
#define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK 0x00003fff
#define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT 0
static
inline
uint32_t
A2XX_RB_SURFACE_INFO_SURFACE_PITCH
(
uint32_t
val
)
{
return
((
val
)
<<
A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT
)
&
A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK
;
}
#define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK 0x0000c000
#define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT 14
static
inline
uint32_t
A2XX_RB_SURFACE_INFO_MSAA_SAMPLES
(
uint32_t
val
)
{
return
((
val
)
<<
A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT
)
&
A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK
;
}
#define REG_A2XX_RB_COLOR_INFO 0x00002001
#define REG_A2XX_RB_COLOR_INFO 0x00002001
#define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f
#define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f
...
@@ -679,7 +781,7 @@ static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val)
...
@@ -679,7 +781,7 @@ static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val)
#define A2XX_RB_COLOR_INFO_BASE__SHIFT 12
#define A2XX_RB_COLOR_INFO_BASE__SHIFT 12
static
inline
uint32_t
A2XX_RB_COLOR_INFO_BASE
(
uint32_t
val
)
static
inline
uint32_t
A2XX_RB_COLOR_INFO_BASE
(
uint32_t
val
)
{
{
return
((
val
>>
1
0
)
<<
A2XX_RB_COLOR_INFO_BASE__SHIFT
)
&
A2XX_RB_COLOR_INFO_BASE__MASK
;
return
((
val
>>
1
2
)
<<
A2XX_RB_COLOR_INFO_BASE__SHIFT
)
&
A2XX_RB_COLOR_INFO_BASE__MASK
;
}
}
#define REG_A2XX_RB_DEPTH_INFO 0x00002002
#define REG_A2XX_RB_DEPTH_INFO 0x00002002
...
@@ -693,7 +795,7 @@ static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_form
...
@@ -693,7 +795,7 @@ static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_form
#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
static
inline
uint32_t
A2XX_RB_DEPTH_INFO_DEPTH_BASE
(
uint32_t
val
)
static
inline
uint32_t
A2XX_RB_DEPTH_INFO_DEPTH_BASE
(
uint32_t
val
)
{
{
return
((
val
>>
1
0
)
<<
A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT
)
&
A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK
;
return
((
val
>>
1
2
)
<<
A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT
)
&
A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK
;
}
}
#define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005
#define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005
...
@@ -1757,6 +1859,36 @@ static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
...
@@ -1757,6 +1859,36 @@ static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
#define REG_A2XX_COHER_STATUS_PM4 0x00000a2b
#define REG_A2XX_COHER_STATUS_PM4 0x00000a2b
#define REG_A2XX_SQ_TEX_0 0x00000000
#define REG_A2XX_SQ_TEX_0 0x00000000
#define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003
#define A2XX_SQ_TEX_0_TYPE__SHIFT 0
static
inline
uint32_t
A2XX_SQ_TEX_0_TYPE
(
enum
sq_tex_type
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_0_TYPE__SHIFT
)
&
A2XX_SQ_TEX_0_TYPE__MASK
;
}
#define A2XX_SQ_TEX_0_SIGN_X__MASK 0x0000000c
#define A2XX_SQ_TEX_0_SIGN_X__SHIFT 2
static
inline
uint32_t
A2XX_SQ_TEX_0_SIGN_X
(
enum
sq_tex_sign
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_0_SIGN_X__SHIFT
)
&
A2XX_SQ_TEX_0_SIGN_X__MASK
;
}
#define A2XX_SQ_TEX_0_SIGN_Y__MASK 0x00000030
#define A2XX_SQ_TEX_0_SIGN_Y__SHIFT 4
static
inline
uint32_t
A2XX_SQ_TEX_0_SIGN_Y
(
enum
sq_tex_sign
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_0_SIGN_Y__SHIFT
)
&
A2XX_SQ_TEX_0_SIGN_Y__MASK
;
}
#define A2XX_SQ_TEX_0_SIGN_Z__MASK 0x000000c0
#define A2XX_SQ_TEX_0_SIGN_Z__SHIFT 6
static
inline
uint32_t
A2XX_SQ_TEX_0_SIGN_Z
(
enum
sq_tex_sign
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_0_SIGN_Z__SHIFT
)
&
A2XX_SQ_TEX_0_SIGN_Z__MASK
;
}
#define A2XX_SQ_TEX_0_SIGN_W__MASK 0x00000300
#define A2XX_SQ_TEX_0_SIGN_W__SHIFT 8
static
inline
uint32_t
A2XX_SQ_TEX_0_SIGN_W
(
enum
sq_tex_sign
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_0_SIGN_W__SHIFT
)
&
A2XX_SQ_TEX_0_SIGN_W__MASK
;
}
#define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00
#define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00
#define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10
#define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10
static
inline
uint32_t
A2XX_SQ_TEX_0_CLAMP_X
(
enum
sq_tex_clamp
val
)
static
inline
uint32_t
A2XX_SQ_TEX_0_CLAMP_X
(
enum
sq_tex_clamp
val
)
...
@@ -1775,14 +1907,46 @@ static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val)
...
@@ -1775,14 +1907,46 @@ static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val)
{
{
return
((
val
)
<<
A2XX_SQ_TEX_0_CLAMP_Z__SHIFT
)
&
A2XX_SQ_TEX_0_CLAMP_Z__MASK
;
return
((
val
)
<<
A2XX_SQ_TEX_0_CLAMP_Z__SHIFT
)
&
A2XX_SQ_TEX_0_CLAMP_Z__MASK
;
}
}
#define A2XX_SQ_TEX_0_PITCH__MASK 0x
f
fc00000
#define A2XX_SQ_TEX_0_PITCH__MASK 0x
7
fc00000
#define A2XX_SQ_TEX_0_PITCH__SHIFT 22
#define A2XX_SQ_TEX_0_PITCH__SHIFT 22
static
inline
uint32_t
A2XX_SQ_TEX_0_PITCH
(
uint32_t
val
)
static
inline
uint32_t
A2XX_SQ_TEX_0_PITCH
(
uint32_t
val
)
{
{
return
((
val
>>
5
)
<<
A2XX_SQ_TEX_0_PITCH__SHIFT
)
&
A2XX_SQ_TEX_0_PITCH__MASK
;
return
((
val
>>
5
)
<<
A2XX_SQ_TEX_0_PITCH__SHIFT
)
&
A2XX_SQ_TEX_0_PITCH__MASK
;
}
}
#define A2XX_SQ_TEX_0_TILED 0x00000002
#define REG_A2XX_SQ_TEX_1 0x00000001
#define REG_A2XX_SQ_TEX_1 0x00000001
#define A2XX_SQ_TEX_1_FORMAT__MASK 0x0000003f
#define A2XX_SQ_TEX_1_FORMAT__SHIFT 0
static
inline
uint32_t
A2XX_SQ_TEX_1_FORMAT
(
enum
a2xx_sq_surfaceformat
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_1_FORMAT__SHIFT
)
&
A2XX_SQ_TEX_1_FORMAT__MASK
;
}
#define A2XX_SQ_TEX_1_ENDIANNESS__MASK 0x000000c0
#define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT 6
static
inline
uint32_t
A2XX_SQ_TEX_1_ENDIANNESS
(
enum
sq_tex_endian
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_1_ENDIANNESS__SHIFT
)
&
A2XX_SQ_TEX_1_ENDIANNESS__MASK
;
}
#define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK 0x00000300
#define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT 8
static
inline
uint32_t
A2XX_SQ_TEX_1_REQUEST_SIZE
(
uint32_t
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT
)
&
A2XX_SQ_TEX_1_REQUEST_SIZE__MASK
;
}
#define A2XX_SQ_TEX_1_STACKED 0x00000400
#define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK 0x00000800
#define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT 11
static
inline
uint32_t
A2XX_SQ_TEX_1_CLAMP_POLICY
(
enum
sq_tex_clamp_policy
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT
)
&
A2XX_SQ_TEX_1_CLAMP_POLICY__MASK
;
}
#define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK 0xfffff000
#define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT 12
static
inline
uint32_t
A2XX_SQ_TEX_1_BASE_ADDRESS
(
uint32_t
val
)
{
return
((
val
>>
12
)
<<
A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT
)
&
A2XX_SQ_TEX_1_BASE_ADDRESS__MASK
;
}
#define REG_A2XX_SQ_TEX_2 0x00000002
#define REG_A2XX_SQ_TEX_2 0x00000002
#define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff
#define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff
...
@@ -1797,8 +1961,20 @@ static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val)
...
@@ -1797,8 +1961,20 @@ static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val)
{
{
return
((
val
)
<<
A2XX_SQ_TEX_2_HEIGHT__SHIFT
)
&
A2XX_SQ_TEX_2_HEIGHT__MASK
;
return
((
val
)
<<
A2XX_SQ_TEX_2_HEIGHT__SHIFT
)
&
A2XX_SQ_TEX_2_HEIGHT__MASK
;
}
}
#define A2XX_SQ_TEX_2_DEPTH__MASK 0xfc000000
#define A2XX_SQ_TEX_2_DEPTH__SHIFT 26
static
inline
uint32_t
A2XX_SQ_TEX_2_DEPTH
(
uint32_t
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_2_DEPTH__SHIFT
)
&
A2XX_SQ_TEX_2_DEPTH__MASK
;
}
#define REG_A2XX_SQ_TEX_3 0x00000003
#define REG_A2XX_SQ_TEX_3 0x00000003
#define A2XX_SQ_TEX_3_NUM_FORMAT__MASK 0x00000001
#define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT 0
static
inline
uint32_t
A2XX_SQ_TEX_3_NUM_FORMAT
(
enum
sq_tex_num_format
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT
)
&
A2XX_SQ_TEX_3_NUM_FORMAT__MASK
;
}
#define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e
#define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e
#define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1
#define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1
static
inline
uint32_t
A2XX_SQ_TEX_3_SWIZ_X
(
enum
sq_tex_swiz
val
)
static
inline
uint32_t
A2XX_SQ_TEX_3_SWIZ_X
(
enum
sq_tex_swiz
val
)
...
@@ -1823,6 +1999,12 @@ static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val)
...
@@ -1823,6 +1999,12 @@ static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val)
{
{
return
((
val
)
<<
A2XX_SQ_TEX_3_SWIZ_W__SHIFT
)
&
A2XX_SQ_TEX_3_SWIZ_W__MASK
;
return
((
val
)
<<
A2XX_SQ_TEX_3_SWIZ_W__SHIFT
)
&
A2XX_SQ_TEX_3_SWIZ_W__MASK
;
}
}
#define A2XX_SQ_TEX_3_EXP_ADJUST__MASK 0x0007e000
#define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT 13
static
inline
uint32_t
A2XX_SQ_TEX_3_EXP_ADJUST
(
uint32_t
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT
)
&
A2XX_SQ_TEX_3_EXP_ADJUST__MASK
;
}
#define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000
#define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000
#define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19
#define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19
static
inline
uint32_t
A2XX_SQ_TEX_3_XY_MAG_FILTER
(
enum
sq_tex_filter
val
)
static
inline
uint32_t
A2XX_SQ_TEX_3_XY_MAG_FILTER
(
enum
sq_tex_filter
val
)
...
@@ -1835,6 +2017,104 @@ static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val)
...
@@ -1835,6 +2017,104 @@ static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val)
{
{
return
((
val
)
<<
A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT
)
&
A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK
;
return
((
val
)
<<
A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT
)
&
A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK
;
}
}
#define A2XX_SQ_TEX_3_MIP_FILTER__MASK 0x01800000
#define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT 23
static
inline
uint32_t
A2XX_SQ_TEX_3_MIP_FILTER
(
enum
sq_tex_filter
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_3_MIP_FILTER__SHIFT
)
&
A2XX_SQ_TEX_3_MIP_FILTER__MASK
;
}
#define A2XX_SQ_TEX_3_ANISO_FILTER__MASK 0x0e000000
#define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT 25
static
inline
uint32_t
A2XX_SQ_TEX_3_ANISO_FILTER
(
enum
sq_tex_aniso_filter
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT
)
&
A2XX_SQ_TEX_3_ANISO_FILTER__MASK
;
}
#define A2XX_SQ_TEX_3_BORDER_SIZE__MASK 0x80000000
#define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT 31
static
inline
uint32_t
A2XX_SQ_TEX_3_BORDER_SIZE
(
uint32_t
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT
)
&
A2XX_SQ_TEX_3_BORDER_SIZE__MASK
;
}
#define REG_A2XX_SQ_TEX_4 0x00000004
#define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK 0x00000001
#define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT 0
static
inline
uint32_t
A2XX_SQ_TEX_4_VOL_MAG_FILTER
(
enum
sq_tex_filter
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT
)
&
A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK
;
}
#define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK 0x00000002
#define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT 1
static
inline
uint32_t
A2XX_SQ_TEX_4_VOL_MIN_FILTER
(
enum
sq_tex_filter
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT
)
&
A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK
;
}
#define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK 0x0000003c
#define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT 2
static
inline
uint32_t
A2XX_SQ_TEX_4_MIP_MIN_LEVEL
(
uint32_t
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT
)
&
A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK
;
}
#define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK 0x000003c0
#define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT 6
static
inline
uint32_t
A2XX_SQ_TEX_4_MIP_MAX_LEVEL
(
uint32_t
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT
)
&
A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK
;
}
#define A2XX_SQ_TEX_4_MAX_ANISO_WALK 0x00000400
#define A2XX_SQ_TEX_4_MIN_ANISO_WALK 0x00000800
#define A2XX_SQ_TEX_4_LOD_BIAS__MASK 0x003ff000
#define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT 12
static
inline
uint32_t
A2XX_SQ_TEX_4_LOD_BIAS
(
float
val
)
{
return
((((
int32_t
)(
val
*
32
.
0
)))
<<
A2XX_SQ_TEX_4_LOD_BIAS__SHIFT
)
&
A2XX_SQ_TEX_4_LOD_BIAS__MASK
;
}
#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK 0x07c00000
#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT 22
static
inline
uint32_t
A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H
(
uint32_t
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT
)
&
A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK
;
}
#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK 0xf8000000
#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT 27
static
inline
uint32_t
A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V
(
uint32_t
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT
)
&
A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK
;
}
#define REG_A2XX_SQ_TEX_5 0x00000005
#define A2XX_SQ_TEX_5_BORDER_COLOR__MASK 0x00000003
#define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT 0
static
inline
uint32_t
A2XX_SQ_TEX_5_BORDER_COLOR
(
enum
sq_tex_border_color
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT
)
&
A2XX_SQ_TEX_5_BORDER_COLOR__MASK
;
}
#define A2XX_SQ_TEX_5_FORCE_BCW_MAX 0x00000004
#define A2XX_SQ_TEX_5_TRI_CLAMP__MASK 0x00000018
#define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT 3
static
inline
uint32_t
A2XX_SQ_TEX_5_TRI_CLAMP
(
uint32_t
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT
)
&
A2XX_SQ_TEX_5_TRI_CLAMP__MASK
;
}
#define A2XX_SQ_TEX_5_ANISO_BIAS__MASK 0x000001e0
#define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT 5
static
inline
uint32_t
A2XX_SQ_TEX_5_ANISO_BIAS
(
float
val
)
{
return
((((
int32_t
)(
val
*
1
.
0
)))
<<
A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT
)
&
A2XX_SQ_TEX_5_ANISO_BIAS__MASK
;
}
#define A2XX_SQ_TEX_5_DIMENSION__MASK 0x00000600
#define A2XX_SQ_TEX_5_DIMENSION__SHIFT 9
static
inline
uint32_t
A2XX_SQ_TEX_5_DIMENSION
(
enum
sq_tex_dimension
val
)
{
return
((
val
)
<<
A2XX_SQ_TEX_5_DIMENSION__SHIFT
)
&
A2XX_SQ_TEX_5_DIMENSION__MASK
;
}
#define A2XX_SQ_TEX_5_PACKED_MIPS 0x00000800
#define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK 0xfffff000
#define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT 12
static
inline
uint32_t
A2XX_SQ_TEX_5_MIP_ADDRESS
(
uint32_t
val
)
{
return
((
val
>>
12
)
<<
A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT
)
&
A2XX_SQ_TEX_5_MIP_ADDRESS__MASK
;
}
#endif
/* A2XX_XML */
#endif
/* A2XX_XML */
drivers/gpu/drm/msm/adreno/a3xx.xml.h
View file @
ccdf7e28
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
36805 bytes, from 2018-07-03 19:37:1
3)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
42463 bytes, from 2018-11-19 13:44:0
3)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
3634 bytes, from 2018-07-03 19:37:13
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
4201 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
2585 bytes, from 2018-10-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
3052 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
0-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
2-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
39581 bytes, from 2018-10-04 19:06:42
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
40790 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
...
...
drivers/gpu/drm/msm/adreno/a4xx.xml.h
View file @
ccdf7e28
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
36805 bytes, from 2018-07-03 19:37:1
3)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
42463 bytes, from 2018-11-19 13:44:0
3)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
3634 bytes, from 2018-07-03 19:37:13
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
4201 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
2585 bytes, from 2018-10-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
3052 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
0-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
2-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
39581 bytes, from 2018-10-04 19:06:42
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
40790 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
...
...
drivers/gpu/drm/msm/adreno/a5xx.xml.h
View file @
ccdf7e28
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
36805 bytes, from 2018-07-03 19:37:1
3)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
42463 bytes, from 2018-11-19 13:44:0
3)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
3634 bytes, from 2018-07-03 19:37:13
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
4201 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
2585 bytes, from 2018-10-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
3052 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
0-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
2-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
39581 bytes, from 2018-10-04 19:06:42
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
40790 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
...
...
drivers/gpu/drm/msm/adreno/a6xx.xml.h
View file @
ccdf7e28
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
36805 bytes, from 2018-07-03 19:37:1
3)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
42463 bytes, from 2018-11-19 13:44:0
3)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
3634 bytes, from 2018-07-03 19:37:13
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
4201 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
2585 bytes, from 2018-10-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
3052 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
0-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
2-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
39581 bytes, from 2018-10-04 19:06:42
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
40790 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
...
@@ -501,7 +501,7 @@ enum a6xx_vfd_perfcounter_select {
...
@@ -501,7 +501,7 @@ enum a6xx_vfd_perfcounter_select {
PERF_VFDP_VS_STAGE_WAVES
=
22
,
PERF_VFDP_VS_STAGE_WAVES
=
22
,
};
};
enum
a6xx_h
sl
q_perfcounter_select
{
enum
a6xx_h
ls
q_perfcounter_select
{
PERF_HLSQ_BUSY_CYCLES
=
0
,
PERF_HLSQ_BUSY_CYCLES
=
0
,
PERF_HLSQ_STALL_CYCLES_UCHE
=
1
,
PERF_HLSQ_STALL_CYCLES_UCHE
=
1
,
PERF_HLSQ_STALL_CYCLES_SP_STATE
=
2
,
PERF_HLSQ_STALL_CYCLES_SP_STATE
=
2
,
...
@@ -2959,6 +2959,8 @@ static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
...
@@ -2959,6 +2959,8 @@ static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
#define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
#define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
#define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
#define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
#define A6XX_GRAS_LRZ_CNTL_UNK3 0x00000008
#define A6XX_GRAS_LRZ_CNTL_UNK4 0x00000010
#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
...
@@ -2997,6 +2999,13 @@ static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
...
@@ -2997,6 +2999,13 @@ static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
#define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
#define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
#define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
#define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
static
inline
uint32_t
A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT
(
enum
a6xx_color_fmt
val
)
{
return
((
val
)
<<
A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT
)
&
A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK
;
}
#define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000
#define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
#define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
#define A6XX_GRAS_2D_SRC_TL_X_X__MASK 0x00ffff00
#define A6XX_GRAS_2D_SRC_TL_X_X__MASK 0x00ffff00
...
@@ -3449,6 +3458,7 @@ static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
...
@@ -3449,6 +3458,7 @@ static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
return
((
val
)
<<
A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT
)
&
A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK
;
return
((
val
)
<<
A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT
)
&
A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK
;
}
}
#define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
#define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
#define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
static
inline
uint32_t
A6XX_RB_BLEND_CNTL_SAMPLE_MASK
(
uint32_t
val
)
static
inline
uint32_t
A6XX_RB_BLEND_CNTL_SAMPLE_MASK
(
uint32_t
val
)
...
@@ -3642,6 +3652,9 @@ static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
...
@@ -3642,6 +3652,9 @@ static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
#define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891
#define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891
#define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
#define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
#define REG_A6XX_RB_LRZ_CNTL 0x00008898
#define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001
#define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0
#define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0
#define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1
#define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1
...
@@ -3674,6 +3687,14 @@ static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
...
@@ -3674,6 +3687,14 @@ static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
return
((
val
)
<<
A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT
)
&
A6XX_RB_BLIT_SCISSOR_BR_Y__MASK
;
return
((
val
)
<<
A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT
)
&
A6XX_RB_BLIT_SCISSOR_BR_Y__MASK
;
}
}
#define REG_A6XX_RB_MSAA_CNTL 0x000088d5
#define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018
#define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3
static
inline
uint32_t
A6XX_RB_MSAA_CNTL_SAMPLES
(
enum
a3xx_msaa_samples
val
)
{
return
((
val
)
<<
A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT
)
&
A6XX_RB_MSAA_CNTL_SAMPLES__MASK
;
}
#define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6
#define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6
#define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7
#define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7
...
@@ -3684,6 +3705,12 @@ static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
...
@@ -3684,6 +3705,12 @@ static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
return
((
val
)
<<
A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT
)
&
A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK
;
return
((
val
)
<<
A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT
)
&
A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK
;
}
}
#define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004
#define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004
#define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018
#define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3
static
inline
uint32_t
A6XX_RB_BLIT_DST_INFO_SAMPLES
(
enum
a3xx_msaa_samples
val
)
{
return
((
val
)
<<
A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT
)
&
A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK
;
}
#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80
#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80
#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7
#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7
static
inline
uint32_t
A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT
(
enum
a6xx_color_fmt
val
)
static
inline
uint32_t
A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT
(
enum
a6xx_color_fmt
val
)
...
@@ -3780,6 +3807,9 @@ static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val
...
@@ -3780,6 +3807,9 @@ static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val
{
{
return
((
val
)
<<
A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT
)
&
A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK
;
return
((
val
)
<<
A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT
)
&
A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK
;
}
}
#define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000
#define REG_A6XX_RB_UNKNOWN_8C01 0x00008c01
#define REG_A6XX_RB_2D_DST_INFO 0x00008c17
#define REG_A6XX_RB_2D_DST_INFO 0x00008c17
#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
...
@@ -4465,6 +4495,7 @@ static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
...
@@ -4465,6 +4495,7 @@ static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
#define REG_A6XX_SP_BLEND_CNTL 0x0000a989
#define REG_A6XX_SP_BLEND_CNTL 0x0000a989
#define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001
#define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001
#define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
#define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
#define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
#define REG_A6XX_SP_SRGB_CNTL 0x0000a98a
#define REG_A6XX_SP_SRGB_CNTL 0x0000a98a
#define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001
#define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001
...
@@ -4643,6 +4674,8 @@ static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
...
@@ -4643,6 +4674,8 @@ static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
#define REG_A6XX_SP_UNKNOWN_AB20 0x0000ab20
#define REG_A6XX_SP_UNKNOWN_AB20 0x0000ab20
#define REG_A6XX_SP_UNKNOWN_ACC0 0x0000acc0
#define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
#define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
#define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03
#define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03
...
@@ -4700,11 +4733,34 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap va
...
@@ -4700,11 +4733,34 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap va
return
((
val
)
<<
A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT
)
&
A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK
;
return
((
val
)
<<
A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT
)
&
A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK
;
}
}
#define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000
#define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000
#define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
#define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0
static
inline
uint32_t
A6XX_SP_PS_2D_SRC_SIZE_WIDTH
(
uint32_t
val
)
{
return
((
val
)
<<
A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT
)
&
A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK
;
}
#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000
#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15
static
inline
uint32_t
A6XX_SP_PS_2D_SRC_SIZE_HEIGHT
(
uint32_t
val
)
{
return
((
val
)
<<
A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT
)
&
A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK
;
}
#define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2
#define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2
#define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3
#define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3
#define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00
#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
static
inline
uint32_t
A6XX_SP_PS_2D_SRC_PITCH_PITCH
(
uint32_t
val
)
{
return
((
val
>>
6
)
<<
A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT
)
&
A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK
;
}
#define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca
#define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca
#define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb
#define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb
...
@@ -5033,6 +5089,12 @@ static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
...
@@ -5033,6 +5089,12 @@ static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
{
{
return
((
val
)
<<
A6XX_TEX_CONST_0_MIPLVLS__SHIFT
)
&
A6XX_TEX_CONST_0_MIPLVLS__MASK
;
return
((
val
)
<<
A6XX_TEX_CONST_0_MIPLVLS__SHIFT
)
&
A6XX_TEX_CONST_0_MIPLVLS__MASK
;
}
}
#define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
#define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20
static
inline
uint32_t
A6XX_TEX_CONST_0_SAMPLES
(
enum
a3xx_msaa_samples
val
)
{
return
((
val
)
<<
A6XX_TEX_CONST_0_SAMPLES__SHIFT
)
&
A6XX_TEX_CONST_0_SAMPLES__MASK
;
}
#define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000
#define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000
#define A6XX_TEX_CONST_0_FMT__SHIFT 22
#define A6XX_TEX_CONST_0_FMT__SHIFT 22
static
inline
uint32_t
A6XX_TEX_CONST_0_FMT
(
enum
a6xx_tex_fmt
val
)
static
inline
uint32_t
A6XX_TEX_CONST_0_FMT
(
enum
a6xx_tex_fmt
val
)
...
@@ -5365,5 +5427,9 @@ static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
...
@@ -5365,5 +5427,9 @@ static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030
#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001
#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002
#endif
/* A6XX_XML */
#endif
/* A6XX_XML */
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
View file @
ccdf7e28
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
36805 bytes, from 2018-07-03 19:37:1
3)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
42463 bytes, from 2018-11-19 13:44:0
3)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
3634 bytes, from 2018-07-03 19:37:13
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
4201 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
2585 bytes, from 2018-10-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
3052 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
0-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
2-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
39581 bytes, from 2018-10-04 19:06:42
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
40790 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
...
...
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
View file @
ccdf7e28
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
36805 bytes, from 2018-07-03 19:37:1
3)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
42463 bytes, from 2018-11-19 13:44:0
3)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
3634 bytes, from 2018-07-03 19:37:13
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
4201 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
2585 bytes, from 2018-10-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
3052 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
0-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
2-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
39581 bytes, from 2018-10-04 19:06:42
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
40790 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
...
@@ -339,6 +339,15 @@ static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
...
@@ -339,6 +339,15 @@ static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
#define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed
#define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed
#define REG_AXXX_CP_INT_CNTL 0x000001f2
#define REG_AXXX_CP_INT_CNTL 0x000001f2
#define AXXX_CP_INT_CNTL_SW_INT_MASK 0x00080000
#define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK 0x00800000
#define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK 0x01000000
#define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK 0x02000000
#define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK 0x04000000
#define AXXX_CP_INT_CNTL_IB_ERROR_MASK 0x08000000
#define AXXX_CP_INT_CNTL_IB2_INT_MASK 0x20000000
#define AXXX_CP_INT_CNTL_IB1_INT_MASK 0x40000000
#define AXXX_CP_INT_CNTL_RB_INT_MASK 0x80000000
#define REG_AXXX_CP_INT_STATUS 0x000001f3
#define REG_AXXX_CP_INT_STATUS 0x000001f3
...
...
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
View file @
ccdf7e28
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
...
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
36805 bytes, from 2018-07-03 19:37:1
3)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml (
42463 bytes, from 2018-11-19 13:44:0
3)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
3634 bytes, from 2018-07-03 19:37:13
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 1
4201 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
2585 bytes, from 2018-10-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 4
3052 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
0-04 19:06:37
)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-1
2-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
39581 bytes, from 2018-10-04 19:06:42
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 1
40790 bytes, from 2018-12-02 17:29:54
)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
...
@@ -108,6 +108,13 @@ enum pc_di_src_sel {
...
@@ -108,6 +108,13 @@ enum pc_di_src_sel {
DI_SRC_SEL_RESERVED
=
3
,
DI_SRC_SEL_RESERVED
=
3
,
};
};
enum
pc_di_face_cull_sel
{
DI_FACE_CULL_NONE
=
0
,
DI_FACE_CULL_FETCH
=
1
,
DI_FACE_BACKFACE_CULL
=
2
,
DI_FACE_FRONTFACE_CULL
=
3
,
};
enum
pc_di_index_size
{
enum
pc_di_index_size
{
INDEX_SIZE_IGN
=
0
,
INDEX_SIZE_IGN
=
0
,
INDEX_SIZE_16_BIT
=
0
,
INDEX_SIZE_16_BIT
=
0
,
...
@@ -356,6 +363,7 @@ enum a6xx_render_mode {
...
@@ -356,6 +363,7 @@ enum a6xx_render_mode {
RM6_GMEM
=
4
,
RM6_GMEM
=
4
,
RM6_BLIT2D
=
5
,
RM6_BLIT2D
=
5
,
RM6_RESOLVE
=
6
,
RM6_RESOLVE
=
6
,
RM6_BLIT2DSCALE
=
12
,
};
};
enum
pseudo_reg
{
enum
pseudo_reg
{
...
...
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