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Commit cd5f48a7 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'samsung-dt-2' of... 

Merge tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup3

Merge "Samsung 2nd DT updates for v3.15" from Kukjin Kim:

- add DT entry for AHCI SATA and SATA PHY with using generic
  PHY framework for exynos5250 and arndale, smdk5250 boards.
- add SSS DT node for exynos5420 and exynos5250
- remove leftover spi0 node for smdk5250 board
- add ADC and thermistor nodes for exynos4412-trats2 board
- move common irq-combiner node for exynos4x12 from exynos4212
  and exynos4412
- add ADC, PMU and GPS_ALIVE power domain nodes for exynos4x12

Note that based on previous tags/samsung-dt and tags/exynos-clk

* tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: dts: enable ahci sata and sata phy for exynos5250
  ARM: dts: add dt node for sss module for exynos5250/5420
  ARM: dts: Remove leftover spi0 node for smdk5250
  ARM: dts: Add ADC and themistor nodes for exynos4412-trats2
  ARM: dts: Move common dt data for interrupt combiner controller for exynos4x12
  ARM: dts: Add GPS_ALIVE power domain for exynos4x12
  ARM: dts: Add PMU dt data to support PMU for exynos4x12
  ARM: dts: Add ADC's dt data to read raw data for exynos4x12
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 2b23e9a5 ba0d7ed3
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Documentation/devicetree/bindings/ata/exynos-sata-phy.txt deleted 100644 → 0
View file @ 2b23e9a5
* Samsung SATA PHY Controller
SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
Each SATA PHY controller should have its own node.
Required properties:
- compatible : compatible list, contains "samsung,exynos5-sata-phy"
- reg : <registers mapping>
Example:
sata@ffe07000 {
compatible = "samsung,exynos5-sata-phy";
reg = <0xffe07000 0x1000>;
};
Documentation/devicetree/bindings/ata/exynos-sata.txt
View file @ cd5f48a7
......@@ -4,14 +4,21 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
Required properties:
- compatible : compatible list, contains "samsung,exynos5-sata"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
- samsung,sata-freq : <frequency in MHz>
- compatible : compatible list, contains "samsung,exynos5-sata"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
- samsung,sata-freq : <frequency in MHz>
- phys : as mentioned in phy-bindings.txt
- phy-names : as mentioned in phy-bindings.txt
Example:
sata@ffe08000 {
compatible = "samsung,exynos5-sata";
reg = <0xffe08000 0x1000>;
interrupts = <115>;
};
sata@122f0000 {
compatible = "snps,dwc-ahci";
samsung,sata-freq = <66>;
reg = <0x122f0000 0x1ff>;
interrupts = <0 115 0>;
clocks = <&clock 277>, <&clock 143>;
clock-names = "sata", "sclk_sata";
phys = <&sata_phy>;
phy-names = "sata-phy";
};
Documentation/devicetree/bindings/phy/samsung-phy.txt
View file @ cd5f48a7
......@@ -20,3 +20,39 @@ Required properties:
- compatible : should be "samsung,exynos5250-dp-video-phy";
- reg : offset and length of the Display Port PHY register set;
- #phy-cells : from the generic PHY bindings, must be 0;
Samsung SATA PHY Controller
---------------------------
SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
Each SATA PHY controller should have its own node.
Required properties:
- compatible : compatible list, contains "samsung,exynos5250-sata-phy"
- reg : offset and length of the SATA PHY register set;
- #phy-cells : from the generic phy bindings;
Example:
sata_phy: sata-phy@12170000 {
compatible = "samsung,exynos5250-sata-phy";
reg = <0x12170000 0x1ff>;
clocks = <&clock 287>;
clock-names = "sata_phyctrl";
#phy-cells = <0>;
samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
samsung,syscon-phandle = <&pmu_syscon>;
};
Device-Tree bindings for sataphy i2c client driver
--------------------------------------------------
Required properties:
compatible: Should be "samsung,exynos-sataphy-i2c"
- reg: I2C address of the sataphy i2c device.
Example:
sata_phy_i2c:sata-phy@38 {
compatible = "samsung,exynos-sataphy-i2c";
reg = <0x38>;
};
arch/arm/boot/dts/exynos4.dtsi
View file @ cd5f48a7
......@@ -86,6 +86,11 @@ pd_gps: gps-power-domain@10023CE0 {
reg = <0x10023CE0 0x20>;
};
pd_gps_alive: gps-alive-power-domain@10023D00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023D00 0x20>;
};
gic: interrupt-controller@10490000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
......
arch/arm/boot/dts/exynos4212.dtsi
View file @ cd5f48a7
......@@ -22,16 +22,11 @@
/ {
compatible = "samsung,exynos4212";
gic: interrupt-controller@10490000 {
cpu-offset = <0x8000>;
combiner: interrupt-controller@10440000 {
samsung,combiner-nr = <18>;
};
interrupt-controller@10440000 {
samsung,combiner-nr = <18>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
<0 107 0>, <0 108 0>;
gic: interrupt-controller@10490000 {
cpu-offset = <0x8000>;
};
};
arch/arm/boot/dts/exynos4412-trats2.dts
View file @ cd5f48a7
......@@ -106,6 +106,11 @@ key-power {
};
};
adc: adc@126C0000 {
vdd-supply = <&ldo3_reg>;
status = "okay";
};
i2c@13890000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-slave-addr = <0x10>;
......@@ -589,4 +594,20 @@ is_s5k6a3_ep: endpoint {
};
};
};
thermistor-ap@0 {
compatible = "ntc,ncp15wb473";
pullup-uv = <1800000>; /* VCC_1.8V_AP */
pullup-ohm = <100000>; /* 100K */
pulldown-ohm = <100000>; /* 100K */
io-channels = <&adc 1>; /* AP temperature */
};
thermistor-battery@1 {
compatible = "ntc,ncp15wb473";
pullup-uv = <1800000>; /* VCC_1.8V_AP */
pullup-ohm = <100000>; /* 100K */
pulldown-ohm = <100000>; /* 100K */
io-channels = <&adc 2>; /* Battery temperature */
};
};
arch/arm/boot/dts/exynos4412.dtsi
View file @ cd5f48a7
......@@ -22,17 +22,11 @@
/ {
compatible = "samsung,exynos4412";
gic: interrupt-controller@10490000 {
cpu-offset = <0x4000>;
};
interrupt-controller@10440000 {
combiner: interrupt-controller@10440000 {
samsung,combiner-nr = <20>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
<0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
};
gic: interrupt-controller@10490000 {
cpu-offset = <0x4000>;
};
};
arch/arm/boot/dts/exynos4x12.dtsi
View file @ cd5f48a7
......@@ -31,6 +31,12 @@ aliases {
mshc0 = &mshc_0;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&combiner>;
interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
};
pd_isp: isp-power-domain@10023CA0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
......@@ -62,6 +68,14 @@ mct_map: mct-map {
};
};
combiner: interrupt-controller@10440000 {
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
<0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
};
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11400000 0x1000>;
......@@ -80,6 +94,18 @@ wakup_eint: wakeup-interrupt-controller {
};
};
adc: adc@126C0000 {
compatible = "samsung,exynos-adc-v1";
reg = <0x126C0000 0x100>, <0x10020718 0x4>;
interrupt-parent = <&combiner>;
interrupts = <10 3>;
clocks = <&clock CLK_TSADC>;
clock-names = "adc";
#io-channel-cells = <1>;
io-channel-ranges;
status = "disabled";
};
pinctrl_2: pinctrl@03860000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x03860000 0x1000>;
......
arch/arm/boot/dts/exynos5250-arndale.dts
View file @ cd5f48a7
......@@ -374,6 +374,27 @@ hdmiphy@38 {
};
};
i2c@121D0000 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <40000>;
samsung,i2c-slave-addr = <0x38>;
sata_phy_i2c:sata-phy@38 {
compatible = "samsung,exynos-sataphy-i2c";
reg = <0x38>;
};
};
sata@122F0000 {
status = "okay";
};
sata-phy@12170000 {
status = "okay";
samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
};
mmc_0: mmc@12200000 {
status = "okay";
num-slots = <1>;
......
arch/arm/boot/dts/exynos5250-smdk5250.dts
View file @ cd5f48a7
......@@ -242,16 +242,12 @@ i2c@121D0000 {
samsung,i2c-slave-addr = <0x38>;
status = "okay";
sata-phy {
compatible = "samsung,sata-phy";
sata_phy_i2c:sata-phy@38 {
compatible = "samsung,exynos-sataphy-i2c";
reg = <0x38>;
};
};
sata@122F0000 {
samsung,sata-freq = <66>;
};
i2c@12C80000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
......@@ -274,6 +270,15 @@ hdmiphy@38 {
};
};
sata@122F0000 {
status = "okay";
};
sata-phy@12170000 {
status = "okay";
samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
};
mmc@12200000 {
status = "okay";
num-slots = <1>;
......@@ -310,10 +315,6 @@ slot@0 {
};
};
spi_0: spi@12d20000 {
status = "disabled";
};
spi_1: spi@12d30000 {
status = "okay";
......
arch/arm/boot/dts/exynos5250.dtsi
View file @ cd5f48a7
......@@ -47,6 +47,7 @@ aliases {
i2c6 = &i2c_6;
i2c7 = &i2c_7;
i2c8 = &i2c_8;
i2c9 = &i2c_9;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
......@@ -235,16 +236,25 @@ serial@12C30000 {
};
sata@122F0000 {
compatible = "samsung,exynos5-sata-ahci";
compatible = "snps,dwc-ahci";
samsung,sata-freq = <66>;
reg = <0x122F0000 0x1ff>;
interrupts = <0 115 0>;
clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
clock-names = "sata", "sclk_sata";
phys = <&sata_phy>;
phy-names = "sata-phy";
status = "disabled";
};
sata-phy@12170000 {
compatible = "samsung,exynos5-sata-phy";
sata_phy: sata-phy@12170000 {
compatible = "samsung,exynos5250-sata-phy";
reg = <0x12170000 0x1ff>;
clocks = <&clock 287>;
clock-names = "sata_phyctrl";
#phy-cells = <0>;
samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
};
i2c_0: i2c@12C60000 {
......@@ -362,7 +372,7 @@ i2c_8: i2c@12CE0000 {
status = "disabled";
};
i2c@121D0000 {
i2c_9: i2c@121D0000 {
compatible = "samsung,exynos5-sata-phy-i2c";
reg = <0x121D0000 0x100>;
#address-cells = <1>;
......@@ -718,4 +728,12 @@ adc: adc@12D10000 {
io-channel-ranges;
status = "disabled";
};
sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x10000>;
interrupts = <0 112 0>;
clocks = <&clock 348>;
clock-names = "secss";
};
};
arch/arm/boot/dts/exynos5420.dtsi
View file @ cd5f48a7
......@@ -723,4 +723,13 @@ watchdog@101D0000 {
clock-names = "watchdog";
samsung,syscon-phandle = <&pmu_system_controller>;
};
sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x10000>;
interrupts = <0 112 0>;
clocks = <&clock 471>;
clock-names = "secss";
samsung,power-domain = <&g2d_pd>;
};
};
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