Commit cda45691 authored by Neil Armstrong's avatar Neil Armstrong Committed by Jerome Brunet

dt-bindings: clk: meson: add sm1 periph clock controller bindings

Update the documentation to support clock driver for the Amlogic SM1 SoC
and expose the GP1, DSU and the CPU 1, 2 & 3 clocks.

SM1 clock tree is very close, the main differences are :
- each CPU core can achieve a different frequency, albeit a common PLL
- a similar tree as the clock tree has been added for the DynamIQ Shared
  Unit
- has a new GP1 PLL used for the DynamIQ Shared Unit
- SM1 has additional clocks like for CSI, NanoQ an other components
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 0688587a
...@@ -11,6 +11,7 @@ Required Properties: ...@@ -11,6 +11,7 @@ Required Properties:
"amlogic,axg-clkc" for AXG SoC. "amlogic,axg-clkc" for AXG SoC.
"amlogic,g12a-clkc" for G12A SoC. "amlogic,g12a-clkc" for G12A SoC.
"amlogic,g12b-clkc" for G12B SoC. "amlogic,g12b-clkc" for G12B SoC.
"amlogic,sm1-clkc" for SM1 SoC.
- clocks : list of clock phandle, one for each entry clock-names. - clocks : list of clock phandle, one for each entry clock-names.
- clock-names : should contain the following: - clock-names : should contain the following:
* "xtal": the platform xtal * "xtal": the platform xtal
......
...@@ -138,5 +138,10 @@ ...@@ -138,5 +138,10 @@
#define CLKID_VDEC_HEVCF 210 #define CLKID_VDEC_HEVCF 210
#define CLKID_TS 212 #define CLKID_TS 212
#define CLKID_CPUB_CLK 224 #define CLKID_CPUB_CLK 224
#define CLKID_GP1_PLL 243
#define CLKID_DSU_CLK 252
#define CLKID_CPU1_CLK 253
#define CLKID_CPU2_CLK 254
#define CLKID_CPU3_CLK 255
#endif /* __G12A_CLKC_H */ #endif /* __G12A_CLKC_H */
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