Commit cdc5ffc4 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'for-5.3/libata-20190708' of git://git.kernel.dk/linux-block

Pull libata updates from Jens Axboe:
 "These are the changes that are reviewed, tested, and queued up for
  this merge window. This contains:

   - Removal of redundant memset after dmam_alloc_coherent (Fuqian)

   - Expand blacklist check for ST1000LM024, making it independent of
     firmware version (Hans)

   - Request sense fix (Tejun)

   - ahci_sunxi FIFO fix (Uenal)"

* tag 'for-5.3/libata-20190708' of git://git.kernel.dk/linux-block:
  drivers: ata: ahci_sunxi: Increased SATA/AHCI DMA TX/RX FIFOs
  libata: Drop firmware version check from the ST1000LM024 quirk
  ata: sata_sil24: Remove call to memset after dmam_alloc_coherent
  ata:sata_qstor: Remove call to memset after dmam_alloc_coherent
  ata: sata_nv: Remove call to memset after dmam_alloc_coherent
  ata: pdc_adma: Remove call to memset after dmam_alloc_coherent
  ata: libahci: Remove call to memset after dmam_alloc_coherent
  ata: acard-ahci: Remove call to memset after dmam_alloc_coherent
  libata: don't request sense data on !ZAC ATA devices
parents 3b99107f 120357ea
...@@ -344,7 +344,6 @@ static int acard_ahci_port_start(struct ata_port *ap) ...@@ -344,7 +344,6 @@ static int acard_ahci_port_start(struct ata_port *ap)
mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
if (!mem) if (!mem)
return -ENOMEM; return -ENOMEM;
memset(mem, 0, dma_sz);
/* /*
* First item in chunk of DMA memory: 32-slot command table, * First item in chunk of DMA memory: 32-slot command table,
......
...@@ -149,8 +149,51 @@ static void ahci_sunxi_start_engine(struct ata_port *ap) ...@@ -149,8 +149,51 @@ static void ahci_sunxi_start_engine(struct ata_port *ap)
void __iomem *port_mmio = ahci_port_base(ap); void __iomem *port_mmio = ahci_port_base(ap);
struct ahci_host_priv *hpriv = ap->host->private_data; struct ahci_host_priv *hpriv = ap->host->private_data;
/* Setup DMA before DMA start */ /* Setup DMA before DMA start
sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400); *
* NOTE: A similar SoC with SATA/AHCI by Texas Instruments documents
* this Vendor Specific Port (P0DMACR, aka PxDMACR) in its
* User's Guide document (TMS320C674x/OMAP-L1x Processor
* Serial ATA (SATA) Controller, Literature Number: SPRUGJ8C,
* March 2011, Chapter 4.33 Port DMA Control Register (P0DMACR),
* p.68, https://www.ti.com/lit/ug/sprugj8c/sprugj8c.pdf)
* as equivalent to the following struct:
*
* struct AHCI_P0DMACR_t
* {
* unsigned TXTS : 4;
* unsigned RXTS : 4;
* unsigned TXABL : 4;
* unsigned RXABL : 4;
* unsigned Reserved : 16;
* };
*
* TXTS: Transmit Transaction Size (TX_TRANSACTION_SIZE).
* This field defines the DMA transaction size in DWORDs for
* transmit (system bus read, device write) operation. [...]
*
* RXTS: Receive Transaction Size (RX_TRANSACTION_SIZE).
* This field defines the Port DMA transaction size in DWORDs
* for receive (system bus write, device read) operation. [...]
*
* TXABL: Transmit Burst Limit.
* This field allows software to limit the VBUSP master read
* burst size. [...]
*
* RXABL: Receive Burst Limit.
* Allows software to limit the VBUSP master write burst
* size. [...]
*
* Reserved: Reserved.
*
*
* NOTE: According to the above document, the following alternative
* to the code below could perhaps be a better option
* (or preparation) for possible further improvements later:
* sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff,
* 0x00000033);
*/
sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff, 0x00004433);
/* Start DMA */ /* Start DMA */
sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START); sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
......
...@@ -2365,7 +2365,6 @@ static int ahci_port_start(struct ata_port *ap) ...@@ -2365,7 +2365,6 @@ static int ahci_port_start(struct ata_port *ap)
mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
if (!mem) if (!mem)
return -ENOMEM; return -ENOMEM;
memset(mem, 0, dma_sz);
/* /*
* First item in chunk of DMA memory: 32-slot command table, * First item in chunk of DMA memory: 32-slot command table,
......
...@@ -4462,9 +4462,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { ...@@ -4462,9 +4462,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
/* drives which fail FPDMA_AA activation (some may freeze afterwards) /* drives which fail FPDMA_AA activation (some may freeze afterwards)
the ST disks also have LPM issues */ the ST disks also have LPM issues */
{ "ST1000LM024 HN-M101MBB", "2AR10001", ATA_HORKAGE_BROKEN_FPDMA_AA | { "ST1000LM024 HN-M101MBB", NULL, ATA_HORKAGE_BROKEN_FPDMA_AA |
ATA_HORKAGE_NOLPM, },
{ "ST1000LM024 HN-M101MBB", "2BA30001", ATA_HORKAGE_BROKEN_FPDMA_AA |
ATA_HORKAGE_NOLPM, }, ATA_HORKAGE_NOLPM, },
{ "VB0250EAVER", "HPG7", ATA_HORKAGE_BROKEN_FPDMA_AA }, { "VB0250EAVER", "HPG7", ATA_HORKAGE_BROKEN_FPDMA_AA },
......
...@@ -1469,7 +1469,7 @@ static int ata_eh_read_log_10h(struct ata_device *dev, ...@@ -1469,7 +1469,7 @@ static int ata_eh_read_log_10h(struct ata_device *dev,
tf->hob_lbah = buf[10]; tf->hob_lbah = buf[10];
tf->nsect = buf[12]; tf->nsect = buf[12];
tf->hob_nsect = buf[13]; tf->hob_nsect = buf[13];
if (ata_id_has_ncq_autosense(dev->id)) if (dev->class == ATA_DEV_ZAC && ata_id_has_ncq_autosense(dev->id))
tf->auxiliary = buf[14] << 16 | buf[15] << 8 | buf[16]; tf->auxiliary = buf[14] << 16 | buf[15] << 8 | buf[16];
return 0; return 0;
...@@ -1716,7 +1716,8 @@ void ata_eh_analyze_ncq_error(struct ata_link *link) ...@@ -1716,7 +1716,8 @@ void ata_eh_analyze_ncq_error(struct ata_link *link)
memcpy(&qc->result_tf, &tf, sizeof(tf)); memcpy(&qc->result_tf, &tf, sizeof(tf));
qc->result_tf.flags = ATA_TFLAG_ISADDR | ATA_TFLAG_LBA | ATA_TFLAG_LBA48; qc->result_tf.flags = ATA_TFLAG_ISADDR | ATA_TFLAG_LBA | ATA_TFLAG_LBA48;
qc->err_mask |= AC_ERR_DEV | AC_ERR_NCQ; qc->err_mask |= AC_ERR_DEV | AC_ERR_NCQ;
if ((qc->result_tf.command & ATA_SENSE) || qc->result_tf.auxiliary) { if (dev->class == ATA_DEV_ZAC &&
((qc->result_tf.command & ATA_SENSE) || qc->result_tf.auxiliary)) {
char sense_key, asc, ascq; char sense_key, asc, ascq;
sense_key = (qc->result_tf.auxiliary >> 16) & 0xff; sense_key = (qc->result_tf.auxiliary >> 16) & 0xff;
...@@ -1770,10 +1771,11 @@ static unsigned int ata_eh_analyze_tf(struct ata_queued_cmd *qc, ...@@ -1770,10 +1771,11 @@ static unsigned int ata_eh_analyze_tf(struct ata_queued_cmd *qc,
} }
switch (qc->dev->class) { switch (qc->dev->class) {
case ATA_DEV_ATA:
case ATA_DEV_ZAC: case ATA_DEV_ZAC:
if (stat & ATA_SENSE) if (stat & ATA_SENSE)
ata_eh_request_sense(qc, qc->scsicmd); ata_eh_request_sense(qc, qc->scsicmd);
/* fall through */
case ATA_DEV_ATA:
if (err & ATA_ICRC) if (err & ATA_ICRC)
qc->err_mask |= AC_ERR_ATA_BUS; qc->err_mask |= AC_ERR_ATA_BUS;
if (err & (ATA_UNC | ATA_AMNF)) if (err & (ATA_UNC | ATA_AMNF))
......
...@@ -550,7 +550,6 @@ static int adma_port_start(struct ata_port *ap) ...@@ -550,7 +550,6 @@ static int adma_port_start(struct ata_port *ap)
(u32)pp->pkt_dma); (u32)pp->pkt_dma);
return -ENOMEM; return -ENOMEM;
} }
memset(pp->pkt, 0, ADMA_PKT_BYTES);
ap->private_data = pp; ap->private_data = pp;
adma_reinit_engine(ap); adma_reinit_engine(ap);
return 0; return 0;
......
...@@ -1136,7 +1136,6 @@ static int nv_adma_port_start(struct ata_port *ap) ...@@ -1136,7 +1136,6 @@ static int nv_adma_port_start(struct ata_port *ap)
&mem_dma, GFP_KERNEL); &mem_dma, GFP_KERNEL);
if (!mem) if (!mem)
return -ENOMEM; return -ENOMEM;
memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ);
/* /*
* First item in chunk of DMA memory: * First item in chunk of DMA memory:
...@@ -1946,7 +1945,6 @@ static int nv_swncq_port_start(struct ata_port *ap) ...@@ -1946,7 +1945,6 @@ static int nv_swncq_port_start(struct ata_port *ap)
&pp->prd_dma, GFP_KERNEL); &pp->prd_dma, GFP_KERNEL);
if (!pp->prd) if (!pp->prd)
return -ENOMEM; return -ENOMEM;
memset(pp->prd, 0, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE);
ap->private_data = pp; ap->private_data = pp;
pp->sactive_block = ap->ioaddr.scr_addr + 4 * SCR_ACTIVE; pp->sactive_block = ap->ioaddr.scr_addr + 4 * SCR_ACTIVE;
......
...@@ -477,7 +477,6 @@ static int qs_port_start(struct ata_port *ap) ...@@ -477,7 +477,6 @@ static int qs_port_start(struct ata_port *ap)
GFP_KERNEL); GFP_KERNEL);
if (!pp->pkt) if (!pp->pkt)
return -ENOMEM; return -ENOMEM;
memset(pp->pkt, 0, QS_PKT_BYTES);
ap->private_data = pp; ap->private_data = pp;
qs_enter_reg_mode(ap); qs_enter_reg_mode(ap);
......
...@@ -1202,7 +1202,6 @@ static int sil24_port_start(struct ata_port *ap) ...@@ -1202,7 +1202,6 @@ static int sil24_port_start(struct ata_port *ap)
cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
if (!cb) if (!cb)
return -ENOMEM; return -ENOMEM;
memset(cb, 0, cb_size);
pp->cmd_block = cb; pp->cmd_block = cb;
pp->cmd_block_dma = cb_dma; pp->cmd_block_dma = cb_dma;
......
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