Commit cdd30545 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'devicetree-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull DeviceTree changes from Rob Herring:

 - DT unittests for I2C probing and overlays from Pantelis Antoniou

 - Remove DT unittest dependency on OF_DYNAMIC from Gaurav Minocha

 - Add Tegra compatible strings missing for newer parts from Paul
   Walmsley

 - Various vendor prefix additions

* tag 'devicetree-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  of: Add vendor prefix for OmniVision Technologies
  of: Use ovti for Omnivision
  of: Add vendor prefix for Truly Semiconductors Limited
  of: Add vendor prefix for Himax Technologies Inc.
  of/fdt: fix sparse warning
  of: unitest: Add I2C overlay unit tests.
  Documentation: DT: document compatible string existence requirement
  Documentation: DT bindings: add nvidia, tegra132-denver compatible string
  Documentation: DT bindings: add more Tegra chip compatible strings
  of: EXPORT_SYMBOL_GPL of_property_read_u64_array
  of: Fix brace position for struct of_device_id definition
  of/unittest: Remove obsolete code
  dt-bindings: use isil prefix for Intersil in vendor-prefixes.txt
  Add AD Holdings Plc. to vendor-prefixes.
  dt-bindings: Add Silicon Mitus vendor prefix
  Removes OF_UNITTEST dependency on OF_DYNAMIC config symbol
  pinctrl: fix up device tree bindings
  DT: Vendors: Add Everspin
  doc: add bindings document for altera fpga manager
  drivers: of: Export of_reserved_mem_device_{init,release}
parents 42cf0f20 3c3c8e36
...@@ -175,6 +175,7 @@ nodes to be present and contain the properties described below. ...@@ -175,6 +175,7 @@ nodes to be present and contain the properties described below.
"marvell,pj4a" "marvell,pj4a"
"marvell,pj4b" "marvell,pj4b"
"marvell,sheeva-v5" "marvell,sheeva-v5"
"nvidia,tegra132-denver"
"qcom,krait" "qcom,krait"
"qcom,scorpion" "qcom,scorpion"
- enable-method - enable-method
......
NVIDIA Tegra AHB NVIDIA Tegra AHB
Required properties: Required properties:
- compatible : "nvidia,tegra20-ahb" or "nvidia,tegra30-ahb" - compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For
Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
'"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
tegra132, or tegra210.
- reg : Should contain 1 register ranges(address and length) - reg : Should contain 1 register ranges(address and length)
Example: Example:
......
...@@ -6,7 +6,11 @@ modes. It provides power-gating controllers for SoC and CPU power-islands. ...@@ -6,7 +6,11 @@ modes. It provides power-gating controllers for SoC and CPU power-islands.
Required properties: Required properties:
- name : Should be pmc - name : Should be pmc
- compatible : Should contain "nvidia,tegra<chip>-pmc". - compatible : For Tegra20, must contain "nvidia,tegra20-pmc". For Tegra30,
must contain "nvidia,tegra30-pmc". For Tegra114, must contain
"nvidia,tegra114-pmc". For Tegra124, must contain "nvidia,tegra124-pmc".
Otherwise, must contain "nvidia,<chip>-pmc", plus at least one of the
above, where <chip> is tegra132.
- reg : Offset and length of the register set for the device - reg : Offset and length of the register set for the device
- clocks : Must contain an entry for each entry in clock-names. - clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details. See ../clocks/clock-bindings.txt for details.
......
Tegra124 SoC SATA AHCI controller Tegra124 SoC SATA AHCI controller
Required properties : Required properties :
- compatible : "nvidia,tegra124-ahci". - compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise,
must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
is tegra132.
- reg : Should contain 2 entries: - reg : Should contain 2 entries:
- AHCI register set (SATA BAR5) - AHCI register set (SATA BAR5)
- SATA register set - SATA register set
......
Altera SOCFPGA FPGA Manager
Required properties:
- compatible : should contain "altr,socfpga-fpga-mgr"
- reg : base address and size for memory mapped io.
- The first index is for FPGA manager register access.
- The second index is for writing FPGA configuration data.
- interrupts : interrupt for the FPGA Manager device.
Example:
hps_0_fpgamgr: fpgamgr@0xff706000 {
compatible = "altr,socfpga-fpga-mgr";
reg = <0xFF706000 0x1000
0xFFB90000 0x1000>;
interrupts = <0 175 4>;
};
NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block. NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
Required properties: Required properties:
- compatible : should be: - compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
"nvidia,tegra20-efuse" must contain "nvidia,tegra30-efuse". For Tegra114, must contain
"nvidia,tegra30-efuse" "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
"nvidia,tegra114-efuse" Otherwise, must contain "nvidia,<chip>-efuse", plus one of the above, where
"nvidia,tegra124-efuse" <chip> is tegra132.
Details: Details:
nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
due to a hardware bug. Tegra20 also lacks certain information which is due to a hardware bug. Tegra20 also lacks certain information which is
......
...@@ -197,7 +197,9 @@ of the following host1x client modules: ...@@ -197,7 +197,9 @@ of the following host1x client modules:
- sor: serial output resource - sor: serial output resource
Required properties: Required properties:
- compatible: "nvidia,tegra124-sor" - compatible: For Tegra124, must contain "nvidia,tegra124-sor". Otherwise,
must contain '"nvidia,<chip>-sor", "nvidia,tegra124-sor"', where <chip>
is tegra132.
- reg: Physical base address and length of the controller's registers. - reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller. - interrupts: The interrupt outputs from the controller.
- clocks: Must contain an entry for each entry in clock-names. - clocks: Must contain an entry for each entry in clock-names.
...@@ -222,7 +224,9 @@ of the following host1x client modules: ...@@ -222,7 +224,9 @@ of the following host1x client modules:
- nvidia,dpaux: phandle to a DispayPort AUX interface - nvidia,dpaux: phandle to a DispayPort AUX interface
- dpaux: DisplayPort AUX interface - dpaux: DisplayPort AUX interface
- compatible: "nvidia,tegra124-dpaux" - compatible: For Tegra124, must contain "nvidia,tegra124-dpaux". Otherwise,
must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where
<chip> is tegra132.
- reg: Physical base address and length of the controller's registers. - reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller. - interrupts: The interrupt outputs from the controller.
- clocks: Must contain an entry for each entry in clock-names. - clocks: Must contain an entry for each entry in clock-names.
......
NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver. NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
Required properties: Required properties:
- compatible : should be: - compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
"nvidia,tegra114-i2c" "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
"nvidia,tegra30-i2c" For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
"nvidia,tegra20-i2c" "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
"nvidia,tegra20-i2c-dvc" tegra124, tegra132, or tegra210.
Details of compatible are as follows: Details of compatible are as follows:
nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
controller. This only support master mode of I2C communication. Register controller. This only support master mode of I2C communication. Register
......
...@@ -38,7 +38,7 @@ Example: ...@@ -38,7 +38,7 @@ Example:
i2c1: i2c@f0018000 { i2c1: i2c@f0018000 {
ov2640: camera@0x30 { ov2640: camera@0x30 {
compatible = "omnivision,ov2640"; compatible = "ovti,ov2640";
reg = <0x30>; reg = <0x30>;
port { port {
......
...@@ -162,7 +162,7 @@ pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0. ...@@ -162,7 +162,7 @@ pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0.
i2c0: i2c@0xfff20000 { i2c0: i2c@0xfff20000 {
... ...
ov772x_1: camera@0x21 { ov772x_1: camera@0x21 {
compatible = "omnivision,ov772x"; compatible = "ovti,ov772x";
reg = <0x21>; reg = <0x21>;
vddio-supply = <&regulator1>; vddio-supply = <&regulator1>;
vddcore-supply = <&regulator2>; vddcore-supply = <&regulator2>;
......
NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block
Required properties: Required properties:
- compatible : should be: - compatible : For Tegra20, must be "nvidia,tegra20-apbmisc". For Tegra30,
"nvidia,tegra20-apbmisc" must be "nvidia,tegra30-apbmisc". Otherwise, must contain
"nvidia,tegra30-apbmisc" "nvidia,<chip>-apbmisc", plus one of the above, where <chip> is tegra114,
"nvidia,tegra114-apbmisc" tegra124, tegra132.
"nvidia,tegra124-apbmisc"
- reg: Should contain 2 entries: the first entry gives the physical address - reg: Should contain 2 entries: the first entry gives the physical address
and length of the registers which contain revision and debug features. and length of the registers which contain revision and debug features.
The second entry gives the physical address and length of the The second entry gives the physical address and length of the
......
...@@ -7,7 +7,11 @@ This file documents differences between the core properties described ...@@ -7,7 +7,11 @@ This file documents differences between the core properties described
by mmc.txt and the properties used by the sdhci-tegra driver. by mmc.txt and the properties used by the sdhci-tegra driver.
Required properties: Required properties:
- compatible : Should be "nvidia,<chip>-sdhci" - compatible : For Tegra20, must contain "nvidia,tegra20-sdhci".
For Tegra30, must contain "nvidia,tegra30-sdhci". For Tegra114,
must contain "nvidia,tegra114-sdhci". For Tegra124, must contain
"nvidia,tegra124-sdhci". Otherwise, must contain "nvidia,<chip>-sdhci",
plus one of the above, where <chip> is tegra132 or tegra210.
- clocks : Must contain one entry, for the module clock. - clocks : Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details. See ../clocks/clock-bindings.txt for details.
- resets : Must contain an entry for each entry in reset-names. - resets : Must contain an entry for each entry in reset-names.
......
NVIDIA Tegra PCIe controller NVIDIA Tegra PCIe controller
Required properties: Required properties:
- compatible: Must be one of: - compatible: For Tegra20, must contain "nvidia,tegra20-pcie". For Tegra30,
- "nvidia,tegra20-pcie" "nvidia,tegra30-pcie". For Tegra124, must contain "nvidia,tegra124-pcie".
- "nvidia,tegra30-pcie" Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where
- "nvidia,tegra124-pcie" <chip> is tegra132 or tegra210.
- device_type: Must be "pci" - device_type: Must be "pci"
- reg: A list of physical base address and length for each set of controller - reg: A list of physical base address and length for each set of controller
registers. Must contain an entry for each entry in the reg-names property. registers. Must contain an entry for each entry in the reg-names property.
......
...@@ -6,7 +6,8 @@ nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as ...@@ -6,7 +6,8 @@ nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
a baseline, and only documents the differences between the two bindings. a baseline, and only documents the differences between the two bindings.
Required properties: Required properties:
- compatible: "nvidia,tegra124-pinmux" - compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For
Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
- reg: Should contain a list of base address and size pairs for: - reg: Should contain a list of base address and size pairs for:
-- first entry - the drive strength and pad control registers. -- first entry - the drive strength and pad control registers.
-- second entry - the pinmux registers -- second entry - the pinmux registers
......
...@@ -13,7 +13,9 @@ how to describe and reference PHYs in device trees. ...@@ -13,7 +13,9 @@ how to describe and reference PHYs in device trees.
Required properties: Required properties:
-------------------- --------------------
- compatible: should be "nvidia,tegra124-xusb-padctl" - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
"nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
- reg: Physical base address and length of the controller's registers. - reg: Physical base address and length of the controller's registers.
- resets: Must contain an entry for each entry in reset-names. - resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details. See ../reset/reset.txt for details.
......
Tegra SoC PWFM controller Tegra SoC PWFM controller
Required properties: Required properties:
- compatible: should be one of: - compatible: For Tegra20, must contain "nvidia,tegra20-pwm". For Tegra30,
- "nvidia,tegra20-pwm" must contain "nvidia,tegra30-pwm". Otherwise, must contain
- "nvidia,tegra30-pwm" "nvidia,<chip>-pwm", plus one of the above, where <chip> is tegra114,
tegra124, tegra132, or tegra210.
- reg: physical base address and length of the controller's registers - reg: physical base address and length of the controller's registers
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of - #pwm-cells: should be 2. See pwm.txt in this directory for a description of
the cells format. the cells format.
......
...@@ -6,7 +6,9 @@ state. ...@@ -6,7 +6,9 @@ state.
Required properties: Required properties:
- compatible : should be "nvidia,tegra20-rtc". - compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise,
must contain '"nvidia,<chip>-rtc", "nvidia,tegra20-rtc"', where <chip>
can be tegra30, tegra114, tegra124, or tegra132.
- reg : Specifies base physical address and size of the registers. - reg : Specifies base physical address and size of the registers.
- interrupts : A single interrupt specifier. - interrupts : A single interrupt specifier.
- clocks : Must contain one entry, for the module clock. - clocks : Must contain one entry, for the module clock.
......
...@@ -8,7 +8,10 @@ Required properties: ...@@ -8,7 +8,10 @@ Required properties:
- "ns16550" - "ns16550"
- "ns16750" - "ns16750"
- "ns16850" - "ns16850"
- "nvidia,tegra20-uart" - For Tegra20, must contain "nvidia,tegra20-uart"
- For other Tegra, must contain '"nvidia,<chip>-uart",
"nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
tegra132, or tegra210.
- "nxp,lpc3220-uart" - "nxp,lpc3220-uart"
- "ralink,rt2880-uart" - "ralink,rt2880-uart"
- "ibm,qpace-nwp-serial" - "ibm,qpace-nwp-serial"
......
NVIDIA Tegra30 AHUB (Audio Hub) NVIDIA Tegra30 AHUB (Audio Hub)
Required properties: Required properties:
- compatible : "nvidia,tegra30-ahub", "nvidia,tegra114-ahub", etc. - compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114,
must contain "nvidia,tegra114-ahub". For Tegra124, must contain
"nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub",
plus at least one of the above, where <chip> is tegra132.
- reg : Should contain the register physical address and length for each of - reg : Should contain the register physical address and length for each of
the AHUB's register blocks. the AHUB's register blocks.
- Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks. - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
......
NVIDIA Tegra30 HDA controller NVIDIA Tegra30 HDA controller
Required properties: Required properties:
- compatible : "nvidia,tegra30-hda" - compatible : For Tegra30, must contain "nvidia,tegra30-hda". Otherwise,
must contain '"nvidia,<chip>-hda", "nvidia,tegra30-hda"', where <chip> is
tegra114, tegra124, or tegra132.
- reg : Should contain the HDA registers location and length. - reg : Should contain the HDA registers location and length.
- interrupts : The interrupt from the HDA controller. - interrupts : The interrupt from the HDA controller.
- clocks : Must contain an entry for each required entry in clock-names. - clocks : Must contain an entry for each required entry in clock-names.
......
NVIDIA Tegra30 I2S controller NVIDIA Tegra30 I2S controller
Required properties: Required properties:
- compatible : "nvidia,tegra30-i2s" - compatible : For Tegra30, must contain "nvidia,tegra30-i2s". For Tegra124,
must contain "nvidia,tegra124-i2s". Otherwise, must contain
"nvidia,<chip>-i2s" plus at least one of the above, where <chip> is
tegra114 or tegra132.
- reg : Should contain I2S registers location and length - reg : Should contain I2S registers location and length
- clocks : Must contain one entry, for the module clock. - clocks : Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details. See ../clocks/clock-bindings.txt for details.
......
NVIDIA Tegra114 SPI controller. NVIDIA Tegra114 SPI controller.
Required properties: Required properties:
- compatible : should be "nvidia,tegra114-spi". - compatible : For Tegra114, must contain "nvidia,tegra114-spi".
Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
<chip> is tegra124, tegra132, or tegra210.
- reg: Should contain SPI registers location and length. - reg: Should contain SPI registers location and length.
- interrupts: Should contain SPI interrupts. - interrupts: Should contain SPI interrupts.
- clock-names : Must include the following entries: - clock-names : Must include the following entries:
......
...@@ -15,6 +15,29 @@ I. For patch submitters ...@@ -15,6 +15,29 @@ I. For patch submitters
3) The Documentation/ portion of the patch should come in the series before 3) The Documentation/ portion of the patch should come in the series before
the code implementing the binding. the code implementing the binding.
4) Any compatible strings used in a chip or board DTS file must be
previously documented in the corresponding DT binding text file
in Documentation/devicetree/bindings. This rule applies even if
the Linux device driver does not yet match on the compatible
string. [ checkpatch will emit warnings if this step is not
followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864
("checkpatch: add DT compatible string documentation checks"). ]
5) The wildcard "<chip>" may be used in compatible strings, as in
the following example:
- compatible: Must contain '"nvidia,<chip>-pcie",
"nvidia,tegra20-pcie"' where <chip> is tegra30, tegra132, ...
As in the above example, the known values of "<chip>" should be
documented if it is used.
6) If a documented compatible string is not yet matched by the
driver, the documentation should also include a compatible
string that is matched by the driver (as in the "nvidia,tegra20-pcie"
example above).
II. For kernel maintainers II. For kernel maintainers
1) If you aren't comfortable reviewing a given binding, reply to it and ask 1) If you aren't comfortable reviewing a given binding, reply to it and ask
......
...@@ -7,7 +7,9 @@ notifications. It is also used to manage emergency shutdown in an ...@@ -7,7 +7,9 @@ notifications. It is also used to manage emergency shutdown in an
overheating situation. overheating situation.
Required properties : Required properties :
- compatible : "nvidia,tegra124-soctherm". - compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
For Tegra132, must contain "nvidia,tegra132-soctherm".
For Tegra210, must contain "nvidia,tegra210-soctherm".
- reg : Should contain 1 entry: - reg : Should contain 1 entry:
- SOCTHERM register set - SOCTHERM register set
- interrupts : Defines the interrupt used by SOCTHERM - interrupts : Defines the interrupt used by SOCTHERM
......
...@@ -6,7 +6,9 @@ trigger a legacy watchdog reset. ...@@ -6,7 +6,9 @@ trigger a legacy watchdog reset.
Required properties: Required properties:
- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer". - compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise,
must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where
<chip> is tegra124 or tegra132.
- reg : Specifies base physical address and size of the registers. - reg : Specifies base physical address and size of the registers.
- interrupts : A list of 6 interrupts; one per each of timer channels 1 - interrupts : A list of 6 interrupts; one per each of timer channels 1
through 5, and one for the shared interrupt for the remaining channels. through 5, and one for the shared interrupt for the remaining channels.
......
* OF selftest platform device 1) OF selftest platform device
** selftest ** selftest
...@@ -12,3 +12,60 @@ Example: ...@@ -12,3 +12,60 @@ Example:
compatible = "selftest"; compatible = "selftest";
status = "okay"; status = "okay";
}; };
2) OF selftest i2c adapter platform device
** platform device unittest adapter
Required properties:
- compatible: must be selftest-i2c-bus
Children nodes contain selftest i2c devices.
Example:
selftest-i2c-bus {
compatible = "selftest-i2c-bus";
status = "okay";
};
3) OF selftest i2c device
** I2C selftest device
Required properties:
- compatible: must be selftest-i2c-dev
All other properties are optional
Example:
selftest-i2c-dev {
compatible = "selftest-i2c-dev";
status = "okay";
};
4) OF selftest i2c mux device
** I2C selftest mux
Required properties:
- compatible: must be selftest-i2c-mux
Children nodes contain selftest i2c bus nodes per channel.
Example:
selftest-i2c-mux {
compatible = "selftest-i2c-mux";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
channel-0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
i2c-dev {
reg = <8>;
compatible = "selftest-i2c-dev";
status = "okay";
};
};
};
...@@ -6,7 +6,10 @@ Practice : Universal Serial Bus" with the following modifications ...@@ -6,7 +6,10 @@ Practice : Universal Serial Bus" with the following modifications
and additions : and additions :
Required properties : Required properties :
- compatible : Should be "nvidia,tegra20-ehci". - compatible : For Tegra20, must contain "nvidia,tegra20-ehci".
For Tegra30, must contain "nvidia,tegra30-ehci". Otherwise, must contain
"nvidia,<chip>-ehci" plus at least one of the above, where <chip> is
tegra114, tegra124, tegra132, or tegra210.
- nvidia,phy : phandle of the PHY that the controller is connected to. - nvidia,phy : phandle of the PHY that the controller is connected to.
- clocks : Must contain one entry, for the module clock. - clocks : Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details. See ../clocks/clock-bindings.txt for details.
......
...@@ -3,7 +3,10 @@ Tegra SOC USB PHY ...@@ -3,7 +3,10 @@ Tegra SOC USB PHY
The device node for Tegra SOC USB PHY: The device node for Tegra SOC USB PHY:
Required properties : Required properties :
- compatible : Should be "nvidia,tegra<chip>-usb-phy". - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
"nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
tegra114, tegra124, tegra132, or tegra210.
- reg : Defines the following set of registers, in the order listed: - reg : Defines the following set of registers, in the order listed:
- The PHY's own register set. - The PHY's own register set.
Always present. Always present.
......
...@@ -7,6 +7,7 @@ abilis Abilis Systems ...@@ -7,6 +7,7 @@ abilis Abilis Systems
active-semi Active-Semi International Inc active-semi Active-Semi International Inc
ad Avionic Design GmbH ad Avionic Design GmbH
adapteva Adapteva, Inc. adapteva Adapteva, Inc.
adh AD Holdings Plc.
adi Analog Devices, Inc. adi Analog Devices, Inc.
aeroflexgaisler Aeroflex Gaisler AB aeroflexgaisler Aeroflex Gaisler AB
allwinner Allwinner Technology Co., Ltd. allwinner Allwinner Technology Co., Ltd.
...@@ -57,6 +58,7 @@ est ESTeem Wireless Modems ...@@ -57,6 +58,7 @@ est ESTeem Wireless Modems
ettus NI Ettus Research ettus NI Ettus Research
eukrea Eukréa Electromatique eukrea Eukréa Electromatique
everest Everest Semiconductor Co. Ltd. everest Everest Semiconductor Co. Ltd.
everspin Everspin Technologies, Inc.
excito Excito excito Excito
fcs Fairchild Semiconductor fcs Fairchild Semiconductor
fsl Freescale Semiconductor fsl Freescale Semiconductor
...@@ -70,6 +72,7 @@ gumstix Gumstix, Inc. ...@@ -70,6 +72,7 @@ gumstix Gumstix, Inc.
gw Gateworks Corporation gw Gateworks Corporation
hannstar HannStar Display Corporation hannstar HannStar Display Corporation
haoyu Haoyu Microelectronic Co. Ltd. haoyu Haoyu Microelectronic Co. Ltd.
himax Himax Technologies, Inc.
hisilicon Hisilicon Limited. hisilicon Hisilicon Limited.
hit Hitachi Ltd. hit Hitachi Ltd.
honeywell Honeywell honeywell Honeywell
...@@ -83,8 +86,7 @@ innolux Innolux Corporation ...@@ -83,8 +86,7 @@ innolux Innolux Corporation
intel Intel Corporation intel Intel Corporation
intercontrol Inter Control Group intercontrol Inter Control Group
isee ISEE 2007 S.L. isee ISEE 2007 S.L.
isil Intersil (deprecated, use isl) isil Intersil
isl Intersil
karo Ka-Ro electronics GmbH karo Ka-Ro electronics GmbH
keymile Keymile GmbH keymile Keymile GmbH
lacie LaCie lacie LaCie
...@@ -119,6 +121,7 @@ nvidia NVIDIA ...@@ -119,6 +121,7 @@ nvidia NVIDIA
nxp NXP Semiconductors nxp NXP Semiconductors
onnn ON Semiconductor Corp. onnn ON Semiconductor Corp.
opencores OpenCores.org opencores OpenCores.org
ovti OmniVision Technologies
panasonic Panasonic Corporation panasonic Panasonic Corporation
pericom Pericom Technology Inc. pericom Pericom Technology Inc.
phytec PHYTEC Messtechnik GmbH phytec PHYTEC Messtechnik GmbH
...@@ -146,6 +149,7 @@ seagate Seagate Technology PLC ...@@ -146,6 +149,7 @@ seagate Seagate Technology PLC
semtech Semtech Corporation semtech Semtech Corporation
sil Silicon Image sil Silicon Image
silabs Silicon Laboratories silabs Silicon Laboratories
siliconmitus Silicon Mitus, Inc.
simtek simtek
sii Seiko Instruments, Inc. sii Seiko Instruments, Inc.
silergy Silergy Corp. silergy Silergy Corp.
...@@ -167,6 +171,7 @@ tlm Trusted Logic Mobility ...@@ -167,6 +171,7 @@ tlm Trusted Logic Mobility
toradex Toradex AG toradex Toradex AG
toshiba Toshiba Corporation toshiba Toshiba Corporation
toumaz Toumaz toumaz Toumaz
truly Truly Semiconductors Limited
usi Universal Scientific Industrial Co., Ltd. usi Universal Scientific Industrial Co., Ltd.
v3 V3 Semiconductor v3 V3 Semiconductor
variscite Variscite Ltd. variscite Variscite Ltd.
......
...@@ -10,7 +10,6 @@ menu "Device Tree and Open Firmware support" ...@@ -10,7 +10,6 @@ menu "Device Tree and Open Firmware support"
config OF_UNITTEST config OF_UNITTEST
bool "Device Tree runtime unit tests" bool "Device Tree runtime unit tests"
depends on OF_IRQ && OF_EARLY_FLATTREE depends on OF_IRQ && OF_EARLY_FLATTREE
select OF_DYNAMIC
select OF_RESOLVE select OF_RESOLVE
help help
This option builds in test cases for the device tree infrastructure This option builds in test cases for the device tree infrastructure
......
...@@ -1303,6 +1303,7 @@ int of_property_read_u64_array(const struct device_node *np, ...@@ -1303,6 +1303,7 @@ int of_property_read_u64_array(const struct device_node *np,
} }
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(of_property_read_u64_array);
/** /**
* of_property_read_string - Find and read a string from a property * of_property_read_string - Find and read a string from a property
......
...@@ -762,7 +762,7 @@ static inline void early_init_dt_check_for_initrd(unsigned long node) ...@@ -762,7 +762,7 @@ static inline void early_init_dt_check_for_initrd(unsigned long node)
#ifdef CONFIG_SERIAL_EARLYCON #ifdef CONFIG_SERIAL_EARLYCON
extern struct of_device_id __earlycon_of_table[]; extern struct of_device_id __earlycon_of_table[];
int __init early_init_dt_scan_chosen_serial(void) static int __init early_init_dt_scan_chosen_serial(void)
{ {
int offset; int offset;
const char *p; const char *p;
......
...@@ -265,6 +265,7 @@ int of_reserved_mem_device_init(struct device *dev) ...@@ -265,6 +265,7 @@ int of_reserved_mem_device_init(struct device *dev)
return ret; return ret;
} }
EXPORT_SYMBOL_GPL(of_reserved_mem_device_init);
/** /**
* of_reserved_mem_device_release() - release reserved memory device structures * of_reserved_mem_device_release() - release reserved memory device structures
...@@ -289,3 +290,4 @@ void of_reserved_mem_device_release(struct device *dev) ...@@ -289,3 +290,4 @@ void of_reserved_mem_device_release(struct device *dev)
rmem->ops->device_release(rmem, dev); rmem->ops->device_release(rmem, dev);
} }
EXPORT_SYMBOL_GPL(of_reserved_mem_device_release);
...@@ -68,6 +68,48 @@ selftest8: test-selftest8 { ...@@ -68,6 +68,48 @@ selftest8: test-selftest8 {
status = "disabled"; status = "disabled";
reg = <8>; reg = <8>;
}; };
i2c-test-bus {
compatible = "selftest-i2c-bus";
status = "okay";
reg = <50>;
#address-cells = <1>;
#size-cells = <0>;
test-selftest12 {
reg = <8>;
compatible = "selftest-i2c-dev";
status = "disabled";
};
test-selftest13 {
reg = <9>;
compatible = "selftest-i2c-dev";
status = "okay";
};
test-selftest14 {
reg = <10>;
compatible = "selftest-i2c-mux";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
test-mux-dev {
reg = <32>;
compatible = "selftest-i2c-dev";
status = "okay";
};
};
};
};
}; };
}; };
...@@ -231,5 +273,57 @@ test-selftest111 { ...@@ -231,5 +273,57 @@ test-selftest111 {
}; };
}; };
}; };
/* test enable using absolute target path (i2c) */
overlay12 {
fragment@0 {
target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus/test-selftest12";
__overlay__ {
status = "okay";
};
};
};
/* test disable using absolute target path (i2c) */
overlay13 {
fragment@0 {
target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus/test-selftest13";
__overlay__ {
status = "disabled";
};
};
};
/* test mux overlay */
overlay15 {
fragment@0 {
target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus";
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
test-selftest15 {
reg = <11>;
compatible = "selftest-i2c-mux";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
test-mux-dev {
reg = <32>;
compatible = "selftest-i2c-dev";
status = "okay";
};
};
};
};
};
};
}; };
}; };
This diff is collapsed.
...@@ -220,8 +220,7 @@ struct serio_device_id { ...@@ -220,8 +220,7 @@ struct serio_device_id {
/* /*
* Struct used for matching a device * Struct used for matching a device
*/ */
struct of_device_id struct of_device_id {
{
char name[32]; char name[32];
char type[32]; char type[32];
char compatible[128]; char compatible[128];
......
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