arm64/sysreg: Convert ID_AA64PFR0_EL1 to automatic generation

Automatically generate the constants for ID_AA64PFR0_EL1 as per DDI0487I.a,
no functional changes. The generic defines for the ELx fields are left in
place as they remain useful.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-25-broonie@kernel.orgSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>

arch/arm64/include/asm/sysreg.h

@@ -190,7 +190,6 @@
 #define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
 #define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)
 
-#define SYS_ID_AA64PFR0_EL1		sys_reg(3, 0, 0, 4, 0)
 #define SYS_ID_AA64PFR1_EL1		sys_reg(3, 0, 0, 4, 1)
 
 #define SYS_ID_AA64DFR0_EL1		sys_reg(3, 0, 0, 5, 0)
@@ -681,29 +680,6 @@
 #define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
 
 /* id_aa64pfr0 */
-#define ID_AA64PFR0_EL1_CSV3_SHIFT		60
-#define ID_AA64PFR0_EL1_CSV2_SHIFT		56
-#define ID_AA64PFR0_EL1_DIT_SHIFT		48
-#define ID_AA64PFR0_EL1_AMU_SHIFT		44
-#define ID_AA64PFR0_EL1_MPAM_SHIFT		40
-#define ID_AA64PFR0_EL1_SEL2_SHIFT		36
-#define ID_AA64PFR0_EL1_SVE_SHIFT		32
-#define ID_AA64PFR0_EL1_RAS_SHIFT		28
-#define ID_AA64PFR0_EL1_GIC_SHIFT		24
-#define ID_AA64PFR0_EL1_AdvSIMD_SHIFT		20
-#define ID_AA64PFR0_EL1_FP_SHIFT		16
-#define ID_AA64PFR0_EL1_EL3_SHIFT		12
-#define ID_AA64PFR0_EL1_EL2_SHIFT		8
-#define ID_AA64PFR0_EL1_EL1_SHIFT		4
-#define ID_AA64PFR0_EL1_EL0_SHIFT		0
-
-#define ID_AA64PFR0_EL1_AMU_IMP			0x1
-#define ID_AA64PFR0_EL1_SVE_IMP			0x1
-#define ID_AA64PFR0_EL1_RAS_IMP			0x1
-#define ID_AA64PFR0_EL1_RAS_V1P1		0x2
-#define ID_AA64PFR0_EL1_FP_NI			0xf
-#define ID_AA64PFR0_EL1_FP_IMP			0x0
-#define ID_AA64PFR0_EL1_AdvSIMD_NI		0xf
 #define ID_AA64PFR0_EL1_ELx_64BIT_ONLY		0x1
 #define ID_AA64PFR0_EL1_ELx_32BIT_64BIT		0x2
 

arch/arm64/tools/sysreg

@@ -46,6 +46,82 @@
 # feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
 # item ACCDATA) though it may be more taseful to do something else.
 
+Sysreg	ID_AA64PFR0_EL1	3	0	0	4	0
+Enum	63:60	CSV3
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	59:56	CSV2
+	0b0000	NI
+	0b0001	IMP
+	0b0010	CSV2_2
+	0b0011	CSV2_3
+EndEnum
+Enum	55:52	RME
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	51:48	DIT
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	47:44	AMU
+	0b0000	NI
+	0b0001	IMP
+	0b0010	V1P1
+EndEnum
+Enum	43:40	MPAM
+	0b0000	0
+	0b0001	1
+EndEnum
+Enum	39:36	SEL2
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	35:32	SVE
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	31:28	RAS
+	0b0000	NI
+	0b0001	IMP
+	0b0010	V1P1
+EndEnum
+Enum	27:24	GIC
+	0b0000	NI
+	0b0001	IMP
+	0b0010	V4P1
+EndEnum
+Enum	23:20	AdvSIMD
+	0b0000	IMP
+	0b0001	FP16
+	0b1111	NI
+EndEnum
+Enum	19:16	FP
+	0b0000	IMP
+	0b0001	FP16
+	0b1111	NI
+EndEnum
+Enum	15:12	EL3
+	0b0000	NI
+	0b0001	IMP
+	0b0010	AARCH32
+EndEnum
+Enum	11:8	EL2
+	0b0000	NI
+	0b0001	IMP
+	0b0010	AARCH32
+EndEnum
+Enum	7:4	EL1
+	0b0001	IMP
+	0b0010	AARCH32
+EndEnum
+Enum	3:0	EL0
+	0b0001	IMP
+	0b0010	AARCH32
+EndEnum
+EndSysreg
+
 Sysreg	ID_AA64ZFR0_EL1	3	0	0	4	4
 Res0	63:60
 Enum	59:56	F64MM