Commit cedacfec authored by Erik Andrén's avatar Erik Andrén Committed by Mauro Carvalho Chehab

V4L/DVB (10033): m5602: add some comments

Signed-off-by: default avatarErik Andrén <erik.andren@gmail.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent 7e08e66a
...@@ -993,7 +993,7 @@ static const unsigned char init_mt9m111[][4] = ...@@ -993,7 +993,7 @@ static const unsigned char init_mt9m111[][4] =
{BRIDGE, M5602_XB_SIG_INI, 0x02, 0x00}, {BRIDGE, M5602_XB_SIG_INI, 0x02, 0x00},
{BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00}, {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
{BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00}, {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
{BRIDGE, M5602_XB_HSYNC_PARA, 0x02, 0x00}, {BRIDGE, M5602_XB_HSYNC_PARA, 0x02, 0x00}, /* 639*/
{BRIDGE, M5602_XB_HSYNC_PARA, 0x7f, 0x00}, {BRIDGE, M5602_XB_HSYNC_PARA, 0x7f, 0x00},
{BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00}, {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
{BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00}, {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
......
...@@ -386,9 +386,9 @@ static const unsigned char init_ov9650[][3] = ...@@ -386,9 +386,9 @@ static const unsigned char init_ov9650[][3] =
and set PWDN to SLVS (slave mode vertical sync) */ and set PWDN to SLVS (slave mode vertical sync) */
{SENSOR, OV9650_COM10, 0x42}, {SENSOR, OV9650_COM10, 0x42},
/* Set horizontal column start high to default value */ /* Set horizontal column start high to default value */
{SENSOR, OV9650_HSTART, 0x1a}, {SENSOR, OV9650_HSTART, 0x1a}, /* 210 */
/* Set horizontal column end */ /* Set horizontal column end */
{SENSOR, OV9650_HSTOP, 0xbf}, {SENSOR, OV9650_HSTOP, 0xbf}, /* 1534 */
/* Complementing register to the two writes above */ /* Complementing register to the two writes above */
{SENSOR, OV9650_HREF, 0xb2}, {SENSOR, OV9650_HREF, 0xb2},
/* Set vertical row start high bits */ /* Set vertical row start high bits */
...@@ -428,11 +428,12 @@ static const unsigned char init_ov9650[][3] = ...@@ -428,11 +428,12 @@ static const unsigned char init_ov9650[][3] =
{BRIDGE, M5602_XB_VSYNC_PARA, 0x09}, {BRIDGE, M5602_XB_VSYNC_PARA, 0x09},
{BRIDGE, M5602_XB_VSYNC_PARA, 0x00}, {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
{BRIDGE, M5602_XB_VSYNC_PARA, 0x01}, {BRIDGE, M5602_XB_VSYNC_PARA, 0x01},
{BRIDGE, M5602_XB_VSYNC_PARA, 0xe0}, {BRIDGE, M5602_XB_VSYNC_PARA, 0xe0}, /* 480 */
{BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
{BRIDGE, M5602_XB_VSYNC_PARA, 0x00}, {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
{BRIDGE, M5602_XB_HSYNC_PARA, 0x00}, {BRIDGE, M5602_XB_HSYNC_PARA, 0x00},
{BRIDGE, M5602_XB_HSYNC_PARA, 0x5e}, {BRIDGE, M5602_XB_HSYNC_PARA, 0x5e}, /* 94 */
{BRIDGE, M5602_XB_HSYNC_PARA, 0x02}, {BRIDGE, M5602_XB_HSYNC_PARA, 0x02}, /* 734 */
{BRIDGE, M5602_XB_HSYNC_PARA, 0xde} {BRIDGE, M5602_XB_HSYNC_PARA, 0xde}
}; };
......
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