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Commit cf683abd authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-sifive' and 'clk-visconti' into clk-next 

* clk-sifive:
  clk: sifive: Move all stuff into SoCs header files from C files
  clk: sifive: Add SoCs prefix in each SoCs-dependent data
  riscv: dts: Change the macro name of prci in each device node
  dt-bindings: change the macro name of prci in header files and example
  clk: sifive: duplicate the macro definitions for the time being

* clk-visconti:
  clk: visconti: prevent array overflow in visconti_clk_register_gates()
parents c64dd8ea 5e916932 c5601e07
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Showing with 259 additions and 279 deletions
Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
View file @ cf683abd
......@@ -80,7 +80,7 @@ examples:
interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>,
<17>, <18>, <19>, <20>, <21>, <22>;
reg = <0x10060000 0x1000>;
clocks = <&tlclk PRCI_CLK_TLCLK>;
clocks = <&tlclk FU540_PRCI_CLK_TLCLK>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
......
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
View file @ cf683abd
......@@ -104,7 +104,7 @@ examples:
<0x0 0x0 0x0 0x2 &plic0 58>,
<0x0 0x0 0x0 0x3 &plic0 59>,
<0x0 0x0 0x0 0x4 &plic0 60>;
clocks = <&prci PRCI_CLK_PCIE_AUX>;
clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
resets = <&prci 4>;
pwren-gpios = <&gpio 5 0>;
reset-gpios = <&gpio 8 0>;
......
Documentation/devicetree/bindings/serial/sifive-serial.yaml
View file @ cf683abd
......@@ -59,7 +59,7 @@ examples:
interrupt-parent = <&plic0>;
interrupts = <80>;
reg = <0x10010000 0x1000>;
clocks = <&prci PRCI_CLK_TLCLK>;
clocks = <&prci FU540_PRCI_CLK_TLCLK>;
};
...
arch/riscv/boot/dts/sifive/fu540-c000.dtsi
View file @ cf683abd
......@@ -164,7 +164,7 @@ uart0: serial@10010000 {
reg = <0x0 0x10010000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <4>;
clocks = <&prci PRCI_CLK_TLCLK>;
clocks = <&prci FU540_PRCI_CLK_TLCLK>;
status = "disabled";
};
dma: dma@3000000 {
......@@ -180,7 +180,7 @@ uart1: serial@10011000 {
reg = <0x0 0x10011000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <5>;
clocks = <&prci PRCI_CLK_TLCLK>;
clocks = <&prci FU540_PRCI_CLK_TLCLK>;
status = "disabled";
};
i2c0: i2c@10030000 {
......@@ -188,7 +188,7 @@ i2c0: i2c@10030000 {
reg = <0x0 0x10030000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <50>;
clocks = <&prci PRCI_CLK_TLCLK>;
clocks = <&prci FU540_PRCI_CLK_TLCLK>;
reg-shift = <2>;
reg-io-width = <1>;
#address-cells = <1>;
......@@ -201,7 +201,7 @@ qspi0: spi@10040000 {
<0x0 0x20000000 0x0 0x10000000>;
interrupt-parent = <&plic0>;
interrupts = <51>;
clocks = <&prci PRCI_CLK_TLCLK>;
clocks = <&prci FU540_PRCI_CLK_TLCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
......@@ -212,7 +212,7 @@ qspi1: spi@10041000 {
<0x0 0x30000000 0x0 0x10000000>;
interrupt-parent = <&plic0>;
interrupts = <52>;
clocks = <&prci PRCI_CLK_TLCLK>;
clocks = <&prci FU540_PRCI_CLK_TLCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
......@@ -222,7 +222,7 @@ qspi2: spi@10050000 {
reg = <0x0 0x10050000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <6>;
clocks = <&prci PRCI_CLK_TLCLK>;
clocks = <&prci FU540_PRCI_CLK_TLCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
......@@ -235,8 +235,8 @@ eth0: ethernet@10090000 {
<0x0 0x100a0000 0x0 0x1000>;
local-mac-address = [00 00 00 00 00 00];
clock-names = "pclk", "hclk";
clocks = <&prci PRCI_CLK_GEMGXLPLL>,
<&prci PRCI_CLK_GEMGXLPLL>;
clocks = <&prci FU540_PRCI_CLK_GEMGXLPLL>,
<&prci FU540_PRCI_CLK_GEMGXLPLL>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
......@@ -246,7 +246,7 @@ pwm0: pwm@10020000 {
reg = <0x0 0x10020000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <42>, <43>, <44>, <45>;
clocks = <&prci PRCI_CLK_TLCLK>;
clocks = <&prci FU540_PRCI_CLK_TLCLK>;
#pwm-cells = <3>;
status = "disabled";
};
......@@ -255,7 +255,7 @@ pwm1: pwm@10021000 {
reg = <0x0 0x10021000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <46>, <47>, <48>, <49>;
clocks = <&prci PRCI_CLK_TLCLK>;
clocks = <&prci FU540_PRCI_CLK_TLCLK>;
#pwm-cells = <3>;
status = "disabled";
};
......@@ -281,7 +281,7 @@ gpio: gpio@10060000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&prci PRCI_CLK_TLCLK>;
clocks = <&prci FU540_PRCI_CLK_TLCLK>;
status = "disabled";
};
};
......
arch/riscv/boot/dts/sifive/fu740-c000.dtsi
View file @ cf683abd
......@@ -166,7 +166,7 @@ uart0: serial@10010000 {
reg = <0x0 0x10010000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <39>;
clocks = <&prci PRCI_CLK_PCLK>;
clocks = <&prci FU740_PRCI_CLK_PCLK>;
status = "disabled";
};
uart1: serial@10011000 {
......@@ -174,7 +174,7 @@ uart1: serial@10011000 {
reg = <0x0 0x10011000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <40>;
clocks = <&prci PRCI_CLK_PCLK>;
clocks = <&prci FU740_PRCI_CLK_PCLK>;
status = "disabled";
};
i2c0: i2c@10030000 {
......@@ -182,7 +182,7 @@ i2c0: i2c@10030000 {
reg = <0x0 0x10030000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <52>;
clocks = <&prci PRCI_CLK_PCLK>;
clocks = <&prci FU740_PRCI_CLK_PCLK>;
reg-shift = <2>;
reg-io-width = <1>;
#address-cells = <1>;
......@@ -194,7 +194,7 @@ i2c1: i2c@10031000 {
reg = <0x0 0x10031000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <53>;
clocks = <&prci PRCI_CLK_PCLK>;
clocks = <&prci FU740_PRCI_CLK_PCLK>;
reg-shift = <2>;
reg-io-width = <1>;
#address-cells = <1>;
......@@ -207,7 +207,7 @@ qspi0: spi@10040000 {
<0x0 0x20000000 0x0 0x10000000>;
interrupt-parent = <&plic0>;
interrupts = <41>;
clocks = <&prci PRCI_CLK_PCLK>;
clocks = <&prci FU740_PRCI_CLK_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
......@@ -218,7 +218,7 @@ qspi1: spi@10041000 {
<0x0 0x30000000 0x0 0x10000000>;
interrupt-parent = <&plic0>;
interrupts = <42>;
clocks = <&prci PRCI_CLK_PCLK>;
clocks = <&prci FU740_PRCI_CLK_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
......@@ -228,7 +228,7 @@ spi0: spi@10050000 {
reg = <0x0 0x10050000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <43>;
clocks = <&prci PRCI_CLK_PCLK>;
clocks = <&prci FU740_PRCI_CLK_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
......@@ -241,8 +241,8 @@ eth0: ethernet@10090000 {
<0x0 0x100a0000 0x0 0x1000>;
local-mac-address = [00 00 00 00 00 00];
clock-names = "pclk", "hclk";
clocks = <&prci PRCI_CLK_GEMGXLPLL>,
<&prci PRCI_CLK_GEMGXLPLL>;
clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>,
<&prci FU740_PRCI_CLK_GEMGXLPLL>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
......@@ -252,7 +252,7 @@ pwm0: pwm@10020000 {
reg = <0x0 0x10020000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <44>, <45>, <46>, <47>;
clocks = <&prci PRCI_CLK_PCLK>;
clocks = <&prci FU740_PRCI_CLK_PCLK>;
#pwm-cells = <3>;
status = "disabled";
};
......@@ -261,7 +261,7 @@ pwm1: pwm@10021000 {
reg = <0x0 0x10021000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <48>, <49>, <50>, <51>;
clocks = <&prci PRCI_CLK_PCLK>;
clocks = <&prci FU740_PRCI_CLK_PCLK>;
#pwm-cells = <3>;
status = "disabled";
};
......@@ -287,7 +287,7 @@ gpio: gpio@10060000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&prci PRCI_CLK_PCLK>;
clocks = <&prci FU740_PRCI_CLK_PCLK>;
status = "disabled";
};
pcie@e00000000 {
......@@ -316,7 +316,7 @@ pcie@e00000000 {
<0x0 0x0 0x0 0x3 &plic0 59>,
<0x0 0x0 0x0 0x4 &plic0 60>;
clock-names = "pcie_aux";
clocks = <&prci PRCI_CLK_PCIE_AUX>;
clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
pwren-gpios = <&gpio 5 0>;
reset-gpios = <&gpio 8 0>;
resets = <&prci 4>;
......
drivers/clk/sifive/Makefile
View file @ cf683abd
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o fu540-prci.o fu740-prci.o
obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o
drivers/clk/sifive/fu540-prci.c deleted 100644 → 0
View file @ c64dd8ea
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018-2019 SiFive, Inc.
* Copyright (C) 2018-2019 Wesley Terpstra
* Copyright (C) 2018-2019 Paul Walmsley
* Copyright (C) 2020 Zong Li
*
* The FU540 PRCI implements clock and reset control for the SiFive
* FU540-C000 chip. This driver assumes that it has sole control
* over all PRCI resources.
*
* This driver is based on the PRCI driver written by Wesley Terpstra:
* https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
*
* References:
* - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
*/
#include <linux/module.h>
#include <dt-bindings/clock/sifive-fu540-prci.h>
#include "fu540-prci.h"
#include "sifive-prci.h"
/* PRCI integration data for each WRPLL instance */
static struct __prci_wrpll_data __prci_corepll_data = {
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
.enable_bypass = sifive_prci_coreclksel_use_hfclk,
.disable_bypass = sifive_prci_coreclksel_use_corepll,
};
static struct __prci_wrpll_data __prci_ddrpll_data = {
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
};
static struct __prci_wrpll_data __prci_gemgxlpll_data = {
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
};
/* Linux clock framework integration */
static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = {
.set_rate = sifive_prci_wrpll_set_rate,
.round_rate = sifive_prci_wrpll_round_rate,
.recalc_rate = sifive_prci_wrpll_recalc_rate,
.enable = sifive_prci_clock_enable,
.disable = sifive_prci_clock_disable,
.is_enabled = sifive_clk_is_enabled,
};
static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
.recalc_rate = sifive_prci_wrpll_recalc_rate,
};
static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = {
.recalc_rate = sifive_prci_tlclksel_recalc_rate,
};
/* List of clock controls provided by the PRCI */
struct __prci_clock __prci_init_clocks_fu540[] = {
[PRCI_CLK_COREPLL] = {
.name = "corepll",
.parent_name = "hfclk",
.ops = &sifive_fu540_prci_wrpll_clk_ops,
.pwd = &__prci_corepll_data,
},
[PRCI_CLK_DDRPLL] = {
.name = "ddrpll",
.parent_name = "hfclk",
.ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
.pwd = &__prci_ddrpll_data,
},
[PRCI_CLK_GEMGXLPLL] = {
.name = "gemgxlpll",
.parent_name = "hfclk",
.ops = &sifive_fu540_prci_wrpll_clk_ops,
.pwd = &__prci_gemgxlpll_data,
},
[PRCI_CLK_TLCLK] = {
.name = "tlclk",
.parent_name = "corepll",
.ops = &sifive_fu540_prci_tlclksel_clk_ops,
},
};
drivers/clk/sifive/fu540-prci.h
View file @ cf683abd
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 SiFive, Inc.
* Zong Li
* Copyright (C) 2018-2021 SiFive, Inc.
* Copyright (C) 2018-2019 Wesley Terpstra
* Copyright (C) 2018-2019 Paul Walmsley
* Copyright (C) 2020-2021 Zong Li
*
* The FU540 PRCI implements clock and reset control for the SiFive
* FU540-C000 chip. This driver assumes that it has sole control
* over all PRCI resources.
*
* This driver is based on the PRCI driver written by Wesley Terpstra:
* https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
*
* References:
* - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
*/
#ifndef __SIFIVE_CLK_FU540_PRCI_H
#define __SIFIVE_CLK_FU540_PRCI_H
#include <linux/module.h>
#include <dt-bindings/clock/sifive-fu540-prci.h>
#include "sifive-prci.h"
#define NUM_CLOCK_FU540 4
/* PRCI integration data for each WRPLL instance */
static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = {
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
.enable_bypass = sifive_prci_coreclksel_use_hfclk,
.disable_bypass = sifive_prci_coreclksel_use_corepll,
};
static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = {
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
};
static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = {
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
};
/* Linux clock framework integration */
static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = {
.set_rate = sifive_prci_wrpll_set_rate,
.round_rate = sifive_prci_wrpll_round_rate,
.recalc_rate = sifive_prci_wrpll_recalc_rate,
.enable = sifive_prci_clock_enable,
.disable = sifive_prci_clock_disable,
.is_enabled = sifive_clk_is_enabled,
};
static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
.recalc_rate = sifive_prci_wrpll_recalc_rate,
};
static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = {
.recalc_rate = sifive_prci_tlclksel_recalc_rate,
};
/* List of clock controls provided by the PRCI */
static struct __prci_clock __prci_init_clocks_fu540[] = {
[FU540_PRCI_CLK_COREPLL] = {
.name = "corepll",
.parent_name = "hfclk",
.ops = &sifive_fu540_prci_wrpll_clk_ops,
.pwd = &sifive_fu540_prci_corepll_data,
},
[FU540_PRCI_CLK_DDRPLL] = {
.name = "ddrpll",
.parent_name = "hfclk",
.ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
.pwd = &sifive_fu540_prci_ddrpll_data,
},
[FU540_PRCI_CLK_GEMGXLPLL] = {
.name = "gemgxlpll",
.parent_name = "hfclk",
.ops = &sifive_fu540_prci_wrpll_clk_ops,
.pwd = &sifive_fu540_prci_gemgxlpll_data,
},
[FU540_PRCI_CLK_TLCLK] = {
.name = "tlclk",
.parent_name = "corepll",
.ops = &sifive_fu540_prci_tlclksel_clk_ops,
},
};
extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540];
static const struct prci_clk_desc prci_clk_fu540 = {
.clks = __prci_init_clocks_fu540,
.num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
};
#endif /* __SIFIVE_CLK_FU540_PRCI_H */
drivers/clk/sifive/fu740-prci.c deleted 100644 → 0
View file @ c64dd8ea
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 SiFive, Inc.
* Copyright (C) 2020 Zong Li
*/
#include <linux/module.h>
#include <dt-bindings/clock/sifive-fu740-prci.h>
#include "fu540-prci.h"
#include "sifive-prci.h"
/* PRCI integration data for each WRPLL instance */
static struct __prci_wrpll_data __prci_corepll_data = {
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
.enable_bypass = sifive_prci_coreclksel_use_hfclk,
.disable_bypass = sifive_prci_coreclksel_use_final_corepll,
};
static struct __prci_wrpll_data __prci_ddrpll_data = {
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
};
static struct __prci_wrpll_data __prci_gemgxlpll_data = {
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
};
static struct __prci_wrpll_data __prci_dvfscorepll_data = {
.cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
.cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET,
.enable_bypass = sifive_prci_corepllsel_use_corepll,
.disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
};
static struct __prci_wrpll_data __prci_hfpclkpll_data = {
.cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
.cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET,
.enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
.disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
};
static struct __prci_wrpll_data __prci_cltxpll_data = {
.cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
.cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET,
};
/* Linux clock framework integration */
static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = {
.set_rate = sifive_prci_wrpll_set_rate,
.round_rate = sifive_prci_wrpll_round_rate,
.recalc_rate = sifive_prci_wrpll_recalc_rate,
.enable = sifive_prci_clock_enable,
.disable = sifive_prci_clock_disable,
.is_enabled = sifive_clk_is_enabled,
};
static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = {
.recalc_rate = sifive_prci_wrpll_recalc_rate,
};
static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = {
.recalc_rate = sifive_prci_tlclksel_recalc_rate,
};
static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
.recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
};
static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = {
.enable = sifive_prci_pcie_aux_clock_enable,
.disable = sifive_prci_pcie_aux_clock_disable,
.is_enabled = sifive_prci_pcie_aux_clock_is_enabled,
};
/* List of clock controls provided by the PRCI */
struct __prci_clock __prci_init_clocks_fu740[] = {
[PRCI_CLK_COREPLL] = {
.name = "corepll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_corepll_data,
},
[PRCI_CLK_DDRPLL] = {
.name = "ddrpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_ro_clk_ops,
.pwd = &__prci_ddrpll_data,
},
[PRCI_CLK_GEMGXLPLL] = {
.name = "gemgxlpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_gemgxlpll_data,
},
[PRCI_CLK_DVFSCOREPLL] = {
.name = "dvfscorepll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_dvfscorepll_data,
},
[PRCI_CLK_HFPCLKPLL] = {
.name = "hfpclkpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_hfpclkpll_data,
},
[PRCI_CLK_CLTXPLL] = {
.name = "cltxpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_cltxpll_data,
},
[PRCI_CLK_TLCLK] = {
.name = "tlclk",
.parent_name = "corepll",
.ops = &sifive_fu740_prci_tlclksel_clk_ops,
},
[PRCI_CLK_PCLK] = {
.name = "pclk",
.parent_name = "hfpclkpll",
.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
},
[PRCI_CLK_PCIE_AUX] = {
.name = "pcie_aux",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_pcie_aux_clk_ops,
},
};
drivers/clk/sifive/fu740-prci.h
View file @ cf683abd
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 SiFive, Inc.
* Zong Li
* Copyright (C) 2020-2021 SiFive, Inc.
* Copyright (C) 2020-2021 Zong Li
*/
#ifndef __SIFIVE_CLK_FU740_PRCI_H
#define __SIFIVE_CLK_FU740_PRCI_H
#include <linux/module.h>
#include <dt-bindings/clock/sifive-fu740-prci.h>
#include "sifive-prci.h"
#define NUM_CLOCK_FU740 9
/* PRCI integration data for each WRPLL instance */
static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = {
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
.enable_bypass = sifive_prci_coreclksel_use_hfclk,
.disable_bypass = sifive_prci_coreclksel_use_final_corepll,
};
static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = {
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
};
static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = {
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
};
static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = {
.cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
.cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET,
.enable_bypass = sifive_prci_corepllsel_use_corepll,
.disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
};
static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = {
.cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
.cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET,
.enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
.disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
};
static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = {
.cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
.cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET,
};
/* Linux clock framework integration */
static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = {
.set_rate = sifive_prci_wrpll_set_rate,
.round_rate = sifive_prci_wrpll_round_rate,
.recalc_rate = sifive_prci_wrpll_recalc_rate,
.enable = sifive_prci_clock_enable,
.disable = sifive_prci_clock_disable,
.is_enabled = sifive_clk_is_enabled,
};
extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740];
static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = {
.recalc_rate = sifive_prci_wrpll_recalc_rate,
};
static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = {
.recalc_rate = sifive_prci_tlclksel_recalc_rate,
};
static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
.recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
};
static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = {
.enable = sifive_prci_pcie_aux_clock_enable,
.disable = sifive_prci_pcie_aux_clock_disable,
.is_enabled = sifive_prci_pcie_aux_clock_is_enabled,
};
/* List of clock controls provided by the PRCI */
static struct __prci_clock __prci_init_clocks_fu740[] = {
[FU740_PRCI_CLK_COREPLL] = {
.name = "corepll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &sifive_fu740_prci_corepll_data,
},
[FU740_PRCI_CLK_DDRPLL] = {
.name = "ddrpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_ro_clk_ops,
.pwd = &sifive_fu740_prci_ddrpll_data,
},
[FU740_PRCI_CLK_GEMGXLPLL] = {
.name = "gemgxlpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &sifive_fu740_prci_gemgxlpll_data,
},
[FU740_PRCI_CLK_DVFSCOREPLL] = {
.name = "dvfscorepll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &sifive_fu740_prci_dvfscorepll_data,
},
[FU740_PRCI_CLK_HFPCLKPLL] = {
.name = "hfpclkpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &sifive_fu740_prci_hfpclkpll_data,
},
[FU740_PRCI_CLK_CLTXPLL] = {
.name = "cltxpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &sifive_fu740_prci_cltxpll_data,
},
[FU740_PRCI_CLK_TLCLK] = {
.name = "tlclk",
.parent_name = "corepll",
.ops = &sifive_fu740_prci_tlclksel_clk_ops,
},
[FU740_PRCI_CLK_PCLK] = {
.name = "pclk",
.parent_name = "hfpclkpll",
.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
},
[FU740_PRCI_CLK_PCIE_AUX] = {
.name = "pcie_aux",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_pcie_aux_clk_ops,
},
};
static const struct prci_clk_desc prci_clk_fu740 = {
.clks = __prci_init_clocks_fu740,
......
drivers/clk/sifive/sifive-prci.c
View file @ cf683abd
......@@ -12,11 +12,6 @@
#include "fu540-prci.h"
#include "fu740-prci.h"
static const struct prci_clk_desc prci_clk_fu540 = {
.clks = __prci_init_clocks_fu540,
.num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
};
/*
* Private functions
*/
......
drivers/clk/visconti/clkc-tmpv770x.c
View file @ cf683abd
......@@ -176,7 +176,7 @@ static const struct visconti_clk_gate_table clk_gate_tables[] = {
{ TMPV770X_CLK_WRCK, "wrck",
clks_parent_data, ARRAY_SIZE(clks_parent_data),
0, 0x68, 0x168, 9, 32,
-1, }, /* No reset */
NO_RESET, },
{ TMPV770X_CLK_PICKMON, "pickmon",
clks_parent_data, ARRAY_SIZE(clks_parent_data),
0, 0x10, 0x110, 8, 4,
......
drivers/clk/visconti/clkc.c
View file @ cf683abd
......@@ -147,7 +147,7 @@ int visconti_clk_register_gates(struct visconti_clk_provider *ctx,
if (!dev_name)
return -ENOMEM;
if (clks[i].rs_id >= 0) {
if (clks[i].rs_id != NO_RESET) {
rson_offset = reset[clks[i].rs_id].rson_offset;
rsoff_offset = reset[clks[i].rs_id].rsoff_offset;
rs_idx = reset[clks[i].rs_id].rs_idx;
......
drivers/clk/visconti/clkc.h
View file @ cf683abd
......@@ -73,4 +73,7 @@ int visconti_clk_register_gates(struct visconti_clk_provider *data,
int num_gate,
const struct visconti_reset_data *reset,
spinlock_t *lock);
#define NO_RESET 0xFF
#endif /* _VISCONTI_CLKC_H_ */
include/dt-bindings/clock/sifive-fu540-prci.h
View file @ cf683abd
......@@ -10,9 +10,9 @@
/* Clock indexes for use by Device Tree data and the PRCI driver */
#define PRCI_CLK_COREPLL 0
#define PRCI_CLK_DDRPLL 1
#define PRCI_CLK_GEMGXLPLL 2
#define PRCI_CLK_TLCLK 3
#define FU540_PRCI_CLK_COREPLL 0
#define FU540_PRCI_CLK_DDRPLL 1
#define FU540_PRCI_CLK_GEMGXLPLL 2
#define FU540_PRCI_CLK_TLCLK 3
#endif
include/dt-bindings/clock/sifive-fu740-prci.h
View file @ cf683abd
......@@ -11,14 +11,14 @@
/* Clock indexes for use by Device Tree data and the PRCI driver */
#define PRCI_CLK_COREPLL 0
#define PRCI_CLK_DDRPLL 1
#define PRCI_CLK_GEMGXLPLL 2
#define PRCI_CLK_DVFSCOREPLL 3
#define PRCI_CLK_HFPCLKPLL 4
#define PRCI_CLK_CLTXPLL 5
#define PRCI_CLK_TLCLK 6
#define PRCI_CLK_PCLK 7
#define PRCI_CLK_PCIE_AUX 8
#define FU740_PRCI_CLK_COREPLL 0
#define FU740_PRCI_CLK_DDRPLL 1
#define FU740_PRCI_CLK_GEMGXLPLL 2
#define FU740_PRCI_CLK_DVFSCOREPLL 3
#define FU740_PRCI_CLK_HFPCLKPLL 4
#define FU740_PRCI_CLK_CLTXPLL 5
#define FU740_PRCI_CLK_TLCLK 6
#define FU740_PRCI_CLK_PCLK 7
#define FU740_PRCI_CLK_PCIE_AUX 8
#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */
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