Commit d0331c21 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Greg Kroah-Hartman

watchdog: s3c2410: Fix infinite interrupt in soft mode

[ Upstream commit 0b445549 ]

In soft (no-reboot) mode, the driver self-pings watchdog upon expiration
of an interrupt.  However the interrupt itself was not cleared thus on
first hit, the system enters infinite interrupt handling loop.

On Odroid U3 (Exynos4412), when booted with s3c2410_wdt.soft_noboot=1
argument the console is flooded:
	# killall -9 watchdog
	[   60.523760] s3c2410-wdt 10060000.watchdog: watchdog timer expired (irq)
	[   60.536744] s3c2410-wdt 10060000.watchdog: watchdog timer expired (irq)

Fix this by writing something to the WTCLRINT register to clear the
interrupt.  The register WTCLRINT however appeared in S3C6410 so a new
watchdog quirk and flavor are needed.
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarSasha Levin <alexander.levin@verizon.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 07371cd9
...@@ -6,10 +6,11 @@ occurred. ...@@ -6,10 +6,11 @@ occurred.
Required properties: Required properties:
- compatible : should be one among the following - compatible : should be one among the following
(a) "samsung,s3c2410-wdt" for Exynos4 and previous SoCs - "samsung,s3c2410-wdt" for S3C2410
(b) "samsung,exynos5250-wdt" for Exynos5250 - "samsung,s3c6410-wdt" for S3C6410, S5PV210 and Exynos4
(c) "samsung,exynos5420-wdt" for Exynos5420 - "samsung,exynos5250-wdt" for Exynos5250
(c) "samsung,exynos7-wdt" for Exynos7 - "samsung,exynos5420-wdt" for Exynos5420
- "samsung,exynos7-wdt" for Exynos7
- reg : base physical address of the controller and length of memory mapped - reg : base physical address of the controller and length of memory mapped
region. region.
......
...@@ -46,6 +46,7 @@ ...@@ -46,6 +46,7 @@
#define S3C2410_WTCON 0x00 #define S3C2410_WTCON 0x00
#define S3C2410_WTDAT 0x04 #define S3C2410_WTDAT 0x04
#define S3C2410_WTCNT 0x08 #define S3C2410_WTCNT 0x08
#define S3C2410_WTCLRINT 0x0c
#define S3C2410_WTCNT_MAXCNT 0xffff #define S3C2410_WTCNT_MAXCNT 0xffff
...@@ -72,6 +73,7 @@ ...@@ -72,6 +73,7 @@
#define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
#define QUIRK_HAS_PMU_CONFIG (1 << 0) #define QUIRK_HAS_PMU_CONFIG (1 << 0)
#define QUIRK_HAS_RST_STAT (1 << 1) #define QUIRK_HAS_RST_STAT (1 << 1)
#define QUIRK_HAS_WTCLRINT_REG (1 << 2)
/* These quirks require that we have a PMU register map */ /* These quirks require that we have a PMU register map */
#define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \ #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
...@@ -143,13 +145,18 @@ static const struct s3c2410_wdt_variant drv_data_s3c2410 = { ...@@ -143,13 +145,18 @@ static const struct s3c2410_wdt_variant drv_data_s3c2410 = {
}; };
#ifdef CONFIG_OF #ifdef CONFIG_OF
static const struct s3c2410_wdt_variant drv_data_s3c6410 = {
.quirks = QUIRK_HAS_WTCLRINT_REG,
};
static const struct s3c2410_wdt_variant drv_data_exynos5250 = { static const struct s3c2410_wdt_variant drv_data_exynos5250 = {
.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
.mask_bit = 20, .mask_bit = 20,
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
.rst_stat_bit = 20, .rst_stat_bit = 20,
.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
| QUIRK_HAS_WTCLRINT_REG,
}; };
static const struct s3c2410_wdt_variant drv_data_exynos5420 = { static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
...@@ -158,7 +165,8 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = { ...@@ -158,7 +165,8 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
.mask_bit = 0, .mask_bit = 0,
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
.rst_stat_bit = 9, .rst_stat_bit = 9,
.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
| QUIRK_HAS_WTCLRINT_REG,
}; };
static const struct s3c2410_wdt_variant drv_data_exynos7 = { static const struct s3c2410_wdt_variant drv_data_exynos7 = {
...@@ -167,12 +175,15 @@ static const struct s3c2410_wdt_variant drv_data_exynos7 = { ...@@ -167,12 +175,15 @@ static const struct s3c2410_wdt_variant drv_data_exynos7 = {
.mask_bit = 23, .mask_bit = 23,
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
.rst_stat_bit = 23, /* A57 WDTRESET */ .rst_stat_bit = 23, /* A57 WDTRESET */
.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
| QUIRK_HAS_WTCLRINT_REG,
}; };
static const struct of_device_id s3c2410_wdt_match[] = { static const struct of_device_id s3c2410_wdt_match[] = {
{ .compatible = "samsung,s3c2410-wdt", { .compatible = "samsung,s3c2410-wdt",
.data = &drv_data_s3c2410 }, .data = &drv_data_s3c2410 },
{ .compatible = "samsung,s3c6410-wdt",
.data = &drv_data_s3c6410 },
{ .compatible = "samsung,exynos5250-wdt", { .compatible = "samsung,exynos5250-wdt",
.data = &drv_data_exynos5250 }, .data = &drv_data_exynos5250 },
{ .compatible = "samsung,exynos5420-wdt", { .compatible = "samsung,exynos5420-wdt",
...@@ -418,6 +429,10 @@ static irqreturn_t s3c2410wdt_irq(int irqno, void *param) ...@@ -418,6 +429,10 @@ static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
dev_info(wdt->dev, "watchdog timer expired (irq)\n"); dev_info(wdt->dev, "watchdog timer expired (irq)\n");
s3c2410wdt_keepalive(&wdt->wdt_device); s3c2410wdt_keepalive(&wdt->wdt_device);
if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG)
writel(0x1, wdt->reg_base + S3C2410_WTCLRINT);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
......
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