Commit d07b75ba authored by Quinn Tran's avatar Quinn Tran Committed by Martin K. Petersen

scsi: qla2xxx: edif: Fix EDIF enable flag

edif_enabled is prematurely turned on if hardware is capable of handling
the feature.  However, firmware also needs to support EDIF before enabling
this bit.

Link: https://lore.kernel.org/r/20210817051315.2477-4-njavali@marvell.comSigned-off-by: default avatarQuinn Tran <qutran@marvell.com>
Signed-off-by: default avatarNilesh Javali <njavali@marvell.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 22547929
...@@ -4021,6 +4021,7 @@ struct qla_hw_data { ...@@ -4021,6 +4021,7 @@ struct qla_hw_data {
uint32_t scm_supported_f:1; uint32_t scm_supported_f:1;
/* Enabled in Driver */ /* Enabled in Driver */
uint32_t scm_enabled:1; uint32_t scm_enabled:1;
uint32_t edif_hw:1;
uint32_t edif_enabled:1; uint32_t edif_enabled:1;
uint32_t plogi_template_valid:1; uint32_t plogi_template_valid:1;
uint32_t port_isolated:1; uint32_t port_isolated:1;
...@@ -4433,6 +4434,7 @@ struct qla_hw_data { ...@@ -4433,6 +4434,7 @@ struct qla_hw_data {
/* Cisco fabric attached */ /* Cisco fabric attached */
#define FW_ATTR_EXT0_SCM_CISCO 0x00002000 #define FW_ATTR_EXT0_SCM_CISCO 0x00002000
#define FW_ATTR_EXT0_NVME2 BIT_13 #define FW_ATTR_EXT0_NVME2 BIT_13
#define FW_ATTR_EXT0_EDIF BIT_5
uint16_t fw_attributes_ext[2]; uint16_t fw_attributes_ext[2];
uint32_t fw_memory_size; uint32_t fw_memory_size;
uint32_t fw_transfer_size; uint32_t fw_transfer_size;
......
...@@ -663,6 +663,7 @@ qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr, ...@@ -663,6 +663,7 @@ qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
} }
#define NVME_ENABLE_FLAG BIT_3 #define NVME_ENABLE_FLAG BIT_3
#define EDIF_HW_SUPPORT BIT_10
/* /*
* qla2x00_execute_fw * qla2x00_execute_fw
...@@ -795,10 +796,10 @@ qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr) ...@@ -795,10 +796,10 @@ qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
} }
} }
if (IS_QLA28XX(ha) && (mcp->mb[5] & BIT_10) && ql2xsecenable) { if (IS_QLA28XX(ha) && (mcp->mb[5] & EDIF_HW_SUPPORT)) {
ha->flags.edif_enabled = 1; ha->flags.edif_hw = 1;
ql_log(ql_log_info, vha, 0xffff, ql_log(ql_log_info, vha, 0xffff,
"%s: edif is enabled\n", __func__); "%s: edif HW\n", __func__);
} }
done: done:
...@@ -1136,6 +1137,13 @@ qla2x00_get_fw_version(scsi_qla_host_t *vha) ...@@ -1136,6 +1137,13 @@ qla2x00_get_fw_version(scsi_qla_host_t *vha)
ha->fw_attributes_ext[0]); ha->fw_attributes_ext[0]);
vha->flags.nvme2_enabled = 1; vha->flags.nvme2_enabled = 1;
} }
if (IS_QLA28XX(ha) && ha->flags.edif_hw && ql2xsecenable &&
(ha->fw_attributes_ext[0] & FW_ATTR_EXT0_EDIF)) {
ha->flags.edif_enabled = 1;
ql_log(ql_log_info + ql_dbg_edif, vha, 0xffff,
"%s: edif is enabled\n", __func__);
}
} }
if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
......
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