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Merge branch 'cpsw-add-MQPRIO-and-CBS-Qdisc-offload' 

Ivan Khoronzhuk says:

====================
net: ethernet: ti: cpsw: add MQPRIO and CBS Qdisc offload

This series adds MQPRIO and CBS Qdisc offload for TI cpsw driver.
It potentially can be used in audio video bridging (AVB) and time
sensitive networking (TSN).

Patchset was tested on AM572x EVM and BBB boards. Last patch from this
series adds detailed description of configuration with examples. For
consistency reasons, in role of talker and listener, tools from
patchset "TSN: Add qdisc based config interface for CBS" were used and
can be seen here: https://www.spinics.net/lists/netdev/msg460869.html

Based on net-next/master

v5..v4:
- corrected typo of "am57xx" board name, no functional changes

v4..v3:
 - nothing, just rebase

v3..v2:
 - corrected typo of "shaper" word, no functional changes

v2..v1:
 - changed name cpsw.txt on ti-cpsw.txt
 - changed name cpsw_set_tc() on cpsw_set_mqprio()
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents b19c7bb1 ae62372f
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Documentation/networking/ti-cpsw.txt 0 → 100644
View file @ d3585edf
* Texas Instruments CPSW ethernet driver
Multiqueue & CBS & MQPRIO
=====================================================================
=====================================================================
The cpsw has 3 CBS shapers for each external ports. This document
describes MQPRIO and CBS Qdisc offload configuration for cpsw driver
based on examples. It potentially can be used in audio video bridging
(AVB) and time sensitive networking (TSN).
The following examples were tested on AM572x EVM and BBB boards.
Test setup
==========
Under consideration two examples with AM572x EVM running cpsw driver
in dual_emac mode.
Several prerequisites:
- TX queues must be rated starting from txq0 that has highest priority
- Traffic classes are used starting from 0, that has highest priority
- CBS shapers should be used with rated queues
- The bandwidth for CBS shapers has to be set a little bit more then
potential incoming rate, thus, rate of all incoming tx queues has
to be a little less
- Real rates can differ, due to discreetness
- Map skb-priority to txq is not enough, also skb-priority to l2 prio
map has to be created with ip or vconfig tool
- Any l2/socket prio (0 - 7) for classes can be used, but for
simplicity default values are used: 3 and 2
- only 2 classes tested: A and B, but checked and can work with more,
maximum allowed 4, but only for 3 rate can be set.
Test setup for examples
=======================
+-------------------------------+
|--+ |
| | Workstation0 |
|E | MAC 18:03:73:66:87:42 |
+-----------------------------+ +--|t | |
| | 1 | E | | |h |./tsn_listener -d \ |
| Target board: | 0 | t |--+ |0 | 18:03:73:66:87:42 -i eth0 \|
| AM572x EVM | 0 | h | | | -s 1500 |
| | 0 | 0 | |--+ |
| Only 2 classes: |Mb +---| +-------------------------------+
| class A, class B | |
| | +---| +-------------------------------+
| | 1 | E | |--+ |
| | 0 | t | | | Workstation1 |
| | 0 | h |--+ |E | MAC 20:cf:30:85:7d:fd |
| |Mb | 1 | +--|t | |
+-----------------------------+ |h |./tsn_listener -d \ |
|0 | 20:cf:30:85:7d:fd -i eth0 \|
| | -s 1500 |
|--+ |
+-------------------------------+
*********************************************************************
*********************************************************************
*********************************************************************
Example 1: One port tx AVB configuration scheme for target board
----------------------------------------------------------------------
(prints and scheme for AM572x evm, applicable for single port boards)
tc - traffic class
txq - transmit queue
p - priority
f - fifo (cpsw fifo)
S - shaper configured
+------------------------------------------------------------------+ u
| +---------------+ +---------------+ +------+ +------+ | s
| | | | | | | | | | e
| | App 1 | | App 2 | | Apps | | Apps | | r
| | Class A | | Class B | | Rest | | Rest | |
| | Eth0 | | Eth0 | | Eth0 | | Eth1 | | s
| | VLAN100 | | VLAN100 | | | | | | | | p
| | 40 Mb/s | | 20 Mb/s | | | | | | | | a
| | SO_PRIORITY=3 | | SO_PRIORITY=2 | | | | | | | | c
| | | | | | | | | | | | | | e
| +---|-----------+ +---|-----------+ +---|--+ +---|--+ |
+-----|------------------|------------------|--------|-------------+
+-+ +------------+ | |
| | +-----------------+ +--+
| | | |
+---|-------|-------------|-----------------------|----------------+
| +----+ +----+ +----+ +----+ +----+ |
| | p3 | | p2 | | p1 | | p0 | | p0 | | k
| \ / \ / \ / \ / \ / | e
| \ / \ / \ / \ / \ / | r
| \/ \/ \/ \/ \/ | n
| | | | | | e
| | | +-----+ | | l
| | | | | |
| +----+ +----+ +----+ +----+ | s
| |tc0 | |tc1 | |tc2 | |tc0 | | p
| \ / \ / \ / \ / | a
| \ / \ / \ / \ / | c
| \/ \/ \/ \/ | e
| | | +-----+ | |
| | | | | | |
| | | | | | |
| | | | | | |
| +----+ +----+ +----+ +----+ +----+ |
| |txq0| |txq1| |txq2| |txq3| |txq4| |
| \ / \ / \ / \ / \ / |
| \ / \ / \ / \ / \ / |
| \/ \/ \/ \/ \/ |
| +-|------|------|------|--+ +--|--------------+ |
| | | | | | | Eth0.100 | | Eth1 | |
+---|------|------|------|------------------------|----------------+
| | | | |
p p p p |
3 2 0-1, 4-7 <- L2 priority |
| | | | |
| | | | |
+---|------|------|------|------------------------|----------------+
| | | | | |----------+ |
| +----+ +----+ +----+ +----+ +----+ |
| |dma7| |dma6| |dma5| |dma4| |dma3| |
| \ / \ / \ / \ / \ / | c
| \S / \S / \ / \ / \ / | p
| \/ \/ \/ \/ \/ | s
| | | | +----- | | w
| | | | | | |
| | | | | | | d
| +----+ +----+ +----+p p+----+ | r
| | | | | | |o o| | | i
| | f3 | | f2 | | f0 |r r| f0 | | v
| |tc0 | |tc1 | |tc2 |t t|tc0 | | e
| \CBS / \CBS / \CBS /1 2\CBS / | r
| \S / \S / \ / \ / |
| \/ \/ \/ \/ |
+------------------------------------------------------------------+
========================================Eth==========================>
1)
// Add 4 tx queues, for interface Eth0, and 1 tx queue for Eth1
$ ethtool -L eth0 rx 1 tx 5
rx unmodified, ignoring
2)
// Check if num of queues is set correctly:
$ ethtool -l eth0
Channel parameters for eth0:
Pre-set maximums:
RX: 8
TX: 8
Other: 0
Combined: 0
Current hardware settings:
RX: 1
TX: 5
Other: 0
Combined: 0
3)
// TX queues must be rated starting from 0, so set bws for tx0 and tx1
// Set rates 40 and 20 Mb/s appropriately.
// Pay attention, real speed can differ a bit due to discreetness.
// Leave last 2 tx queues not rated.
$ echo 40 > /sys/class/net/eth0/queues/tx-0/tx_maxrate
$ echo 20 > /sys/class/net/eth0/queues/tx-1/tx_maxrate
4)
// Check maximum rate of tx (cpdma) queues:
$ cat /sys/class/net/eth0/queues/tx-*/tx_maxrate
40
20
0
0
0
5)
// Map skb->priority to traffic class:
// 3pri -> tc0, 2pri -> tc1, (0,1,4-7)pri -> tc2
// Map traffic class to transmit queue:
// tc0 -> txq0, tc1 -> txq1, tc2 -> (txq2, txq3)
$ tc qdisc replace dev eth0 handle 100: parent root mqprio num_tc 3 \
map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 queues 1@0 1@1 2@2 hw 1
5a)
// As two interface sharing same set of tx queues, assign all traffic
// coming to interface Eth1 to separate queue in order to not mix it
// with traffic from interface Eth0, so use separate txq to send
// packets to Eth1, so all prio -> tc0 and tc0 -> txq4
// Here hw 0, so here still default configuration for eth1 in hw
$ tc qdisc replace dev eth1 handle 100: parent root mqprio num_tc 1 \
map 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 queues 1@4 hw 0
6)
// Check classes settings
$ tc -g class show dev eth0
+---(100:ffe2) mqprio
| +---(100:3) mqprio
| +---(100:4) mqprio
|
+---(100:ffe1) mqprio
| +---(100:2) mqprio
|
+---(100:ffe0) mqprio
+---(100:1) mqprio
$ tc -g class show dev eth1
+---(100:ffe0) mqprio
+---(100:5) mqprio
7)
// Set rate for class A - 41 Mbit (tc0, txq0) using CBS Qdisc
// Set it +1 Mb for reserve (important!)
// here only idle slope is important, others arg are ignored
// Pay attention, real speed can differ a bit due to discreetness
$ tc qdisc add dev eth0 parent 100:1 cbs locredit -1438 \
hicredit 62 sendslope -959000 idleslope 41000 offload 1
net eth0: set FIFO3 bw = 50
8)
// Set rate for class B - 21 Mbit (tc1, txq1) using CBS Qdisc:
// Set it +1 Mb for reserve (important!)
$ tc qdisc add dev eth0 parent 100:2 cbs locredit -1468 \
hicredit 65 sendslope -979000 idleslope 21000 offload 1
net eth0: set FIFO2 bw = 30
9)
// Create vlan 100 to map sk->priority to vlan qos
$ ip link add link eth0 name eth0.100 type vlan id 100
8021q: 802.1Q VLAN Support v1.8
8021q: adding VLAN 0 to HW filter on device eth0
8021q: adding VLAN 0 to HW filter on device eth1
net eth0: Adding vlanid 100 to vlan filter
10)
// Map skb->priority to L2 prio, 1 to 1
$ ip link set eth0.100 type vlan \
egress 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7
11)
// Check egress map for vlan 100
$ cat /proc/net/vlan/eth0.100
[...]
INGRESS priority mappings: 0:0 1:0 2:0 3:0 4:0 5:0 6:0 7:0
EGRESS priority mappings: 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7
12)
// Run your appropriate tools with socket option "SO_PRIORITY"
// to 3 for class A and/or to 2 for class B
// (I took at https://www.spinics.net/lists/netdev/msg460869.html)
./tsn_talker -d 18:03:73:66:87:42 -i eth0.100 -p3 -s 1500&
./tsn_talker -d 18:03:73:66:87:42 -i eth0.100 -p2 -s 1500&
13)
// run your listener on workstation (should be in same vlan)
// (I took at https://www.spinics.net/lists/netdev/msg460869.html)
./tsn_listener -d 18:03:73:66:87:42 -i enp5s0 -s 1500
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39000 kbps
14)
// Restore default configuration if needed
$ ip link del eth0.100
$ tc qdisc del dev eth1 root
$ tc qdisc del dev eth0 root
net eth0: Prev FIFO2 is shaped
net eth0: set FIFO3 bw = 0
net eth0: set FIFO2 bw = 0
$ ethtool -L eth0 rx 1 tx 1
*********************************************************************
*********************************************************************
*********************************************************************
Example 2: Two port tx AVB configuration scheme for target board
----------------------------------------------------------------------
(prints and scheme for AM572x evm, for dual emac boards only)
+------------------------------------------------------------------+ u
| +----------+ +----------+ +------+ +----------+ +----------+ | s
| | | | | | | | | | | | e
| | App 1 | | App 2 | | Apps | | App 3 | | App 4 | | r
| | Class A | | Class B | | Rest | | Class B | | Class A | |
| | Eth0 | | Eth0 | | | | | Eth1 | | Eth1 | | s
| | VLAN100 | | VLAN100 | | | | | VLAN100 | | VLAN100 | | p
| | 40 Mb/s | | 20 Mb/s | | | | | 10 Mb/s | | 30 Mb/s | | a
| | SO_PRI=3 | | SO_PRI=2 | | | | | SO_PRI=3 | | SO_PRI=2 | | c
| | | | | | | | | | | | | | | | | e
| +---|------+ +---|------+ +---|--+ +---|------+ +---|------+ |
+-----|-------------|-------------|---------|-------------|--------+
+-+ +-------+ | +----------+ +----+
| | +-------+------+ | |
| | | | | |
+---|-------|-------------|--------------|-------------|-------|---+
| +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ |
| | p3 | | p2 | | p1 | | p0 | | p0 | | p1 | | p2 | | p3 | | k
| \ / \ / \ / \ / \ / \ / \ / \ / | e
| \ / \ / \ / \ / \ / \ / \ / \ / | r
| \/ \/ \/ \/ \/ \/ \/ \/ | n
| | | | | | | | e
| | | +----+ +----+ | | | l
| | | | | | | |
| +----+ +----+ +----+ +----+ +----+ +----+ | s
| |tc0 | |tc1 | |tc2 | |tc2 | |tc1 | |tc0 | | p
| \ / \ / \ / \ / \ / \ / | a
| \ / \ / \ / \ / \ / \ / | c
| \/ \/ \/ \/ \/ \/ | e
| | | +-----+ +-----+ | | |
| | | | | | | | | |
| | | | | | | | | |
| | | | | E E | | | | |
| +----+ +----+ +----+ +----+ t t +----+ +----+ +----+ +----+ |
| |txq0| |txq1| |txq4| |txq5| h h |txq6| |txq7| |txq3| |txq2| |
| \ / \ / \ / \ / 0 1 \ / \ / \ / \ / |
| \ / \ / \ / \ / . . \ / \ / \ / \ / |
| \/ \/ \/ \/ 1 1 \/ \/ \/ \/ |
| +-|------|------|------|--+ 0 0 +-|------|------|------|--+ |
| | | | | | | 0 0 | | | | | | |
+---|------|------|------|---------------|------|------|------|----+
| | | | | | | |
p p p p p p p p
3 2 0-1, 4-7 <-L2 pri-> 0-1, 4-7 2 3
| | | | | | | |
| | | | | | | |
+---|------|------|------|---------------|------|------|------|----+
| | | | | | | | | |
| +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ |
| |dma7| |dma6| |dma3| |dma2| |dma1| |dma0| |dma4| |dma5| |
| \ / \ / \ / \ / \ / \ / \ / \ / | c
| \S / \S / \ / \ / \ / \ / \S / \S / | p
| \/ \/ \/ \/ \/ \/ \/ \/ | s
| | | | +----- | | | | | w
| | | | | +----+ | | | |
| | | | | | | | | | d
| +----+ +----+ +----+p p+----+ +----+ +----+ | r
| | | | | | |o o| | | | | | | i
| | f3 | | f2 | | f0 |r CPSW r| f3 | | f2 | | f0 | | v
| |tc0 | |tc1 | |tc2 |t t|tc0 | |tc1 | |tc2 | | e
| \CBS / \CBS / \CBS /1 2\CBS / \CBS / \CBS / | r
| \S / \S / \ / \S / \S / \ / |
| \/ \/ \/ \/ \/ \/ |
+------------------------------------------------------------------+
========================================Eth==========================>
1)
// Add 8 tx queues, for interface Eth0, but they are common, so are accessed
// by two interfaces Eth0 and Eth1.
$ ethtool -L eth1 rx 1 tx 8
rx unmodified, ignoring
2)
// Check if num of queues is set correctly:
$ ethtool -l eth0
Channel parameters for eth0:
Pre-set maximums:
RX: 8
TX: 8
Other: 0
Combined: 0
Current hardware settings:
RX: 1
TX: 8
Other: 0
Combined: 0
3)
// TX queues must be rated starting from 0, so set bws for tx0 and tx1 for Eth0
// and for tx2 and tx3 for Eth1. That is, rates 40 and 20 Mb/s appropriately
// for Eth0 and 30 and 10 Mb/s for Eth1.
// Real speed can differ a bit due to discreetness
// Leave last 4 tx queues as not rated
$ echo 40 > /sys/class/net/eth0/queues/tx-0/tx_maxrate
$ echo 20 > /sys/class/net/eth0/queues/tx-1/tx_maxrate
$ echo 30 > /sys/class/net/eth1/queues/tx-2/tx_maxrate
$ echo 10 > /sys/class/net/eth1/queues/tx-3/tx_maxrate
4)
// Check maximum rate of tx (cpdma) queues:
$ cat /sys/class/net/eth0/queues/tx-*/tx_maxrate
40
20
30
10
0
0
0
0
5)
// Map skb->priority to traffic class for Eth0:
// 3pri -> tc0, 2pri -> tc1, (0,1,4-7)pri -> tc2
// Map traffic class to transmit queue:
// tc0 -> txq0, tc1 -> txq1, tc2 -> (txq4, txq5)
$ tc qdisc replace dev eth0 handle 100: parent root mqprio num_tc 3 \
map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 queues 1@0 1@1 2@4 hw 1
6)
// Check classes settings
$ tc -g class show dev eth0
+---(100:ffe2) mqprio
| +---(100:5) mqprio
| +---(100:6) mqprio
|
+---(100:ffe1) mqprio
| +---(100:2) mqprio
|
+---(100:ffe0) mqprio
+---(100:1) mqprio
7)
// Set rate for class A - 41 Mbit (tc0, txq0) using CBS Qdisc for Eth0
// here only idle slope is important, others ignored
// Real speed can differ a bit due to discreetness
$ tc qdisc add dev eth0 parent 100:1 cbs locredit -1470 \
hicredit 62 sendslope -959000 idleslope 41000 offload 1
net eth0: set FIFO3 bw = 50
8)
// Set rate for class B - 21 Mbit (tc1, txq1) using CBS Qdisc for Eth0
$ tc qdisc add dev eth0 parent 100:2 cbs locredit -1470 \
hicredit 65 sendslope -979000 idleslope 21000 offload 1
net eth0: set FIFO2 bw = 30
9)
// Create vlan 100 to map sk->priority to vlan qos for Eth0
$ ip link add link eth0 name eth0.100 type vlan id 100
net eth0: Adding vlanid 100 to vlan filter
10)
// Map skb->priority to L2 prio for Eth0.100, one to one
$ ip link set eth0.100 type vlan \
egress 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7
11)
// Check egress map for vlan 100
$ cat /proc/net/vlan/eth0.100
[...]
INGRESS priority mappings: 0:0 1:0 2:0 3:0 4:0 5:0 6:0 7:0
EGRESS priority mappings: 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7
12)
// Map skb->priority to traffic class for Eth1:
// 3pri -> tc0, 2pri -> tc1, (0,1,4-7)pri -> tc2
// Map traffic class to transmit queue:
// tc0 -> txq2, tc1 -> txq3, tc2 -> (txq6, txq7)
$ tc qdisc replace dev eth1 handle 100: parent root mqprio num_tc 3 \
map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 queues 1@2 1@3 2@6 hw 1
13)
// Check classes settings
$ tc -g class show dev eth1
+---(100:ffe2) mqprio
| +---(100:7) mqprio
| +---(100:8) mqprio
|
+---(100:ffe1) mqprio
| +---(100:4) mqprio
|
+---(100:ffe0) mqprio
+---(100:3) mqprio
14)
// Set rate for class A - 31 Mbit (tc0, txq2) using CBS Qdisc for Eth1
// here only idle slope is important, others ignored
// Set it +1 Mb for reserve (important!)
$ tc qdisc add dev eth1 parent 100:3 cbs locredit -1453 \
hicredit 47 sendslope -969000 idleslope 31000 offload 1
net eth1: set FIFO3 bw = 31
15)
// Set rate for class B - 11 Mbit (tc1, txq3) using CBS Qdisc for Eth1
// Set it +1 Mb for reserve (important!)
$ tc qdisc add dev eth1 parent 100:4 cbs locredit -1483 \
hicredit 34 sendslope -989000 idleslope 11000 offload 1
net eth1: set FIFO2 bw = 11
16)
// Create vlan 100 to map sk->priority to vlan qos for Eth1
$ ip link add link eth1 name eth1.100 type vlan id 100
net eth1: Adding vlanid 100 to vlan filter
17)
// Map skb->priority to L2 prio for Eth1.100, one to one
$ ip link set eth1.100 type vlan \
egress 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7
18)
// Check egress map for vlan 100
$ cat /proc/net/vlan/eth1.100
[...]
INGRESS priority mappings: 0:0 1:0 2:0 3:0 4:0 5:0 6:0 7:0
EGRESS priority mappings: 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7
19)
// Run appropriate tools with socket option "SO_PRIORITY" to 3
// for class A and to 2 for class B. For both interfaces
./tsn_talker -d 18:03:73:66:87:42 -i eth0.100 -p2 -s 1500&
./tsn_talker -d 18:03:73:66:87:42 -i eth0.100 -p3 -s 1500&
./tsn_talker -d 20:cf:30:85:7d:fd -i eth1.100 -p2 -s 1500&
./tsn_talker -d 20:cf:30:85:7d:fd -i eth1.100 -p3 -s 1500&
20)
// run your listener on workstation (should be in same vlan)
// (I took at https://www.spinics.net/lists/netdev/msg460869.html)
./tsn_listener -d 18:03:73:66:87:42 -i enp5s0 -s 1500
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39012 kbps
Receiving data rate: 39000 kbps
21)
// Restore default configuration if needed
$ ip link del eth1.100
$ ip link del eth0.100
$ tc qdisc del dev eth1 root
net eth1: Prev FIFO2 is shaped
net eth1: set FIFO3 bw = 0
net eth1: set FIFO2 bw = 0
$ tc qdisc del dev eth0 root
net eth0: Prev FIFO2 is shaped
net eth0: set FIFO3 bw = 0
net eth0: set FIFO2 bw = 0
$ ethtool -L eth0 rx 1 tx 1
drivers/net/ethernet/ti/cpsw.c
View file @ d3585edf
......@@ -39,12 +39,15 @@
#include <linux/sys_soc.h>
#include <linux/pinctrl/consumer.h>
#include <net/pkt_cls.h>
#include "cpsw.h"
#include "cpsw_ale.h"
#include "cpts.h"
#include "davinci_cpdma.h"
#include <net/pkt_sched.h>
#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
NETIF_MSG_DRV | NETIF_MSG_LINK | \
NETIF_MSG_IFUP | NETIF_MSG_INTR | \
......@@ -153,6 +156,12 @@ do { \
#define IRQ_NUM 2
#define CPSW_MAX_QUEUES 8
#define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
#define CPSW_FIFO_QUEUE_TYPE_SHIFT 16
#define CPSW_FIFO_SHAPE_EN_SHIFT 16
#define CPSW_FIFO_RATE_EN_SHIFT 20
#define CPSW_TC_NUM 4
#define CPSW_FIFO_SHAPERS_NUM (CPSW_TC_NUM - 1)
#define CPSW_PCT_MASK 0x7f
#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT 29
#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0)
......@@ -454,6 +463,9 @@ struct cpsw_priv {
u8 mac_addr[ETH_ALEN];
bool rx_pause;
bool tx_pause;
bool mqprio_hw;
int fifo_bw[CPSW_TC_NUM];
int shp_cfg_speed;
u32 emac_port;
struct cpsw_common *cpsw;
};
......@@ -968,8 +980,8 @@ static int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget)
/* process every unprocessed channel */
ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
if (!(ch_map & 0x01))
for (ch = 0, num_tx = 0; ch_map & 0xff; ch_map <<= 1, ch++) {
if (!(ch_map & 0x80))
continue;
txv = &cpsw->txv[ch];
......@@ -1078,6 +1090,38 @@ static void cpsw_set_slave_mac(struct cpsw_slave *slave,
slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
}
static bool cpsw_shp_is_off(struct cpsw_priv *priv)
{
struct cpsw_common *cpsw = priv->cpsw;
struct cpsw_slave *slave;
u32 shift, mask, val;
val = readl_relaxed(&cpsw->regs->ptype);
slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
mask = 7 << shift;
val = val & mask;
return !val;
}
static void cpsw_fifo_shp_on(struct cpsw_priv *priv, int fifo, int on)
{
struct cpsw_common *cpsw = priv->cpsw;
struct cpsw_slave *slave;
u32 shift, mask, val;
val = readl_relaxed(&cpsw->regs->ptype);
slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
mask = (1 << --fifo) << shift;
val = on ? val | mask : val & ~mask;
writel_relaxed(val, &cpsw->regs->ptype);
}
static void _cpsw_adjust_link(struct cpsw_slave *slave,
struct cpsw_priv *priv, bool *link)
{
......@@ -1117,6 +1161,12 @@ static void _cpsw_adjust_link(struct cpsw_slave *slave,
mac_control |= BIT(4);
*link = true;
if (priv->shp_cfg_speed &&
priv->shp_cfg_speed != slave->phy->speed &&
!cpsw_shp_is_off(priv))
dev_warn(priv->dev,
"Speed was changed, CBS shaper speeds are changed!");
} else {
mac_control = 0;
/* disable forwarding */
......@@ -1578,6 +1628,231 @@ static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
soft_reset_slave(slave);
}
static int cpsw_tc_to_fifo(int tc, int num_tc)
{
if (tc == num_tc - 1)
return 0;
return CPSW_FIFO_SHAPERS_NUM - tc;
}
static int cpsw_set_fifo_bw(struct cpsw_priv *priv, int fifo, int bw)
{
struct cpsw_common *cpsw = priv->cpsw;
u32 val = 0, send_pct, shift;
struct cpsw_slave *slave;
int pct = 0, i;
if (bw > priv->shp_cfg_speed * 1000)
goto err;
/* shaping has to stay enabled for highest fifos linearly
* and fifo bw no more then interface can allow
*/
slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
send_pct = slave_read(slave, SEND_PERCENT);
for (i = CPSW_FIFO_SHAPERS_NUM; i > 0; i--) {
if (!bw) {
if (i >= fifo || !priv->fifo_bw[i])
continue;
dev_warn(priv->dev, "Prev FIFO%d is shaped", i);
continue;
}
if (!priv->fifo_bw[i] && i > fifo) {
dev_err(priv->dev, "Upper FIFO%d is not shaped", i);
return -EINVAL;
}
shift = (i - 1) * 8;
if (i == fifo) {
send_pct &= ~(CPSW_PCT_MASK << shift);
val = DIV_ROUND_UP(bw, priv->shp_cfg_speed * 10);
if (!val)
val = 1;
send_pct |= val << shift;
pct += val;
continue;
}
if (priv->fifo_bw[i])
pct += (send_pct >> shift) & CPSW_PCT_MASK;
}
if (pct >= 100)
goto err;
slave_write(slave, send_pct, SEND_PERCENT);
priv->fifo_bw[fifo] = bw;
dev_warn(priv->dev, "set FIFO%d bw = %d\n", fifo,
DIV_ROUND_CLOSEST(val * priv->shp_cfg_speed, 100));
return 0;
err:
dev_err(priv->dev, "Bandwidth doesn't fit in tc configuration");
return -EINVAL;
}
static int cpsw_set_fifo_rlimit(struct cpsw_priv *priv, int fifo, int bw)
{
struct cpsw_common *cpsw = priv->cpsw;
struct cpsw_slave *slave;
u32 tx_in_ctl_rg, val;
int ret;
ret = cpsw_set_fifo_bw(priv, fifo, bw);
if (ret)
return ret;
slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
tx_in_ctl_rg = cpsw->version == CPSW_VERSION_1 ?
CPSW1_TX_IN_CTL : CPSW2_TX_IN_CTL;
if (!bw)
cpsw_fifo_shp_on(priv, fifo, bw);
val = slave_read(slave, tx_in_ctl_rg);
if (cpsw_shp_is_off(priv)) {
/* disable FIFOs rate limited queues */
val &= ~(0xf << CPSW_FIFO_RATE_EN_SHIFT);
/* set type of FIFO queues to normal priority mode */
val &= ~(3 << CPSW_FIFO_QUEUE_TYPE_SHIFT);
/* set type of FIFO queues to be rate limited */
if (bw)
val |= 2 << CPSW_FIFO_QUEUE_TYPE_SHIFT;
else
priv->shp_cfg_speed = 0;
}
/* toggle a FIFO rate limited queue */
if (bw)
val |= BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
else
val &= ~BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
slave_write(slave, val, tx_in_ctl_rg);
/* FIFO transmit shape enable */
cpsw_fifo_shp_on(priv, fifo, bw);
return 0;
}
/* Defaults:
* class A - prio 3
* class B - prio 2
* shaping for class A should be set first
*/
static int cpsw_set_cbs(struct net_device *ndev,
struct tc_cbs_qopt_offload *qopt)
{
struct cpsw_priv *priv = netdev_priv(ndev);
struct cpsw_common *cpsw = priv->cpsw;
struct cpsw_slave *slave;
int prev_speed = 0;
int tc, ret, fifo;
u32 bw = 0;
tc = netdev_txq_to_tc(priv->ndev, qopt->queue);
/* enable channels in backward order, as highest FIFOs must be rate
* limited first and for compliance with CPDMA rate limited channels
* that also used in bacward order. FIFO0 cannot be rate limited.
*/
fifo = cpsw_tc_to_fifo(tc, ndev->num_tc);
if (!fifo) {
dev_err(priv->dev, "Last tc%d can't be rate limited", tc);
return -EINVAL;
}
/* do nothing, it's disabled anyway */
if (!qopt->enable && !priv->fifo_bw[fifo])
return 0;
/* shapers can be set if link speed is known */
slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
if (slave->phy && slave->phy->link) {
if (priv->shp_cfg_speed &&
priv->shp_cfg_speed != slave->phy->speed)
prev_speed = priv->shp_cfg_speed;
priv->shp_cfg_speed = slave->phy->speed;
}
if (!priv->shp_cfg_speed) {
dev_err(priv->dev, "Link speed is not known");
return -1;
}
ret = pm_runtime_get_sync(cpsw->dev);
if (ret < 0) {
pm_runtime_put_noidle(cpsw->dev);
return ret;
}
bw = qopt->enable ? qopt->idleslope : 0;
ret = cpsw_set_fifo_rlimit(priv, fifo, bw);
if (ret) {
priv->shp_cfg_speed = prev_speed;
prev_speed = 0;
}
if (bw && prev_speed)
dev_warn(priv->dev,
"Speed was changed, CBS shaper speeds are changed!");
pm_runtime_put_sync(cpsw->dev);
return ret;
}
static void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
{
int fifo, bw;
for (fifo = CPSW_FIFO_SHAPERS_NUM; fifo > 0; fifo--) {
bw = priv->fifo_bw[fifo];
if (!bw)
continue;
cpsw_set_fifo_rlimit(priv, fifo, bw);
}
}
static void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
{
struct cpsw_common *cpsw = priv->cpsw;
u32 tx_prio_map = 0;
int i, tc, fifo;
u32 tx_prio_rg;
if (!priv->mqprio_hw)
return;
for (i = 0; i < 8; i++) {
tc = netdev_get_prio_tc_map(priv->ndev, i);
fifo = CPSW_FIFO_SHAPERS_NUM - tc;
tx_prio_map |= fifo << (4 * i);
}
tx_prio_rg = cpsw->version == CPSW_VERSION_1 ?
CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
slave_write(slave, tx_prio_map, tx_prio_rg);
}
/* restore resources after port reset */
static void cpsw_restore(struct cpsw_priv *priv)
{
/* restore MQPRIO offload */
for_each_slave(priv, cpsw_mqprio_resume, priv);
/* restore CBS offload */
for_each_slave(priv, cpsw_cbs_resume, priv);
}
static int cpsw_ndo_open(struct net_device *ndev)
{
struct cpsw_priv *priv = netdev_priv(ndev);
......@@ -1657,6 +1932,8 @@ static int cpsw_ndo_open(struct net_device *ndev)
}
cpsw_restore(priv);
/* Enable Interrupt pacing if configured */
if (cpsw->coal_intvl != 0) {
struct ethtool_coalesce coal;
......@@ -2191,6 +2468,78 @@ static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
return ret;
}
static int cpsw_set_mqprio(struct net_device *ndev, void *type_data)
{
struct tc_mqprio_qopt_offload *mqprio = type_data;
struct cpsw_priv *priv = netdev_priv(ndev);
struct cpsw_common *cpsw = priv->cpsw;
int fifo, num_tc, count, offset;
struct cpsw_slave *slave;
u32 tx_prio_map = 0;
int i, tc, ret;
num_tc = mqprio->qopt.num_tc;
if (num_tc > CPSW_TC_NUM)
return -EINVAL;
if (mqprio->mode != TC_MQPRIO_MODE_DCB)
return -EINVAL;
ret = pm_runtime_get_sync(cpsw->dev);
if (ret < 0) {
pm_runtime_put_noidle(cpsw->dev);
return ret;
}
if (num_tc) {
for (i = 0; i < 8; i++) {
tc = mqprio->qopt.prio_tc_map[i];
fifo = cpsw_tc_to_fifo(tc, num_tc);
tx_prio_map |= fifo << (4 * i);
}
netdev_set_num_tc(ndev, num_tc);
for (i = 0; i < num_tc; i++) {
count = mqprio->qopt.count[i];
offset = mqprio->qopt.offset[i];
netdev_set_tc_queue(ndev, i, count, offset);
}
}
if (!mqprio->qopt.hw) {
/* restore default configuration */
netdev_reset_tc(ndev);
tx_prio_map = TX_PRIORITY_MAPPING;
}
priv->mqprio_hw = mqprio->qopt.hw;
offset = cpsw->version == CPSW_VERSION_1 ?
CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
slave_write(slave, tx_prio_map, offset);
pm_runtime_put_sync(cpsw->dev);
return 0;
}
static int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
void *type_data)
{
switch (type) {
case TC_SETUP_QDISC_CBS:
return cpsw_set_cbs(ndev, type_data);
case TC_SETUP_QDISC_MQPRIO:
return cpsw_set_mqprio(ndev, type_data);
default:
return -EOPNOTSUPP;
}
}
static const struct net_device_ops cpsw_netdev_ops = {
.ndo_open = cpsw_ndo_open,
.ndo_stop = cpsw_ndo_stop,
......@@ -2206,6 +2555,7 @@ static const struct net_device_ops cpsw_netdev_ops = {
#endif
.ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
.ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
.ndo_setup_tc = cpsw_ndo_setup_tc,
};
static int cpsw_get_regs_len(struct net_device *ndev)
......@@ -2432,7 +2782,7 @@ static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
void (*handler)(void *, int, int);
struct netdev_queue *queue;
struct cpsw_vector *vec;
int ret, *ch;
int ret, *ch, vch;
if (rx) {
ch = &cpsw->rx_ch_num;
......@@ -2445,7 +2795,8 @@ static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
}
while (*ch < ch_num) {
vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
vch = rx ? *ch : 7 - *ch;
vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx);
queue = netdev_get_tx_queue(priv->ndev, *ch);
queue->tx_maxrate = 0;
......@@ -2982,7 +3333,7 @@ static int cpsw_probe(struct platform_device *pdev)
u32 slave_offset, sliver_offset, slave_size;
const struct soc_device_attribute *soc;
struct cpsw_common *cpsw;
int ret = 0, i;
int ret = 0, i, ch;
int irq;
cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
......@@ -3157,7 +3508,8 @@ static int cpsw_probe(struct platform_device *pdev)
if (soc)
cpsw->quirk_irq = 1;
cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
ch = cpsw->quirk_irq ? 0 : 7;
cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, ch, cpsw_tx_handler, 0);
if (IS_ERR(cpsw->txv[0].ch)) {
dev_err(priv->dev, "error initializing tx dma channel\n");
ret = PTR_ERR(cpsw->txv[0].ch);
......
drivers/net/ethernet/ti/davinci_cpdma.c
View file @ d3585edf
......@@ -406,37 +406,36 @@ static int cpdma_chan_fit_rate(struct cpdma_chan *ch, u32 rate,
struct cpdma_chan *chan;
u32 old_rate = ch->rate;
u32 new_rmask = 0;
int rlim = 1;
int rlim = 0;
int i;
*prio_mode = 0;
for (i = tx_chan_num(0); i < tx_chan_num(CPDMA_MAX_CHANNELS); i++) {
chan = ctlr->channels[i];
if (!chan) {
rlim = 0;
if (!chan)
continue;
}
if (chan == ch)
chan->rate = rate;
if (chan->rate) {
if (rlim) {
new_rmask |= chan->mask;
} else {
ch->rate = old_rate;
dev_err(ctlr->dev, "Prev channel of %dch is not rate limited\n",
chan->chan_num);
return -EINVAL;
}
} else {
*prio_mode = 1;
rlim = 0;
rlim = 1;
new_rmask |= chan->mask;
continue;
}
if (rlim)
goto err;
}
*rmask = new_rmask;
*prio_mode = rlim;
return 0;
err:
ch->rate = old_rate;
dev_err(ctlr->dev, "Upper cpdma ch%d is not rate limited\n",
chan->chan_num);
return -EINVAL;
}
static u32 cpdma_chan_set_factors(struct cpdma_ctlr *ctlr,
......
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