Commit d39f77b0 authored by Andrew Jackson's avatar Andrew Jackson Committed by Wolfram Sang

i2c: designware: prevent early stop on TX FIFO empty

If the Designware core is configured with IC_EMPTYFIFO_HOLD_MASTER_EN
set to zero, allowing the TX FIFO to become empty causes a STOP
condition to be generated on the I2C bus. If the transmit FIFO
threshold is set too high, an erroneous STOP condition can be
generated on long transfers - particularly where the interrupt
latency is extended.
Signed-off-by: default avatarAndrew Jackson <Andrew.Jackson@arm.com>
Signed-off-by: default avatarLiviu Dudau <Liviu.Dudau@arm.com>
Tested-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
parent 27caca9d
...@@ -359,7 +359,7 @@ int i2c_dw_init(struct dw_i2c_dev *dev) ...@@ -359,7 +359,7 @@ int i2c_dw_init(struct dw_i2c_dev *dev)
} }
/* Configure Tx/Rx FIFO threshold levels */ /* Configure Tx/Rx FIFO threshold levels */
dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
dw_writel(dev, 0, DW_IC_RX_TL); dw_writel(dev, 0, DW_IC_RX_TL);
/* configure the i2c master */ /* configure the i2c master */
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment