Commit d45bc58d authored by Marc Gonzalez's avatar Marc Gonzalez Committed by Boris Brezillon

mtd: nand: import nand_hw_control_init()

The code to initialize a struct nand_hw_control is duplicated across
several drivers. Factorize it using an inline function.
Signed-off-by: default avatarMarc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
parent 29b4817d
...@@ -761,8 +761,7 @@ static int bf5xx_nand_probe(struct platform_device *pdev) ...@@ -761,8 +761,7 @@ static int bf5xx_nand_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, info); platform_set_drvdata(pdev, info);
spin_lock_init(&info->controller.lock); nand_hw_control_init(&info->controller);
init_waitqueue_head(&info->controller.wq);
info->device = &pdev->dev; info->device = &pdev->dev;
info->platform = plat; info->platform = plat;
......
...@@ -2370,8 +2370,7 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc) ...@@ -2370,8 +2370,7 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
init_completion(&ctrl->done); init_completion(&ctrl->done);
init_completion(&ctrl->dma_done); init_completion(&ctrl->dma_done);
spin_lock_init(&ctrl->controller.lock); nand_hw_control_init(&ctrl->controller);
init_waitqueue_head(&ctrl->controller.wq);
INIT_LIST_HEAD(&ctrl->host_list); INIT_LIST_HEAD(&ctrl->host_list);
/* NAND register range */ /* NAND register range */
......
...@@ -1249,8 +1249,7 @@ static void __init init_mtd_structs(struct mtd_info *mtd) ...@@ -1249,8 +1249,7 @@ static void __init init_mtd_structs(struct mtd_info *mtd)
nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE; nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE;
nand->IO_ADDR_R = nand->IO_ADDR_W = doc->virtadr + DOC_IOSPACE_DATA; nand->IO_ADDR_R = nand->IO_ADDR_W = doc->virtadr + DOC_IOSPACE_DATA;
nand->controller = &nand->hwcontrol; nand->controller = &nand->hwcontrol;
spin_lock_init(&nand->controller->lock); nand_hw_control_init(nand->controller);
init_waitqueue_head(&nand->controller->wq);
/* methods */ /* methods */
nand->cmdfunc = docg4_command; nand->cmdfunc = docg4_command;
......
...@@ -879,8 +879,7 @@ static int fsl_elbc_nand_probe(struct platform_device *pdev) ...@@ -879,8 +879,7 @@ static int fsl_elbc_nand_probe(struct platform_device *pdev)
} }
elbc_fcm_ctrl->counter++; elbc_fcm_ctrl->counter++;
spin_lock_init(&elbc_fcm_ctrl->controller.lock); nand_hw_control_init(&elbc_fcm_ctrl->controller);
init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);
fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl; fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
} else { } else {
elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
......
...@@ -987,8 +987,7 @@ static int fsl_ifc_nand_probe(struct platform_device *dev) ...@@ -987,8 +987,7 @@ static int fsl_ifc_nand_probe(struct platform_device *dev)
ifc_nand_ctrl->addr = NULL; ifc_nand_ctrl->addr = NULL;
fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl; fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
spin_lock_init(&ifc_nand_ctrl->controller.lock); nand_hw_control_init(&ifc_nand_ctrl->controller);
init_waitqueue_head(&ifc_nand_ctrl->controller.wq);
} else { } else {
ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand; ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
} }
......
...@@ -368,9 +368,8 @@ static int jz4780_nand_probe(struct platform_device *pdev) ...@@ -368,9 +368,8 @@ static int jz4780_nand_probe(struct platform_device *pdev)
nfc->dev = dev; nfc->dev = dev;
nfc->num_banks = num_banks; nfc->num_banks = num_banks;
spin_lock_init(&nfc->controller.lock); nand_hw_control_init(&nfc->controller);
INIT_LIST_HEAD(&nfc->chips); INIT_LIST_HEAD(&nfc->chips);
init_waitqueue_head(&nfc->controller.wq);
ret = jz4780_nand_init_chips(nfc, pdev); ret = jz4780_nand_init_chips(nfc, pdev);
if (ret) { if (ret) {
......
...@@ -3191,8 +3191,7 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) ...@@ -3191,8 +3191,7 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)
if (!chip->controller) { if (!chip->controller) {
chip->controller = &chip->hwcontrol; chip->controller = &chip->hwcontrol;
spin_lock_init(&chip->controller->lock); nand_hw_control_init(chip->controller);
init_waitqueue_head(&chip->controller->wq);
} }
} }
......
...@@ -218,8 +218,7 @@ static int ndfc_probe(struct platform_device *ofdev) ...@@ -218,8 +218,7 @@ static int ndfc_probe(struct platform_device *ofdev)
ndfc = &ndfc_ctrl[cs]; ndfc = &ndfc_ctrl[cs];
ndfc->chip_select = cs; ndfc->chip_select = cs;
spin_lock_init(&ndfc->ndfc_control.lock); nand_hw_control_init(&ndfc->ndfc_control);
init_waitqueue_head(&ndfc->ndfc_control.wq);
ndfc->ofdev = ofdev; ndfc->ofdev = ofdev;
dev_set_drvdata(&ofdev->dev, ndfc); dev_set_drvdata(&ofdev->dev, ndfc);
......
...@@ -1810,8 +1810,7 @@ static int alloc_nand_resource(struct platform_device *pdev) ...@@ -1810,8 +1810,7 @@ static int alloc_nand_resource(struct platform_device *pdev)
chip->cmdfunc = nand_cmdfunc; chip->cmdfunc = nand_cmdfunc;
} }
spin_lock_init(&chip->controller->lock); nand_hw_control_init(chip->controller);
init_waitqueue_head(&chip->controller->wq);
info->clk = devm_clk_get(&pdev->dev, NULL); info->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(info->clk)) { if (IS_ERR(info->clk)) {
dev_err(&pdev->dev, "failed to get nand clock\n"); dev_err(&pdev->dev, "failed to get nand clock\n");
......
...@@ -1957,8 +1957,7 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) ...@@ -1957,8 +1957,7 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
INIT_LIST_HEAD(&nandc->desc_list); INIT_LIST_HEAD(&nandc->desc_list);
INIT_LIST_HEAD(&nandc->host_list); INIT_LIST_HEAD(&nandc->host_list);
spin_lock_init(&nandc->controller.lock); nand_hw_control_init(&nandc->controller);
init_waitqueue_head(&nandc->controller.wq);
return 0; return 0;
} }
......
...@@ -977,8 +977,7 @@ static int s3c24xx_nand_probe(struct platform_device *pdev) ...@@ -977,8 +977,7 @@ static int s3c24xx_nand_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, info); platform_set_drvdata(pdev, info);
spin_lock_init(&info->controller.lock); nand_hw_control_init(&info->controller);
init_waitqueue_head(&info->controller.wq);
/* get the clock source and enable it */ /* get the clock source and enable it */
......
...@@ -2175,8 +2175,7 @@ static int sunxi_nfc_probe(struct platform_device *pdev) ...@@ -2175,8 +2175,7 @@ static int sunxi_nfc_probe(struct platform_device *pdev)
return -ENOMEM; return -ENOMEM;
nfc->dev = dev; nfc->dev = dev;
spin_lock_init(&nfc->controller.lock); nand_hw_control_init(&nfc->controller);
init_waitqueue_head(&nfc->controller.wq);
INIT_LIST_HEAD(&nfc->chips); INIT_LIST_HEAD(&nfc->chips);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0); r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
......
...@@ -303,8 +303,7 @@ static int __init txx9ndfmc_probe(struct platform_device *dev) ...@@ -303,8 +303,7 @@ static int __init txx9ndfmc_probe(struct platform_device *dev)
dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n", dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
(gbusclk + 500000) / 1000000, hold, spw); (gbusclk + 500000) / 1000000, hold, spw);
spin_lock_init(&drvdata->hw_control.lock); nand_hw_control_init(&drvdata->hw_control);
init_waitqueue_head(&drvdata->hw_control.wq);
platform_set_drvdata(dev, drvdata); platform_set_drvdata(dev, drvdata);
txx9ndfmc_initialize(dev); txx9ndfmc_initialize(dev);
......
...@@ -460,6 +460,13 @@ struct nand_hw_control { ...@@ -460,6 +460,13 @@ struct nand_hw_control {
wait_queue_head_t wq; wait_queue_head_t wq;
}; };
static inline void nand_hw_control_init(struct nand_hw_control *nfc)
{
nfc->active = NULL;
spin_lock_init(&nfc->lock);
init_waitqueue_head(&nfc->wq);
}
/** /**
* struct nand_ecc_ctrl - Control structure for ECC * struct nand_ecc_ctrl - Control structure for ECC
* @mode: ECC mode * @mode: ECC mode
......
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