Commit d50e5c24 authored by Alan Harrison's avatar Alan Harrison Committed by Alex Deucher

drm/amdgpu: Add to initialization of mmVCE_VCPU_CNTL register

Add a bit needed during initialization into the driver, where it is supposed
to be.  Currently, this is happening in the VCE firmware, and although
functional, this is the correct place to perform this initialization.
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlan Harrison <Alan.Harrison@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c10c8f7c
...@@ -510,6 +510,8 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx) ...@@ -510,6 +510,8 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
WREG32(mmVCE_LMI_SWAP_CNTL, 0); WREG32(mmVCE_LMI_SWAP_CNTL, 0);
WREG32(mmVCE_LMI_SWAP_CNTL1, 0); WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
WREG32(mmVCE_LMI_VM_CTRL, 0); WREG32(mmVCE_LMI_VM_CTRL, 0);
WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000);
if (adev->asic_type >= CHIP_STONEY) { if (adev->asic_type >= CHIP_STONEY) {
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8)); WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));
......
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