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Commit d5edc4ec authored by Thierry Reding's avatar Thierry Reding
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ARM: tegra: colibri: Properly align pin names 

Align pin names on subsequent lines with the first the name of the first
pin in the first line.
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 3791d1cc
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Showing with 36 additions and 36 deletions
arch/arm/boot/dts/tegra30-colibri.dtsi
View file @ d5edc4ec
...@@ -39,7 +39,7 @@ pv2 { ...@@ -39,7 +39,7 @@ pv2 {
/* Colibri Backlight PWM<A> */ /* Colibri Backlight PWM<A> */
sdmmc3_dat3_pb4 { sdmmc3_dat3_pb4 {
nvidia,pins = "sdmmc3_dat3_pb4"; nvidia,pins = "sdmmc3_dat3_pb4";
nvidia,function = "pwm0"; nvidia,function = "pwm0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,tristate = <TEGRA_PIN_DISABLE>;
...@@ -74,11 +74,11 @@ kb_row10_ps2 { ...@@ -74,11 +74,11 @@ kb_row10_ps2 {
nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,tristate = <TEGRA_PIN_DISABLE>;
}; };
kb_row11_ps3 { kb_row11_ps3 {
nvidia,pins = "kb_row11_ps3", nvidia,pins = "kb_row11_ps3",
"kb_row12_ps4", "kb_row12_ps4",
"kb_row13_ps5", "kb_row13_ps5",
"kb_row14_ps6", "kb_row14_ps6",
"kb_row15_ps7"; "kb_row15_ps7";
nvidia,function = "sdmmc2"; nvidia,function = "sdmmc2";
nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,tristate = <TEGRA_PIN_DISABLE>;
...@@ -86,17 +86,17 @@ kb_row11_ps3 { ...@@ -86,17 +86,17 @@ kb_row11_ps3 {
/* Colibri SSP */ /* Colibri SSP */
ulpi_clk_py0 { ulpi_clk_py0 {
nvidia,pins = "ulpi_clk_py0", nvidia,pins = "ulpi_clk_py0",
"ulpi_dir_py1", "ulpi_dir_py1",
"ulpi_nxt_py2", "ulpi_nxt_py2",
"ulpi_stp_py3"; "ulpi_stp_py3";
nvidia,function = "spi1"; nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,tristate = <TEGRA_PIN_DISABLE>;
}; };
sdmmc3_dat6_pd3 { sdmmc3_dat6_pd3 {
nvidia,pins = "sdmmc3_dat6_pd3", nvidia,pins = "sdmmc3_dat6_pd3",
"sdmmc3_dat7_pd4"; "sdmmc3_dat7_pd4";
nvidia,function = "spdif"; nvidia,function = "spdif";
nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>; nvidia,tristate = <TEGRA_PIN_ENABLE>;
...@@ -104,14 +104,14 @@ sdmmc3_dat6_pd3 { ...@@ -104,14 +104,14 @@ sdmmc3_dat6_pd3 {
/* Colibri UART_A */ /* Colibri UART_A */
ulpi_data0 { ulpi_data0 {
nvidia,pins = "ulpi_data0_po1", nvidia,pins = "ulpi_data0_po1",
"ulpi_data1_po2", "ulpi_data1_po2",
"ulpi_data2_po3", "ulpi_data2_po3",
"ulpi_data3_po4", "ulpi_data3_po4",
"ulpi_data4_po5", "ulpi_data4_po5",
"ulpi_data5_po6", "ulpi_data5_po6",
"ulpi_data6_po7", "ulpi_data6_po7",
"ulpi_data7_po0"; "ulpi_data7_po0";
nvidia,function = "uarta"; nvidia,function = "uarta";
nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,tristate = <TEGRA_PIN_DISABLE>;
...@@ -119,10 +119,10 @@ ulpi_data0 { ...@@ -119,10 +119,10 @@ ulpi_data0 {
/* Colibri UART_B */ /* Colibri UART_B */
gmi_a16_pj7 { gmi_a16_pj7 {
nvidia,pins = "gmi_a16_pj7", nvidia,pins = "gmi_a16_pj7",
"gmi_a17_pb0", "gmi_a17_pb0",
"gmi_a18_pb1", "gmi_a18_pb1",
"gmi_a19_pk7"; "gmi_a19_pk7";
nvidia,function = "uartd"; nvidia,function = "uartd";
nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,tristate = <TEGRA_PIN_DISABLE>;
...@@ -130,8 +130,8 @@ gmi_a16_pj7 { ...@@ -130,8 +130,8 @@ gmi_a16_pj7 {
/* Colibri UART_C */ /* Colibri UART_C */
uart2_rxd { uart2_rxd {
nvidia,pins = "uart2_rxd_pc3", nvidia,pins = "uart2_rxd_pc3",
"uart2_txd_pc2"; "uart2_txd_pc2";
nvidia,function = "uartb"; nvidia,function = "uartb";
nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,tristate = <TEGRA_PIN_DISABLE>;
...@@ -139,21 +139,21 @@ uart2_rxd { ...@@ -139,21 +139,21 @@ uart2_rxd {
/* eMMC */ /* eMMC */
sdmmc4_clk_pcc4 { sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4", nvidia,pins = "sdmmc4_clk_pcc4",
"sdmmc4_rst_n_pcc3"; "sdmmc4_rst_n_pcc3";
nvidia,function = "sdmmc4"; nvidia,function = "sdmmc4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,tristate = <TEGRA_PIN_DISABLE>;
}; };
sdmmc4_dat0_paa0 { sdmmc4_dat0_paa0 {
nvidia,pins = "sdmmc4_dat0_paa0", nvidia,pins = "sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1", "sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2", "sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3", "sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4", "sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5", "sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6", "sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7"; "sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4"; nvidia,function = "sdmmc4";
nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,tristate = <TEGRA_PIN_DISABLE>;
......
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