Commit d619a956 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Mauro Carvalho Chehab

media: dt-bindings: rcar_vin: Document RZ/G1 per-board settings

The R-Car Gen2 per-board settings apply to RZ/G1, too.

Fixes: 1d14a5ea ("media: dt-bindings: media: rcar_vin: add device tree support for r8a774[35]")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@kernel.org>
parent c05b9d7b
...@@ -44,7 +44,7 @@ on Gen3 and RZ/G2 platforms to a CSI-2 receiver. ...@@ -44,7 +44,7 @@ on Gen3 and RZ/G2 platforms to a CSI-2 receiver.
Additionally, an alias named vinX will need to be created to specify Additionally, an alias named vinX will need to be created to specify
which video input device this is. which video input device this is.
The per-board settings Gen2 platforms: The per-board settings for Gen2 and RZ/G1 platforms:
- port - sub-node describing a single endpoint connected to the VIN - port - sub-node describing a single endpoint connected to the VIN
from external SoC pins as described in video-interfaces.txt[1]. from external SoC pins as described in video-interfaces.txt[1].
...@@ -64,7 +64,7 @@ The per-board settings Gen2 platforms: ...@@ -64,7 +64,7 @@ The per-board settings Gen2 platforms:
- data-enable-active: polarity of CLKENB signal, see [1] for - data-enable-active: polarity of CLKENB signal, see [1] for
description. Default is active high. description. Default is active high.
The per-board settings Gen3 and RZ/G2 platforms: The per-board settings for Gen3 and RZ/G2 platforms:
Gen3 and RZ/G2 platforms can support both a single connected parallel input Gen3 and RZ/G2 platforms can support both a single connected parallel input
source from external SoC pins (port@0) and/or multiple parallel input sources source from external SoC pins (port@0) and/or multiple parallel input sources
......
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