Commit d64f1404 authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'tegra-for-6.6-arm64-dt' of...

Merge tag 'tegra-for-6.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt

arm64: tegra: Device tree changes for v6.6-rc1

The majority of this is fixes all over the place for DT schema
validation warnings. However, there are also cleanups for some things in
DT and audio support is added on IGX Orin. Jetson Orin NX and Nano also
gain a new thermal trip point to help keep the device cool at moderate
loads.

* tag 'tegra-for-6.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (22 commits)
  arm64: tegra: Add blank lines for better readability
  arm64: tegra: Remove {clock,reset}-names from VIC powergate
  arm64: tegra: Drop incorrect maxim,disable-etr on Smaug
  arm64: tegra: Add SPI device tree nodes for Tegra234
  arm64: tegra: Enable UARTA and UARTE for Orin Nano
  arm64: tegra: Add UARTE device tree node on Tegra234
  arm64: tegra: Adapt to LP855X bindings changes
  arm64: tegra: Add PCIe and DP 3.3V supplies
  arm64: tegra: Add missing reset-names for Tegra HS UART
  arm64: tegra: Remove current-speed for SBSA UART
  arm64: tegra: smaug: Remove reg-shift for high-speed UART
  arm64: tegra: Remove dmas and dma-names for debug UART
  arm64: tegra: Add 35°C trip point for Jetson Orin NX/Nano
  arm64: tegra: Remove duplicate PCI nodes
  arm64: tegra: Sort PCI nodes correctly on Orin
  arm64: tegra: Add audio support for IGX Orin
  arm64: tegra: Update CPU OPP tables
  arm64: tegra: Fix HSUART for Smaug
  arm64: tegra: Fix HSUART for Jetson AGX Orin
  arm64: tegra: Add missing alias for NVIDIA IGX Orin
  ...

Link: https://lore.kernel.org/r/20230728094129.3587109-4-thierry.reding@gmail.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents caeca8a4 d7fb6468
......@@ -531,6 +531,8 @@ soc_warm_reset_l {
};
serial@70006000 {
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
};
......
......@@ -135,7 +135,8 @@ tegra_ahub: ahub@2900800 {
clocks = <&bpmp TEGRA186_CLK_AHUB>;
clock-names = "ahub";
assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
assigned-clock-rates = <81600000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x02900800 0x02900800 0x11800>;
......
......@@ -231,7 +231,8 @@ tegra_ahub: ahub@2900800 {
clocks = <&bpmp TEGRA194_CLK_AHUB>;
clock-names = "ahub";
assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>;
assigned-clock-rates = <81600000>;
status = "disabled";
#address-cells = <2>;
......
......@@ -28,6 +28,8 @@ gpu@57000000 {
/* debug port */
serial@70006000 {
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
};
......
......@@ -58,19 +58,17 @@ backlight: backlight@2c {
dev-ctrl = /bits/ 8 <0x80>;
init-brt = /bits/ 8 <0xff>;
pwm-period = <29334>;
pwms = <&pwm 0 29334>;
pwm-names = "lp8557";
/* boost frequency 1 MHz */
rom_13h {
rom-13h {
rom-addr = /bits/ 8 <0x13>;
rom-val = /bits/ 8 <0x01>;
};
/* 3 LED string */
rom_14h {
rom-14h {
rom-addr = /bits/ 8 <0x14>;
rom-val = /bits/ 8 <0x87>;
};
......
......@@ -21,6 +21,8 @@ memory@80000000 {
/* debug port */
serial@70006000 {
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
};
......
......@@ -1321,6 +1321,8 @@ shutdown {
};
serial@70006000 {
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
};
......
......@@ -126,6 +126,8 @@ dvfs_pwm_pbb1 {
/* debug port */
serial@70006000 {
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
};
......
......@@ -1312,11 +1312,15 @@ shutdown {
};
serial@70006000 {
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
};
uartd: serial@70006300 {
compatible = "nvidia,tegra30-hsuart";
reset-names = "serial";
/delete-property/ reg-shift;
status = "okay";
bluetooth {
......@@ -1391,7 +1395,6 @@ max77621_gpu: regulator@1c {
maxim,dvs-default-state = <1>;
maxim,enable-active-discharge;
maxim,enable-bias-control;
maxim,disable-etr;
maxim,enable-gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
maxim,externally-enable;
};
......
......@@ -916,9 +916,7 @@ pd_venc: venc {
pd_vic: vic {
clocks = <&tegra_car TEGRA210_CLK_VIC03>;
clock-names = "vic";
resets = <&tegra_car 178>;
reset-names = "vic";
#power-domain-cells = <0>;
};
......@@ -1386,7 +1384,8 @@ tegra_ahub: ahub@702d0800 {
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
clock-names = "ahub";
assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>;
assigned-clock-rates = <81600000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x702d0000 0x702d0000 0x0000e400>;
......
// SPDX-License-Identifier: GPL-2.0
#include "tegra234.dtsi"
#include "tegra234-p3701.dtsi"
/ {
model = "NVIDIA Jetson AGX Orin";
......
// SPDX-License-Identifier: GPL-2.0
#include "tegra234.dtsi"
#include "tegra234-p3701.dtsi"
/ {
compatible = "nvidia,p3701-0008", "nvidia,tegra234";
......
// SPDX-License-Identifier: GPL-2.0
/ {
compatible = "nvidia,p3701", "nvidia,tegra234";
bus@0 {
aconnect@2900000 {
status = "okay";
ahub@2900800 {
status = "okay";
i2s@2901000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
i2s1_cif: endpoint {
remote-endpoint = <&xbar_i2s1>;
};
};
i2s1_port: port@1 {
reg = <1>;
i2s1_dap: endpoint {
dai-format = "i2s";
/* placeholder for external codec */
};
};
};
};
i2s@2901100 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
i2s2_cif: endpoint {
remote-endpoint = <&xbar_i2s2>;
};
};
i2s2_port: port@1 {
reg = <1>;
i2s2_dap: endpoint {
dai-format = "i2s";
/* placeholder for external codec */
};
};
};
};
i2s@2901300 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
i2s4_cif: endpoint {
remote-endpoint = <&xbar_i2s4>;
};
};
i2s4_port: port@1 {
reg = <1>;
i2s4_dap: endpoint {
dai-format = "i2s";
/* placeholder for external codec */
};
};
};
};
i2s@2901500 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
i2s6_cif: endpoint {
remote-endpoint = <&xbar_i2s6>;
};
};
i2s6_port: port@1 {
reg = <1>;
i2s6_dap: endpoint {
dai-format = "i2s";
/* placeholder for external codec */
};
};
};
};
sfc@2902000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sfc1_cif_in: endpoint {
remote-endpoint = <&xbar_sfc1_in>;
};
};
sfc1_out_port: port@1 {
reg = <1>;
sfc1_cif_out: endpoint {
remote-endpoint = <&xbar_sfc1_out>;
};
};
};
};
sfc@2902200 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sfc2_cif_in: endpoint {
remote-endpoint = <&xbar_sfc2_in>;
};
};
sfc2_out_port: port@1 {
reg = <1>;
sfc2_cif_out: endpoint {
remote-endpoint = <&xbar_sfc2_out>;
};
};
};
};
sfc@2902400 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sfc3_cif_in: endpoint {
remote-endpoint = <&xbar_sfc3_in>;
};
};
sfc3_out_port: port@1 {
reg = <1>;
sfc3_cif_out: endpoint {
remote-endpoint = <&xbar_sfc3_out>;
};
};
};
};
sfc@2902600 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sfc4_cif_in: endpoint {
remote-endpoint = <&xbar_sfc4_in>;
};
};
sfc4_out_port: port@1 {
reg = <1>;
sfc4_cif_out: endpoint {
remote-endpoint = <&xbar_sfc4_out>;
};
};
};
};
amx@2903000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
amx1_in1: endpoint {
remote-endpoint = <&xbar_amx1_in1>;
};
};
port@1 {
reg = <1>;
amx1_in2: endpoint {
remote-endpoint = <&xbar_amx1_in2>;
};
};
port@2 {
reg = <2>;
amx1_in3: endpoint {
remote-endpoint = <&xbar_amx1_in3>;
};
};
port@3 {
reg = <3>;
amx1_in4: endpoint {
remote-endpoint = <&xbar_amx1_in4>;
};
};
amx1_out_port: port@4 {
reg = <4>;
amx1_out: endpoint {
remote-endpoint = <&xbar_amx1_out>;
};
};
};
};
amx@2903100 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
amx2_in1: endpoint {
remote-endpoint = <&xbar_amx2_in1>;
};
};
port@1 {
reg = <1>;
amx2_in2: endpoint {
remote-endpoint = <&xbar_amx2_in2>;
};
};
port@2 {
reg = <2>;
amx2_in3: endpoint {
remote-endpoint = <&xbar_amx2_in3>;
};
};
port@3 {
reg = <3>;
amx2_in4: endpoint {
remote-endpoint = <&xbar_amx2_in4>;
};
};
amx2_out_port: port@4 {
reg = <4>;
amx2_out: endpoint {
remote-endpoint = <&xbar_amx2_out>;
};
};
};
};
amx@2903200 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
amx3_in1: endpoint {
remote-endpoint = <&xbar_amx3_in1>;
};
};
port@1 {
reg = <1>;
amx3_in2: endpoint {
remote-endpoint = <&xbar_amx3_in2>;
};
};
port@2 {
reg = <2>;
amx3_in3: endpoint {
remote-endpoint = <&xbar_amx3_in3>;
};
};
port@3 {
reg = <3>;
amx3_in4: endpoint {
remote-endpoint = <&xbar_amx3_in4>;
};
};
amx3_out_port: port@4 {
reg = <4>;
amx3_out: endpoint {
remote-endpoint = <&xbar_amx3_out>;
};
};
};
};
amx@2903300 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
amx4_in1: endpoint {
remote-endpoint = <&xbar_amx4_in1>;
};
};
port@1 {
reg = <1>;
amx4_in2: endpoint {
remote-endpoint = <&xbar_amx4_in2>;
};
};
port@2 {
reg = <2>;
amx4_in3: endpoint {
remote-endpoint = <&xbar_amx4_in3>;
};
};
port@3 {
reg = <3>;
amx4_in4: endpoint {
remote-endpoint = <&xbar_amx4_in4>;
};
};
amx4_out_port: port@4 {
reg = <4>;
amx4_out: endpoint {
remote-endpoint = <&xbar_amx4_out>;
};
};
};
};
adx@2903800 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adx1_in: endpoint {
remote-endpoint = <&xbar_adx1_in>;
};
};
adx1_out1_port: port@1 {
reg = <1>;
adx1_out1: endpoint {
remote-endpoint = <&xbar_adx1_out1>;
};
};
adx1_out2_port: port@2 {
reg = <2>;
adx1_out2: endpoint {
remote-endpoint = <&xbar_adx1_out2>;
};
};
adx1_out3_port: port@3 {
reg = <3>;
adx1_out3: endpoint {
remote-endpoint = <&xbar_adx1_out3>;
};
};
adx1_out4_port: port@4 {
reg = <4>;
adx1_out4: endpoint {
remote-endpoint = <&xbar_adx1_out4>;
};
};
};
};
adx@2903900 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adx2_in: endpoint {
remote-endpoint = <&xbar_adx2_in>;
};
};
adx2_out1_port: port@1 {
reg = <1>;
adx2_out1: endpoint {
remote-endpoint = <&xbar_adx2_out1>;
};
};
adx2_out2_port: port@2 {
reg = <2>;
adx2_out2: endpoint {
remote-endpoint = <&xbar_adx2_out2>;
};
};
adx2_out3_port: port@3 {
reg = <3>;
adx2_out3: endpoint {
remote-endpoint = <&xbar_adx2_out3>;
};
};
adx2_out4_port: port@4 {
reg = <4>;
adx2_out4: endpoint {
remote-endpoint = <&xbar_adx2_out4>;
};
};
};
};
adx@2903a00 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adx3_in: endpoint {
remote-endpoint = <&xbar_adx3_in>;
};
};
adx3_out1_port: port@1 {
reg = <1>;
adx3_out1: endpoint {
remote-endpoint = <&xbar_adx3_out1>;
};
};
adx3_out2_port: port@2 {
reg = <2>;
adx3_out2: endpoint {
remote-endpoint = <&xbar_adx3_out2>;
};
};
adx3_out3_port: port@3 {
reg = <3>;
adx3_out3: endpoint {
remote-endpoint = <&xbar_adx3_out3>;
};
};
adx3_out4_port: port@4 {
reg = <4>;
adx3_out4: endpoint {
remote-endpoint = <&xbar_adx3_out4>;
};
};
};
};
adx@2903b00 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adx4_in: endpoint {
remote-endpoint = <&xbar_adx4_in>;
};
};
adx4_out1_port: port@1 {
reg = <1>;
adx4_out1: endpoint {
remote-endpoint = <&xbar_adx4_out1>;
};
};
adx4_out2_port: port@2 {
reg = <2>;
adx4_out2: endpoint {
remote-endpoint = <&xbar_adx4_out2>;
};
};
adx4_out3_port: port@3 {
reg = <3>;
adx4_out3: endpoint {
remote-endpoint = <&xbar_adx4_out3>;
};
};
adx4_out4_port: port@4 {
reg = <4>;
adx4_out4: endpoint {
remote-endpoint = <&xbar_adx4_out4>;
};
};
};
};
dmic@2904200 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dmic3_cif: endpoint {
remote-endpoint = <&xbar_dmic3>;
};
};
dmic3_port: port@1 {
reg = <1>;
dmic3_dap: endpoint {
/* placeholder for external codec */
};
};
};
};
processing-engine@2908000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
ope1_cif_in_ep: endpoint {
remote-endpoint = <&xbar_ope1_in_ep>;
};
};
ope1_out_port: port@1 {
reg = <0x1>;
ope1_cif_out_ep: endpoint {
remote-endpoint = <&xbar_ope1_out_ep>;
};
};
};
};
mvc@290a000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mvc1_cif_in: endpoint {
remote-endpoint = <&xbar_mvc1_in>;
};
};
mvc1_out_port: port@1 {
reg = <1>;
mvc1_cif_out: endpoint {
remote-endpoint = <&xbar_mvc1_out>;
};
};
};
};
mvc@290a200 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mvc2_cif_in: endpoint {
remote-endpoint = <&xbar_mvc2_in>;
};
};
mvc2_out_port: port@1 {
reg = <1>;
mvc2_cif_out: endpoint {
remote-endpoint = <&xbar_mvc2_out>;
};
};
};
};
amixer@290bb00 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
mix_in1: endpoint {
remote-endpoint = <&xbar_mix_in1>;
};
};
port@1 {
reg = <0x1>;
mix_in2: endpoint {
remote-endpoint = <&xbar_mix_in2>;
};
};
port@2 {
reg = <0x2>;
mix_in3: endpoint {
remote-endpoint = <&xbar_mix_in3>;
};
};
port@3 {
reg = <0x3>;
mix_in4: endpoint {
remote-endpoint = <&xbar_mix_in4>;
};
};
port@4 {
reg = <0x4>;
mix_in5: endpoint {
remote-endpoint = <&xbar_mix_in5>;
};
};
port@5 {
reg = <0x5>;
mix_in6: endpoint {
remote-endpoint = <&xbar_mix_in6>;
};
};
port@6 {
reg = <0x6>;
mix_in7: endpoint {
remote-endpoint = <&xbar_mix_in7>;
};
};
port@7 {
reg = <0x7>;
mix_in8: endpoint {
remote-endpoint = <&xbar_mix_in8>;
};
};
port@8 {
reg = <0x8>;
mix_in9: endpoint {
remote-endpoint = <&xbar_mix_in9>;
};
};
port@9 {
reg = <0x9>;
mix_in10: endpoint {
remote-endpoint = <&xbar_mix_in10>;
};
};
mix_out1_port: port@a {
reg = <0xa>;
mix_out1: endpoint {
remote-endpoint = <&xbar_mix_out1>;
};
};
mix_out2_port: port@b {
reg = <0xb>;
mix_out2: endpoint {
remote-endpoint = <&xbar_mix_out2>;
};
};
mix_out3_port: port@c {
reg = <0xc>;
mix_out3: endpoint {
remote-endpoint = <&xbar_mix_out3>;
};
};
mix_out4_port: port@d {
reg = <0xd>;
mix_out4: endpoint {
remote-endpoint = <&xbar_mix_out4>;
};
};
mix_out5_port: port@e {
reg = <0xe>;
mix_out5: endpoint {
remote-endpoint = <&xbar_mix_out5>;
};
};
};
};
admaif@290f000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
admaif0_port: port@0 {
reg = <0x0>;
admaif0: endpoint {
remote-endpoint = <&xbar_admaif0>;
};
};
admaif1_port: port@1 {
reg = <0x1>;
admaif1: endpoint {
remote-endpoint = <&xbar_admaif1>;
};
};
admaif2_port: port@2 {
reg = <0x2>;
admaif2: endpoint {
remote-endpoint = <&xbar_admaif2>;
};
};
admaif3_port: port@3 {
reg = <0x3>;
admaif3: endpoint {
remote-endpoint = <&xbar_admaif3>;
};
};
admaif4_port: port@4 {
reg = <0x4>;
admaif4: endpoint {
remote-endpoint = <&xbar_admaif4>;
};
};
admaif5_port: port@5 {
reg = <0x5>;
admaif5: endpoint {
remote-endpoint = <&xbar_admaif5>;
};
};
admaif6_port: port@6 {
reg = <0x6>;
admaif6: endpoint {
remote-endpoint = <&xbar_admaif6>;
};
};
admaif7_port: port@7 {
reg = <0x7>;
admaif7: endpoint {
remote-endpoint = <&xbar_admaif7>;
};
};
admaif8_port: port@8 {
reg = <0x8>;
admaif8: endpoint {
remote-endpoint = <&xbar_admaif8>;
};
};
admaif9_port: port@9 {
reg = <0x9>;
admaif9: endpoint {
remote-endpoint = <&xbar_admaif9>;
};
};
admaif10_port: port@a {
reg = <0xa>;
admaif10: endpoint {
remote-endpoint = <&xbar_admaif10>;
};
};
admaif11_port: port@b {
reg = <0xb>;
admaif11: endpoint {
remote-endpoint = <&xbar_admaif11>;
};
};
admaif12_port: port@c {
reg = <0xc>;
admaif12: endpoint {
remote-endpoint = <&xbar_admaif12>;
};
};
admaif13_port: port@d {
reg = <0xd>;
admaif13: endpoint {
remote-endpoint = <&xbar_admaif13>;
};
};
admaif14_port: port@e {
reg = <0xe>;
admaif14: endpoint {
remote-endpoint = <&xbar_admaif14>;
};
};
admaif15_port: port@f {
reg = <0xf>;
admaif15: endpoint {
remote-endpoint = <&xbar_admaif15>;
};
};
admaif16_port: port@10 {
reg = <0x10>;
admaif16: endpoint {
remote-endpoint = <&xbar_admaif16>;
};
};
admaif17_port: port@11 {
reg = <0x11>;
admaif17: endpoint {
remote-endpoint = <&xbar_admaif17>;
};
};
admaif18_port: port@12 {
reg = <0x12>;
admaif18: endpoint {
remote-endpoint = <&xbar_admaif18>;
};
};
admaif19_port: port@13 {
reg = <0x13>;
admaif19: endpoint {
remote-endpoint = <&xbar_admaif19>;
};
};
};
};
asrc@2910000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
asrc_in1_ep: endpoint {
remote-endpoint = <&xbar_asrc_in1_ep>;
};
};
port@1 {
reg = <0x1>;
asrc_in2_ep: endpoint {
remote-endpoint = <&xbar_asrc_in2_ep>;
};
};
port@2 {
reg = <0x2>;
asrc_in3_ep: endpoint {
remote-endpoint = <&xbar_asrc_in3_ep>;
};
};
port@3 {
reg = <0x3>;
asrc_in4_ep: endpoint {
remote-endpoint = <&xbar_asrc_in4_ep>;
};
};
port@4 {
reg = <0x4>;
asrc_in5_ep: endpoint {
remote-endpoint = <&xbar_asrc_in5_ep>;
};
};
port@5 {
reg = <0x5>;
asrc_in6_ep: endpoint {
remote-endpoint = <&xbar_asrc_in6_ep>;
};
};
port@6 {
reg = <0x6>;
asrc_in7_ep: endpoint {
remote-endpoint = <&xbar_asrc_in7_ep>;
};
};
asrc_out1_port: port@7 {
reg = <0x7>;
asrc_out1_ep: endpoint {
remote-endpoint = <&xbar_asrc_out1_ep>;
};
};
asrc_out2_port: port@8 {
reg = <0x8>;
asrc_out2_ep: endpoint {
remote-endpoint = <&xbar_asrc_out2_ep>;
};
};
asrc_out3_port: port@9 {
reg = <0x9>;
asrc_out3_ep: endpoint {
remote-endpoint = <&xbar_asrc_out3_ep>;
};
};
asrc_out4_port: port@a {
reg = <0xa>;
asrc_out4_ep: endpoint {
remote-endpoint = <&xbar_asrc_out4_ep>;
};
};
asrc_out5_port: port@b {
reg = <0xb>;
asrc_out5_ep: endpoint {
remote-endpoint = <&xbar_asrc_out5_ep>;
};
};
asrc_out6_port: port@c {
reg = <0xc>;
asrc_out6_ep: endpoint {
remote-endpoint = <&xbar_asrc_out6_ep>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
xbar_admaif0: endpoint {
remote-endpoint = <&admaif0>;
};
};
port@1 {
reg = <0x1>;
xbar_admaif1: endpoint {
remote-endpoint = <&admaif1>;
};
};
port@2 {
reg = <0x2>;
xbar_admaif2: endpoint {
remote-endpoint = <&admaif2>;
};
};
port@3 {
reg = <0x3>;
xbar_admaif3: endpoint {
remote-endpoint = <&admaif3>;
};
};
port@4 {
reg = <0x4>;
xbar_admaif4: endpoint {
remote-endpoint = <&admaif4>;
};
};
port@5 {
reg = <0x5>;
xbar_admaif5: endpoint {
remote-endpoint = <&admaif5>;
};
};
port@6 {
reg = <0x6>;
xbar_admaif6: endpoint {
remote-endpoint = <&admaif6>;
};
};
port@7 {
reg = <0x7>;
xbar_admaif7: endpoint {
remote-endpoint = <&admaif7>;
};
};
port@8 {
reg = <0x8>;
xbar_admaif8: endpoint {
remote-endpoint = <&admaif8>;
};
};
port@9 {
reg = <0x9>;
xbar_admaif9: endpoint {
remote-endpoint = <&admaif9>;
};
};
port@a {
reg = <0xa>;
xbar_admaif10: endpoint {
remote-endpoint = <&admaif10>;
};
};
port@b {
reg = <0xb>;
xbar_admaif11: endpoint {
remote-endpoint = <&admaif11>;
};
};
port@c {
reg = <0xc>;
xbar_admaif12: endpoint {
remote-endpoint = <&admaif12>;
};
};
port@d {
reg = <0xd>;
xbar_admaif13: endpoint {
remote-endpoint = <&admaif13>;
};
};
port@e {
reg = <0xe>;
xbar_admaif14: endpoint {
remote-endpoint = <&admaif14>;
};
};
port@f {
reg = <0xf>;
xbar_admaif15: endpoint {
remote-endpoint = <&admaif15>;
};
};
port@10 {
reg = <0x10>;
xbar_admaif16: endpoint {
remote-endpoint = <&admaif16>;
};
};
port@11 {
reg = <0x11>;
xbar_admaif17: endpoint {
remote-endpoint = <&admaif17>;
};
};
port@12 {
reg = <0x12>;
xbar_admaif18: endpoint {
remote-endpoint = <&admaif18>;
};
};
port@13 {
reg = <0x13>;
xbar_admaif19: endpoint {
remote-endpoint = <&admaif19>;
};
};
xbar_i2s1_port: port@14 {
reg = <0x14>;
xbar_i2s1: endpoint {
remote-endpoint = <&i2s1_cif>;
};
};
xbar_i2s2_port: port@15 {
reg = <0x15>;
xbar_i2s2: endpoint {
remote-endpoint = <&i2s2_cif>;
};
};
xbar_i2s4_port: port@17 {
reg = <0x17>;
xbar_i2s4: endpoint {
remote-endpoint = <&i2s4_cif>;
};
};
xbar_i2s6_port: port@19 {
reg = <0x19>;
xbar_i2s6: endpoint {
remote-endpoint = <&i2s6_cif>;
};
};
xbar_dmic3_port: port@1c {
reg = <0x1c>;
xbar_dmic3: endpoint {
remote-endpoint = <&dmic3_cif>;
};
};
xbar_sfc1_in_port: port@20 {
reg = <0x20>;
xbar_sfc1_in: endpoint {
remote-endpoint = <&sfc1_cif_in>;
};
};
port@21 {
reg = <0x21>;
xbar_sfc1_out: endpoint {
remote-endpoint = <&sfc1_cif_out>;
};
};
xbar_sfc2_in_port: port@22 {
reg = <0x22>;
xbar_sfc2_in: endpoint {
remote-endpoint = <&sfc2_cif_in>;
};
};
port@23 {
reg = <0x23>;
xbar_sfc2_out: endpoint {
remote-endpoint = <&sfc2_cif_out>;
};
};
xbar_sfc3_in_port: port@24 {
reg = <0x24>;
xbar_sfc3_in: endpoint {
remote-endpoint = <&sfc3_cif_in>;
};
};
port@25 {
reg = <0x25>;
xbar_sfc3_out: endpoint {
remote-endpoint = <&sfc3_cif_out>;
};
};
xbar_sfc4_in_port: port@26 {
reg = <0x26>;
xbar_sfc4_in: endpoint {
remote-endpoint = <&sfc4_cif_in>;
};
};
port@27 {
reg = <0x27>;
xbar_sfc4_out: endpoint {
remote-endpoint = <&sfc4_cif_out>;
};
};
xbar_mvc1_in_port: port@28 {
reg = <0x28>;
xbar_mvc1_in: endpoint {
remote-endpoint = <&mvc1_cif_in>;
};
};
port@29 {
reg = <0x29>;
xbar_mvc1_out: endpoint {
remote-endpoint = <&mvc1_cif_out>;
};
};
xbar_mvc2_in_port: port@2a {
reg = <0x2a>;
xbar_mvc2_in: endpoint {
remote-endpoint = <&mvc2_cif_in>;
};
};
port@2b {
reg = <0x2b>;
xbar_mvc2_out: endpoint {
remote-endpoint = <&mvc2_cif_out>;
};
};
xbar_amx1_in1_port: port@2c {
reg = <0x2c>;
xbar_amx1_in1: endpoint {
remote-endpoint = <&amx1_in1>;
};
};
xbar_amx1_in2_port: port@2d {
reg = <0x2d>;
xbar_amx1_in2: endpoint {
remote-endpoint = <&amx1_in2>;
};
};
xbar_amx1_in3_port: port@2e {
reg = <0x2e>;
xbar_amx1_in3: endpoint {
remote-endpoint = <&amx1_in3>;
};
};
xbar_amx1_in4_port: port@2f {
reg = <0x2f>;
xbar_amx1_in4: endpoint {
remote-endpoint = <&amx1_in4>;
};
};
port@30 {
reg = <0x30>;
xbar_amx1_out: endpoint {
remote-endpoint = <&amx1_out>;
};
};
xbar_amx2_in1_port: port@31 {
reg = <0x31>;
xbar_amx2_in1: endpoint {
remote-endpoint = <&amx2_in1>;
};
};
xbar_amx2_in2_port: port@32 {
reg = <0x32>;
xbar_amx2_in2: endpoint {
remote-endpoint = <&amx2_in2>;
};
};
xbar_amx2_in3_port: port@33 {
reg = <0x33>;
xbar_amx2_in3: endpoint {
remote-endpoint = <&amx2_in3>;
};
};
xbar_amx2_in4_port: port@34 {
reg = <0x34>;
xbar_amx2_in4: endpoint {
remote-endpoint = <&amx2_in4>;
};
};
port@35 {
reg = <0x35>;
xbar_amx2_out: endpoint {
remote-endpoint = <&amx2_out>;
};
};
xbar_amx3_in1_port: port@36 {
reg = <0x36>;
xbar_amx3_in1: endpoint {
remote-endpoint = <&amx3_in1>;
};
};
xbar_amx3_in2_port: port@37 {
reg = <0x37>;
xbar_amx3_in2: endpoint {
remote-endpoint = <&amx3_in2>;
};
};
xbar_amx3_in3_port: port@38 {
reg = <0x38>;
xbar_amx3_in3: endpoint {
remote-endpoint = <&amx3_in3>;
};
};
xbar_amx3_in4_port: port@39 {
reg = <0x39>;
xbar_amx3_in4: endpoint {
remote-endpoint = <&amx3_in4>;
};
};
port@3a {
reg = <0x3a>;
xbar_amx3_out: endpoint {
remote-endpoint = <&amx3_out>;
};
};
xbar_amx4_in1_port: port@3b {
reg = <0x3b>;
xbar_amx4_in1: endpoint {
remote-endpoint = <&amx4_in1>;
};
};
xbar_amx4_in2_port: port@3c {
reg = <0x3c>;
xbar_amx4_in2: endpoint {
remote-endpoint = <&amx4_in2>;
};
};
xbar_amx4_in3_port: port@3d {
reg = <0x3d>;
xbar_amx4_in3: endpoint {
remote-endpoint = <&amx4_in3>;
};
};
xbar_amx4_in4_port: port@3e {
reg = <0x3e>;
xbar_amx4_in4: endpoint {
remote-endpoint = <&amx4_in4>;
};
};
port@3f {
reg = <0x3f>;
xbar_amx4_out: endpoint {
remote-endpoint = <&amx4_out>;
};
};
xbar_adx1_in_port: port@40 {
reg = <0x40>;
xbar_adx1_in: endpoint {
remote-endpoint = <&adx1_in>;
};
};
port@41 {
reg = <0x41>;
xbar_adx1_out1: endpoint {
remote-endpoint = <&adx1_out1>;
};
};
port@42 {
reg = <0x42>;
xbar_adx1_out2: endpoint {
remote-endpoint = <&adx1_out2>;
};
};
port@43 {
reg = <0x43>;
xbar_adx1_out3: endpoint {
remote-endpoint = <&adx1_out3>;
};
};
port@44 {
reg = <0x44>;
xbar_adx1_out4: endpoint {
remote-endpoint = <&adx1_out4>;
};
};
xbar_adx2_in_port: port@45 {
reg = <0x45>;
xbar_adx2_in: endpoint {
remote-endpoint = <&adx2_in>;
};
};
port@46 {
reg = <0x46>;
xbar_adx2_out1: endpoint {
remote-endpoint = <&adx2_out1>;
};
};
port@47 {
reg = <0x47>;
xbar_adx2_out2: endpoint {
remote-endpoint = <&adx2_out2>;
};
};
port@48 {
reg = <0x48>;
xbar_adx2_out3: endpoint {
remote-endpoint = <&adx2_out3>;
};
};
port@49 {
reg = <0x49>;
xbar_adx2_out4: endpoint {
remote-endpoint = <&adx2_out4>;
};
};
xbar_adx3_in_port: port@4a {
reg = <0x4a>;
xbar_adx3_in: endpoint {
remote-endpoint = <&adx3_in>;
};
};
port@4b {
reg = <0x4b>;
xbar_adx3_out1: endpoint {
remote-endpoint = <&adx3_out1>;
};
};
port@4c {
reg = <0x4c>;
xbar_adx3_out2: endpoint {
remote-endpoint = <&adx3_out2>;
};
};
port@4d {
reg = <0x4d>;
xbar_adx3_out3: endpoint {
remote-endpoint = <&adx3_out3>;
};
};
port@4e {
reg = <0x4e>;
xbar_adx3_out4: endpoint {
remote-endpoint = <&adx3_out4>;
};
};
xbar_adx4_in_port: port@4f {
reg = <0x4f>;
xbar_adx4_in: endpoint {
remote-endpoint = <&adx4_in>;
};
};
port@50 {
reg = <0x50>;
xbar_adx4_out1: endpoint {
remote-endpoint = <&adx4_out1>;
};
};
port@51 {
reg = <0x51>;
xbar_adx4_out2: endpoint {
remote-endpoint = <&adx4_out2>;
};
};
port@52 {
reg = <0x52>;
xbar_adx4_out3: endpoint {
remote-endpoint = <&adx4_out3>;
};
};
port@53 {
reg = <0x53>;
xbar_adx4_out4: endpoint {
remote-endpoint = <&adx4_out4>;
};
};
xbar_mix_in1_port: port@54 {
reg = <0x54>;
xbar_mix_in1: endpoint {
remote-endpoint = <&mix_in1>;
};
};
xbar_mix_in2_port: port@55 {
reg = <0x55>;
xbar_mix_in2: endpoint {
remote-endpoint = <&mix_in2>;
};
};
xbar_mix_in3_port: port@56 {
reg = <0x56>;
xbar_mix_in3: endpoint {
remote-endpoint = <&mix_in3>;
};
};
xbar_mix_in4_port: port@57 {
reg = <0x57>;
xbar_mix_in4: endpoint {
remote-endpoint = <&mix_in4>;
};
};
xbar_mix_in5_port: port@58 {
reg = <0x58>;
xbar_mix_in5: endpoint {
remote-endpoint = <&mix_in5>;
};
};
xbar_mix_in6_port: port@59 {
reg = <0x59>;
xbar_mix_in6: endpoint {
remote-endpoint = <&mix_in6>;
};
};
xbar_mix_in7_port: port@5a {
reg = <0x5a>;
xbar_mix_in7: endpoint {
remote-endpoint = <&mix_in7>;
};
};
xbar_mix_in8_port: port@5b {
reg = <0x5b>;
xbar_mix_in8: endpoint {
remote-endpoint = <&mix_in8>;
};
};
xbar_mix_in9_port: port@5c {
reg = <0x5c>;
xbar_mix_in9: endpoint {
remote-endpoint = <&mix_in9>;
};
};
xbar_mix_in10_port: port@5d {
reg = <0x5d>;
xbar_mix_in10: endpoint {
remote-endpoint = <&mix_in10>;
};
};
port@5e {
reg = <0x5e>;
xbar_mix_out1: endpoint {
remote-endpoint = <&mix_out1>;
};
};
port@5f {
reg = <0x5f>;
xbar_mix_out2: endpoint {
remote-endpoint = <&mix_out2>;
};
};
port@60 {
reg = <0x60>;
xbar_mix_out3: endpoint {
remote-endpoint = <&mix_out3>;
};
};
port@61 {
reg = <0x61>;
xbar_mix_out4: endpoint {
remote-endpoint = <&mix_out4>;
};
};
port@62 {
reg = <0x62>;
xbar_mix_out5: endpoint {
remote-endpoint = <&mix_out5>;
};
};
xbar_asrc_in1_port: port@63 {
reg = <0x63>;
xbar_asrc_in1_ep: endpoint {
remote-endpoint = <&asrc_in1_ep>;
};
};
port@64 {
reg = <0x64>;
xbar_asrc_out1_ep: endpoint {
remote-endpoint = <&asrc_out1_ep>;
};
};
xbar_asrc_in2_port: port@65 {
reg = <0x65>;
xbar_asrc_in2_ep: endpoint {
remote-endpoint = <&asrc_in2_ep>;
};
};
port@66 {
reg = <0x66>;
xbar_asrc_out2_ep: endpoint {
remote-endpoint = <&asrc_out2_ep>;
};
};
xbar_asrc_in3_port: port@67 {
reg = <0x67>;
xbar_asrc_in3_ep: endpoint {
remote-endpoint = <&asrc_in3_ep>;
};
};
port@68 {
reg = <0x68>;
xbar_asrc_out3_ep: endpoint {
remote-endpoint = <&asrc_out3_ep>;
};
};
xbar_asrc_in4_port: port@69 {
reg = <0x69>;
xbar_asrc_in4_ep: endpoint {
remote-endpoint = <&asrc_in4_ep>;
};
};
port@6a {
reg = <0x6a>;
xbar_asrc_out4_ep: endpoint {
remote-endpoint = <&asrc_out4_ep>;
};
};
xbar_asrc_in5_port: port@6b {
reg = <0x6b>;
xbar_asrc_in5_ep: endpoint {
remote-endpoint = <&asrc_in5_ep>;
};
};
port@6c {
reg = <0x6c>;
xbar_asrc_out5_ep: endpoint {
remote-endpoint = <&asrc_out5_ep>;
};
};
xbar_asrc_in6_port: port@6d {
reg = <0x6d>;
xbar_asrc_in6_ep: endpoint {
remote-endpoint = <&asrc_in6_ep>;
};
};
port@6e {
reg = <0x6e>;
xbar_asrc_out6_ep: endpoint {
remote-endpoint = <&asrc_out6_ep>;
};
};
xbar_asrc_in7_port: port@6f {
reg = <0x6f>;
xbar_asrc_in7_ep: endpoint {
remote-endpoint = <&asrc_in7_ep>;
};
};
xbar_ope1_in_port: port@70 {
reg = <0x70>;
xbar_ope1_in_ep: endpoint {
remote-endpoint = <&ope1_cif_in_ep>;
};
};
port@71 {
reg = <0x71>;
xbar_ope1_out_ep: endpoint {
remote-endpoint = <&ope1_cif_out_ep>;
};
};
};
};
dma-controller@2930000 {
status = "okay";
};
interrupt-controller@2a40000 {
status = "okay";
};
};
};
};
......@@ -3,7 +3,6 @@
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/sound/rt5640.h>
#include "tegra234-p3701-0000.dtsi"
#include "tegra234-p3737-0000.dtsi"
......@@ -24,2022 +23,14 @@ chosen {
};
bus@0 {
aconnect@2900000 {
status = "okay";
ahub@2900800 {
status = "okay";
i2s@2901000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
i2s1_cif: endpoint {
remote-endpoint = <&xbar_i2s1>;
};
};
i2s1_port: port@1 {
reg = <1>;
i2s1_dap: endpoint {
dai-format = "i2s";
remote-endpoint = <&rt5640_ep>;
};
};
};
};
i2s@2901100 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
i2s2_cif: endpoint {
remote-endpoint = <&xbar_i2s2>;
};
};
i2s2_port: port@1 {
reg = <1>;
i2s2_dap: endpoint {
dai-format = "i2s";
/* placeholder for external codec */
};
};
};
};
i2s@2901300 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
i2s4_cif: endpoint {
remote-endpoint = <&xbar_i2s4>;
};
};
i2s4_port: port@1 {
reg = <1>;
i2s4_dap: endpoint {
dai-format = "i2s";
/* placeholder for external codec */
};
};
};
};
i2s@2901500 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
i2s6_cif: endpoint {
remote-endpoint = <&xbar_i2s6>;
};
};
i2s6_port: port@1 {
reg = <1>;
i2s6_dap: endpoint {
dai-format = "i2s";
/* placeholder for external codec */
};
};
};
};
sfc@2902000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sfc1_cif_in: endpoint {
remote-endpoint = <&xbar_sfc1_in>;
};
};
sfc1_out_port: port@1 {
reg = <1>;
sfc1_cif_out: endpoint {
remote-endpoint = <&xbar_sfc1_out>;
};
};
};
};
sfc@2902200 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sfc2_cif_in: endpoint {
remote-endpoint = <&xbar_sfc2_in>;
};
};
sfc2_out_port: port@1 {
reg = <1>;
sfc2_cif_out: endpoint {
remote-endpoint = <&xbar_sfc2_out>;
};
};
};
};
sfc@2902400 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sfc3_cif_in: endpoint {
remote-endpoint = <&xbar_sfc3_in>;
};
};
sfc3_out_port: port@1 {
reg = <1>;
sfc3_cif_out: endpoint {
remote-endpoint = <&xbar_sfc3_out>;
};
};
};
};
sfc@2902600 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sfc4_cif_in: endpoint {
remote-endpoint = <&xbar_sfc4_in>;
};
};
sfc4_out_port: port@1 {
reg = <1>;
sfc4_cif_out: endpoint {
remote-endpoint = <&xbar_sfc4_out>;
};
};
};
};
amx@2903000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
amx1_in1: endpoint {
remote-endpoint = <&xbar_amx1_in1>;
};
};
port@1 {
reg = <1>;
amx1_in2: endpoint {
remote-endpoint = <&xbar_amx1_in2>;
};
};
port@2 {
reg = <2>;
amx1_in3: endpoint {
remote-endpoint = <&xbar_amx1_in3>;
};
};
port@3 {
reg = <3>;
amx1_in4: endpoint {
remote-endpoint = <&xbar_amx1_in4>;
};
};
amx1_out_port: port@4 {
reg = <4>;
amx1_out: endpoint {
remote-endpoint = <&xbar_amx1_out>;
};
};
};
};
amx@2903100 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
amx2_in1: endpoint {
remote-endpoint = <&xbar_amx2_in1>;
};
};
port@1 {
reg = <1>;
amx2_in2: endpoint {
remote-endpoint = <&xbar_amx2_in2>;
};
};
port@2 {
reg = <2>;
amx2_in3: endpoint {
remote-endpoint = <&xbar_amx2_in3>;
};
};
port@3 {
reg = <3>;
amx2_in4: endpoint {
remote-endpoint = <&xbar_amx2_in4>;
};
};
amx2_out_port: port@4 {
reg = <4>;
amx2_out: endpoint {
remote-endpoint = <&xbar_amx2_out>;
};
};
};
};
amx@2903200 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
amx3_in1: endpoint {
remote-endpoint = <&xbar_amx3_in1>;
};
};
port@1 {
reg = <1>;
amx3_in2: endpoint {
remote-endpoint = <&xbar_amx3_in2>;
};
};
port@2 {
reg = <2>;
amx3_in3: endpoint {
remote-endpoint = <&xbar_amx3_in3>;
};
};
port@3 {
reg = <3>;
amx3_in4: endpoint {
remote-endpoint = <&xbar_amx3_in4>;
};
};
amx3_out_port: port@4 {
reg = <4>;
amx3_out: endpoint {
remote-endpoint = <&xbar_amx3_out>;
};
};
};
};
amx@2903300 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
amx4_in1: endpoint {
remote-endpoint = <&xbar_amx4_in1>;
};
};
port@1 {
reg = <1>;
amx4_in2: endpoint {
remote-endpoint = <&xbar_amx4_in2>;
};
};
port@2 {
reg = <2>;
amx4_in3: endpoint {
remote-endpoint = <&xbar_amx4_in3>;
};
};
port@3 {
reg = <3>;
amx4_in4: endpoint {
remote-endpoint = <&xbar_amx4_in4>;
};
};
amx4_out_port: port@4 {
reg = <4>;
amx4_out: endpoint {
remote-endpoint = <&xbar_amx4_out>;
};
};
};
};
adx@2903800 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adx1_in: endpoint {
remote-endpoint = <&xbar_adx1_in>;
};
};
adx1_out1_port: port@1 {
reg = <1>;
adx1_out1: endpoint {
remote-endpoint = <&xbar_adx1_out1>;
};
};
adx1_out2_port: port@2 {
reg = <2>;
adx1_out2: endpoint {
remote-endpoint = <&xbar_adx1_out2>;
};
};
adx1_out3_port: port@3 {
reg = <3>;
adx1_out3: endpoint {
remote-endpoint = <&xbar_adx1_out3>;
};
};
adx1_out4_port: port@4 {
reg = <4>;
adx1_out4: endpoint {
remote-endpoint = <&xbar_adx1_out4>;
};
};
};
};
adx@2903900 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adx2_in: endpoint {
remote-endpoint = <&xbar_adx2_in>;
};
};
adx2_out1_port: port@1 {
reg = <1>;
adx2_out1: endpoint {
remote-endpoint = <&xbar_adx2_out1>;
};
};
adx2_out2_port: port@2 {
reg = <2>;
adx2_out2: endpoint {
remote-endpoint = <&xbar_adx2_out2>;
};
};
adx2_out3_port: port@3 {
reg = <3>;
adx2_out3: endpoint {
remote-endpoint = <&xbar_adx2_out3>;
};
};
adx2_out4_port: port@4 {
reg = <4>;
adx2_out4: endpoint {
remote-endpoint = <&xbar_adx2_out4>;
};
};
};
};
adx@2903a00 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adx3_in: endpoint {
remote-endpoint = <&xbar_adx3_in>;
};
};
adx3_out1_port: port@1 {
reg = <1>;
adx3_out1: endpoint {
remote-endpoint = <&xbar_adx3_out1>;
};
};
adx3_out2_port: port@2 {
reg = <2>;
adx3_out2: endpoint {
remote-endpoint = <&xbar_adx3_out2>;
};
};
adx3_out3_port: port@3 {
reg = <3>;
adx3_out3: endpoint {
remote-endpoint = <&xbar_adx3_out3>;
};
};
adx3_out4_port: port@4 {
reg = <4>;
adx3_out4: endpoint {
remote-endpoint = <&xbar_adx3_out4>;
};
};
};
};
adx@2903b00 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adx4_in: endpoint {
remote-endpoint = <&xbar_adx4_in>;
};
};
adx4_out1_port: port@1 {
reg = <1>;
adx4_out1: endpoint {
remote-endpoint = <&xbar_adx4_out1>;
};
};
adx4_out2_port: port@2 {
reg = <2>;
adx4_out2: endpoint {
remote-endpoint = <&xbar_adx4_out2>;
};
};
adx4_out3_port: port@3 {
reg = <3>;
adx4_out3: endpoint {
remote-endpoint = <&xbar_adx4_out3>;
};
};
adx4_out4_port: port@4 {
reg = <4>;
adx4_out4: endpoint {
remote-endpoint = <&xbar_adx4_out4>;
};
};
};
};
dmic@2904200 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dmic3_cif: endpoint {
remote-endpoint = <&xbar_dmic3>;
};
};
dmic3_port: port@1 {
reg = <1>;
dmic3_dap: endpoint {
/* placeholder for external codec */
};
};
};
};
processing-engine@2908000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
ope1_cif_in_ep: endpoint {
remote-endpoint = <&xbar_ope1_in_ep>;
};
};
ope1_out_port: port@1 {
reg = <0x1>;
ope1_cif_out_ep: endpoint {
remote-endpoint = <&xbar_ope1_out_ep>;
};
};
};
};
mvc@290a000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mvc1_cif_in: endpoint {
remote-endpoint = <&xbar_mvc1_in>;
};
};
mvc1_out_port: port@1 {
reg = <1>;
mvc1_cif_out: endpoint {
remote-endpoint = <&xbar_mvc1_out>;
};
};
};
};
mvc@290a200 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mvc2_cif_in: endpoint {
remote-endpoint = <&xbar_mvc2_in>;
};
};
mvc2_out_port: port@1 {
reg = <1>;
mvc2_cif_out: endpoint {
remote-endpoint = <&xbar_mvc2_out>;
};
};
};
};
amixer@290bb00 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
mix_in1: endpoint {
remote-endpoint = <&xbar_mix_in1>;
};
};
port@1 {
reg = <0x1>;
mix_in2: endpoint {
remote-endpoint = <&xbar_mix_in2>;
};
};
port@2 {
reg = <0x2>;
mix_in3: endpoint {
remote-endpoint = <&xbar_mix_in3>;
};
};
port@3 {
reg = <0x3>;
mix_in4: endpoint {
remote-endpoint = <&xbar_mix_in4>;
};
};
port@4 {
reg = <0x4>;
mix_in5: endpoint {
remote-endpoint = <&xbar_mix_in5>;
};
};
port@5 {
reg = <0x5>;
mix_in6: endpoint {
remote-endpoint = <&xbar_mix_in6>;
};
};
port@6 {
reg = <0x6>;
mix_in7: endpoint {
remote-endpoint = <&xbar_mix_in7>;
};
};
port@7 {
reg = <0x7>;
mix_in8: endpoint {
remote-endpoint = <&xbar_mix_in8>;
};
};
port@8 {
reg = <0x8>;
mix_in9: endpoint {
remote-endpoint = <&xbar_mix_in9>;
};
};
port@9 {
reg = <0x9>;
mix_in10: endpoint {
remote-endpoint = <&xbar_mix_in10>;
};
};
mix_out1_port: port@a {
reg = <0xa>;
mix_out1: endpoint {
remote-endpoint = <&xbar_mix_out1>;
};
};
mix_out2_port: port@b {
reg = <0xb>;
mix_out2: endpoint {
remote-endpoint = <&xbar_mix_out2>;
};
};
mix_out3_port: port@c {
reg = <0xc>;
mix_out3: endpoint {
remote-endpoint = <&xbar_mix_out3>;
};
};
mix_out4_port: port@d {
reg = <0xd>;
mix_out4: endpoint {
remote-endpoint = <&xbar_mix_out4>;
};
};
mix_out5_port: port@e {
reg = <0xe>;
mix_out5: endpoint {
remote-endpoint = <&xbar_mix_out5>;
};
};
};
};
admaif@290f000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
admaif0_port: port@0 {
reg = <0x0>;
admaif0: endpoint {
remote-endpoint = <&xbar_admaif0>;
};
};
admaif1_port: port@1 {
reg = <0x1>;
admaif1: endpoint {
remote-endpoint = <&xbar_admaif1>;
};
};
admaif2_port: port@2 {
reg = <0x2>;
admaif2: endpoint {
remote-endpoint = <&xbar_admaif2>;
};
};
admaif3_port: port@3 {
reg = <0x3>;
admaif3: endpoint {
remote-endpoint = <&xbar_admaif3>;
};
};
admaif4_port: port@4 {
reg = <0x4>;
admaif4: endpoint {
remote-endpoint = <&xbar_admaif4>;
};
};
admaif5_port: port@5 {
reg = <0x5>;
admaif5: endpoint {
remote-endpoint = <&xbar_admaif5>;
};
};
admaif6_port: port@6 {
reg = <0x6>;
admaif6: endpoint {
remote-endpoint = <&xbar_admaif6>;
};
};
admaif7_port: port@7 {
reg = <0x7>;
admaif7: endpoint {
remote-endpoint = <&xbar_admaif7>;
};
};
admaif8_port: port@8 {
reg = <0x8>;
admaif8: endpoint {
remote-endpoint = <&xbar_admaif8>;
};
};
admaif9_port: port@9 {
reg = <0x9>;
admaif9: endpoint {
remote-endpoint = <&xbar_admaif9>;
};
};
admaif10_port: port@a {
reg = <0xa>;
admaif10: endpoint {
remote-endpoint = <&xbar_admaif10>;
};
};
admaif11_port: port@b {
reg = <0xb>;
admaif11: endpoint {
remote-endpoint = <&xbar_admaif11>;
};
};
admaif12_port: port@c {
reg = <0xc>;
admaif12: endpoint {
remote-endpoint = <&xbar_admaif12>;
};
};
admaif13_port: port@d {
reg = <0xd>;
admaif13: endpoint {
remote-endpoint = <&xbar_admaif13>;
};
};
admaif14_port: port@e {
reg = <0xe>;
admaif14: endpoint {
remote-endpoint = <&xbar_admaif14>;
};
};
admaif15_port: port@f {
reg = <0xf>;
admaif15: endpoint {
remote-endpoint = <&xbar_admaif15>;
};
};
admaif16_port: port@10 {
reg = <0x10>;
admaif16: endpoint {
remote-endpoint = <&xbar_admaif16>;
};
};
admaif17_port: port@11 {
reg = <0x11>;
admaif17: endpoint {
remote-endpoint = <&xbar_admaif17>;
};
};
admaif18_port: port@12 {
reg = <0x12>;
admaif18: endpoint {
remote-endpoint = <&xbar_admaif18>;
};
};
admaif19_port: port@13 {
reg = <0x13>;
admaif19: endpoint {
remote-endpoint = <&xbar_admaif19>;
};
};
};
};
asrc@2910000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
asrc_in1_ep: endpoint {
remote-endpoint = <&xbar_asrc_in1_ep>;
};
};
port@1 {
reg = <0x1>;
asrc_in2_ep: endpoint {
remote-endpoint = <&xbar_asrc_in2_ep>;
};
};
port@2 {
reg = <0x2>;
asrc_in3_ep: endpoint {
remote-endpoint = <&xbar_asrc_in3_ep>;
};
};
port@3 {
reg = <0x3>;
asrc_in4_ep: endpoint {
remote-endpoint = <&xbar_asrc_in4_ep>;
};
};
port@4 {
reg = <0x4>;
asrc_in5_ep: endpoint {
remote-endpoint = <&xbar_asrc_in5_ep>;
};
};
port@5 {
reg = <0x5>;
asrc_in6_ep: endpoint {
remote-endpoint = <&xbar_asrc_in6_ep>;
};
};
port@6 {
reg = <0x6>;
asrc_in7_ep: endpoint {
remote-endpoint = <&xbar_asrc_in7_ep>;
};
};
asrc_out1_port: port@7 {
reg = <0x7>;
asrc_out1_ep: endpoint {
remote-endpoint = <&xbar_asrc_out1_ep>;
};
};
asrc_out2_port: port@8 {
reg = <0x8>;
asrc_out2_ep: endpoint {
remote-endpoint = <&xbar_asrc_out2_ep>;
};
};
asrc_out3_port: port@9 {
reg = <0x9>;
asrc_out3_ep: endpoint {
remote-endpoint = <&xbar_asrc_out3_ep>;
};
};
asrc_out4_port: port@a {
reg = <0xa>;
asrc_out4_ep: endpoint {
remote-endpoint = <&xbar_asrc_out4_ep>;
};
};
asrc_out5_port: port@b {
reg = <0xb>;
asrc_out5_ep: endpoint {
remote-endpoint = <&xbar_asrc_out5_ep>;
};
};
asrc_out6_port: port@c {
reg = <0xc>;
asrc_out6_ep: endpoint {
remote-endpoint = <&xbar_asrc_out6_ep>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
xbar_admaif0: endpoint {
remote-endpoint = <&admaif0>;
};
};
port@1 {
reg = <0x1>;
xbar_admaif1: endpoint {
remote-endpoint = <&admaif1>;
};
};
port@2 {
reg = <0x2>;
xbar_admaif2: endpoint {
remote-endpoint = <&admaif2>;
};
};
port@3 {
reg = <0x3>;
xbar_admaif3: endpoint {
remote-endpoint = <&admaif3>;
};
};
port@4 {
reg = <0x4>;
xbar_admaif4: endpoint {
remote-endpoint = <&admaif4>;
};
};
port@5 {
reg = <0x5>;
xbar_admaif5: endpoint {
remote-endpoint = <&admaif5>;
};
};
port@6 {
reg = <0x6>;
xbar_admaif6: endpoint {
remote-endpoint = <&admaif6>;
};
};
port@7 {
reg = <0x7>;
xbar_admaif7: endpoint {
remote-endpoint = <&admaif7>;
};
};
port@8 {
reg = <0x8>;
xbar_admaif8: endpoint {
remote-endpoint = <&admaif8>;
};
};
port@9 {
reg = <0x9>;
xbar_admaif9: endpoint {
remote-endpoint = <&admaif9>;
};
};
port@a {
reg = <0xa>;
xbar_admaif10: endpoint {
remote-endpoint = <&admaif10>;
};
};
port@b {
reg = <0xb>;
xbar_admaif11: endpoint {
remote-endpoint = <&admaif11>;
};
};
port@c {
reg = <0xc>;
xbar_admaif12: endpoint {
remote-endpoint = <&admaif12>;
};
};
port@d {
reg = <0xd>;
xbar_admaif13: endpoint {
remote-endpoint = <&admaif13>;
};
};
port@e {
reg = <0xe>;
xbar_admaif14: endpoint {
remote-endpoint = <&admaif14>;
};
};
port@f {
reg = <0xf>;
xbar_admaif15: endpoint {
remote-endpoint = <&admaif15>;
};
};
port@10 {
reg = <0x10>;
xbar_admaif16: endpoint {
remote-endpoint = <&admaif16>;
};
};
port@11 {
reg = <0x11>;
xbar_admaif17: endpoint {
remote-endpoint = <&admaif17>;
};
};
port@12 {
reg = <0x12>;
xbar_admaif18: endpoint {
remote-endpoint = <&admaif18>;
};
};
port@13 {
reg = <0x13>;
xbar_admaif19: endpoint {
remote-endpoint = <&admaif19>;
};
};
xbar_i2s1_port: port@14 {
reg = <0x14>;
xbar_i2s1: endpoint {
remote-endpoint = <&i2s1_cif>;
};
};
xbar_i2s2_port: port@15 {
reg = <0x15>;
xbar_i2s2: endpoint {
remote-endpoint = <&i2s2_cif>;
};
};
xbar_i2s4_port: port@17 {
reg = <0x17>;
xbar_i2s4: endpoint {
remote-endpoint = <&i2s4_cif>;
};
};
xbar_i2s6_port: port@19 {
reg = <0x19>;
xbar_i2s6: endpoint {
remote-endpoint = <&i2s6_cif>;
};
};
xbar_dmic3_port: port@1c {
reg = <0x1c>;
xbar_dmic3: endpoint {
remote-endpoint = <&dmic3_cif>;
};
};
xbar_sfc1_in_port: port@20 {
reg = <0x20>;
xbar_sfc1_in: endpoint {
remote-endpoint = <&sfc1_cif_in>;
};
};
port@21 {
reg = <0x21>;
xbar_sfc1_out: endpoint {
remote-endpoint = <&sfc1_cif_out>;
};
};
xbar_sfc2_in_port: port@22 {
reg = <0x22>;
xbar_sfc2_in: endpoint {
remote-endpoint = <&sfc2_cif_in>;
};
};
port@23 {
reg = <0x23>;
xbar_sfc2_out: endpoint {
remote-endpoint = <&sfc2_cif_out>;
};
};
xbar_sfc3_in_port: port@24 {
reg = <0x24>;
xbar_sfc3_in: endpoint {
remote-endpoint = <&sfc3_cif_in>;
};
};
port@25 {
reg = <0x25>;
xbar_sfc3_out: endpoint {
remote-endpoint = <&sfc3_cif_out>;
};
};
xbar_sfc4_in_port: port@26 {
reg = <0x26>;
xbar_sfc4_in: endpoint {
remote-endpoint = <&sfc4_cif_in>;
};
};
port@27 {
reg = <0x27>;
xbar_sfc4_out: endpoint {
remote-endpoint = <&sfc4_cif_out>;
};
};
xbar_mvc1_in_port: port@28 {
reg = <0x28>;
xbar_mvc1_in: endpoint {
remote-endpoint = <&mvc1_cif_in>;
};
};
port@29 {
reg = <0x29>;
xbar_mvc1_out: endpoint {
remote-endpoint = <&mvc1_cif_out>;
};
};
xbar_mvc2_in_port: port@2a {
reg = <0x2a>;
xbar_mvc2_in: endpoint {
remote-endpoint = <&mvc2_cif_in>;
};
};
port@2b {
reg = <0x2b>;
xbar_mvc2_out: endpoint {
remote-endpoint = <&mvc2_cif_out>;
};
};
xbar_amx1_in1_port: port@2c {
reg = <0x2c>;
xbar_amx1_in1: endpoint {
remote-endpoint = <&amx1_in1>;
};
};
xbar_amx1_in2_port: port@2d {
reg = <0x2d>;
xbar_amx1_in2: endpoint {
remote-endpoint = <&amx1_in2>;
};
};
xbar_amx1_in3_port: port@2e {
reg = <0x2e>;
xbar_amx1_in3: endpoint {
remote-endpoint = <&amx1_in3>;
};
};
xbar_amx1_in4_port: port@2f {
reg = <0x2f>;
xbar_amx1_in4: endpoint {
remote-endpoint = <&amx1_in4>;
};
};
port@30 {
reg = <0x30>;
xbar_amx1_out: endpoint {
remote-endpoint = <&amx1_out>;
};
};
xbar_amx2_in1_port: port@31 {
reg = <0x31>;
xbar_amx2_in1: endpoint {
remote-endpoint = <&amx2_in1>;
};
};
xbar_amx2_in2_port: port@32 {
reg = <0x32>;
xbar_amx2_in2: endpoint {
remote-endpoint = <&amx2_in2>;
};
};
xbar_amx2_in3_port: port@33 {
reg = <0x33>;
xbar_amx2_in3: endpoint {
remote-endpoint = <&amx2_in3>;
};
};
xbar_amx2_in4_port: port@34 {
reg = <0x34>;
xbar_amx2_in4: endpoint {
remote-endpoint = <&amx2_in4>;
};
};
port@35 {
reg = <0x35>;
xbar_amx2_out: endpoint {
remote-endpoint = <&amx2_out>;
};
};
xbar_amx3_in1_port: port@36 {
reg = <0x36>;
xbar_amx3_in1: endpoint {
remote-endpoint = <&amx3_in1>;
};
};
xbar_amx3_in2_port: port@37 {
reg = <0x37>;
xbar_amx3_in2: endpoint {
remote-endpoint = <&amx3_in2>;
};
};
xbar_amx3_in3_port: port@38 {
reg = <0x38>;
xbar_amx3_in3: endpoint {
remote-endpoint = <&amx3_in3>;
};
};
xbar_amx3_in4_port: port@39 {
reg = <0x39>;
xbar_amx3_in4: endpoint {
remote-endpoint = <&amx3_in4>;
};
};
port@3a {
reg = <0x3a>;
xbar_amx3_out: endpoint {
remote-endpoint = <&amx3_out>;
};
};
xbar_amx4_in1_port: port@3b {
reg = <0x3b>;
xbar_amx4_in1: endpoint {
remote-endpoint = <&amx4_in1>;
};
};
xbar_amx4_in2_port: port@3c {
reg = <0x3c>;
xbar_amx4_in2: endpoint {
remote-endpoint = <&amx4_in2>;
};
};
xbar_amx4_in3_port: port@3d {
reg = <0x3d>;
xbar_amx4_in3: endpoint {
remote-endpoint = <&amx4_in3>;
};
};
xbar_amx4_in4_port: port@3e {
reg = <0x3e>;
xbar_amx4_in4: endpoint {
remote-endpoint = <&amx4_in4>;
};
};
port@3f {
reg = <0x3f>;
xbar_amx4_out: endpoint {
remote-endpoint = <&amx4_out>;
};
};
xbar_adx1_in_port: port@40 {
reg = <0x40>;
xbar_adx1_in: endpoint {
remote-endpoint = <&adx1_in>;
};
};
port@41 {
reg = <0x41>;
xbar_adx1_out1: endpoint {
remote-endpoint = <&adx1_out1>;
};
};
port@42 {
reg = <0x42>;
xbar_adx1_out2: endpoint {
remote-endpoint = <&adx1_out2>;
};
};
port@43 {
reg = <0x43>;
xbar_adx1_out3: endpoint {
remote-endpoint = <&adx1_out3>;
};
};
port@44 {
reg = <0x44>;
xbar_adx1_out4: endpoint {
remote-endpoint = <&adx1_out4>;
};
};
xbar_adx2_in_port: port@45 {
reg = <0x45>;
xbar_adx2_in: endpoint {
remote-endpoint = <&adx2_in>;
};
};
port@46 {
reg = <0x46>;
xbar_adx2_out1: endpoint {
remote-endpoint = <&adx2_out1>;
};
};
port@47 {
reg = <0x47>;
xbar_adx2_out2: endpoint {
remote-endpoint = <&adx2_out2>;
};
};
port@48 {
reg = <0x48>;
xbar_adx2_out3: endpoint {
remote-endpoint = <&adx2_out3>;
};
};
port@49 {
reg = <0x49>;
xbar_adx2_out4: endpoint {
remote-endpoint = <&adx2_out4>;
};
};
xbar_adx3_in_port: port@4a {
reg = <0x4a>;
xbar_adx3_in: endpoint {
remote-endpoint = <&adx3_in>;
};
};
port@4b {
reg = <0x4b>;
xbar_adx3_out1: endpoint {
remote-endpoint = <&adx3_out1>;
};
};
port@4c {
reg = <0x4c>;
xbar_adx3_out2: endpoint {
remote-endpoint = <&adx3_out2>;
};
};
port@4d {
reg = <0x4d>;
xbar_adx3_out3: endpoint {
remote-endpoint = <&adx3_out3>;
};
};
port@4e {
reg = <0x4e>;
xbar_adx3_out4: endpoint {
remote-endpoint = <&adx3_out4>;
};
};
xbar_adx4_in_port: port@4f {
reg = <0x4f>;
xbar_adx4_in: endpoint {
remote-endpoint = <&adx4_in>;
};
};
port@50 {
reg = <0x50>;
xbar_adx4_out1: endpoint {
remote-endpoint = <&adx4_out1>;
};
};
port@51 {
reg = <0x51>;
xbar_adx4_out2: endpoint {
remote-endpoint = <&adx4_out2>;
};
};
port@52 {
reg = <0x52>;
xbar_adx4_out3: endpoint {
remote-endpoint = <&adx4_out3>;
};
};
port@53 {
reg = <0x53>;
xbar_adx4_out4: endpoint {
remote-endpoint = <&adx4_out4>;
};
};
xbar_mix_in1_port: port@54 {
reg = <0x54>;
xbar_mix_in1: endpoint {
remote-endpoint = <&mix_in1>;
};
};
xbar_mix_in2_port: port@55 {
reg = <0x55>;
xbar_mix_in2: endpoint {
remote-endpoint = <&mix_in2>;
};
};
xbar_mix_in3_port: port@56 {
reg = <0x56>;
xbar_mix_in3: endpoint {
remote-endpoint = <&mix_in3>;
};
};
xbar_mix_in4_port: port@57 {
reg = <0x57>;
xbar_mix_in4: endpoint {
remote-endpoint = <&mix_in4>;
};
};
xbar_mix_in5_port: port@58 {
reg = <0x58>;
xbar_mix_in5: endpoint {
remote-endpoint = <&mix_in5>;
};
};
xbar_mix_in6_port: port@59 {
reg = <0x59>;
xbar_mix_in6: endpoint {
remote-endpoint = <&mix_in6>;
};
};
xbar_mix_in7_port: port@5a {
reg = <0x5a>;
xbar_mix_in7: endpoint {
remote-endpoint = <&mix_in7>;
};
};
xbar_mix_in8_port: port@5b {
reg = <0x5b>;
xbar_mix_in8: endpoint {
remote-endpoint = <&mix_in8>;
};
};
xbar_mix_in9_port: port@5c {
reg = <0x5c>;
xbar_mix_in9: endpoint {
remote-endpoint = <&mix_in9>;
};
};
xbar_mix_in10_port: port@5d {
reg = <0x5d>;
xbar_mix_in10: endpoint {
remote-endpoint = <&mix_in10>;
};
};
port@5e {
reg = <0x5e>;
xbar_mix_out1: endpoint {
remote-endpoint = <&mix_out1>;
};
};
port@5f {
reg = <0x5f>;
xbar_mix_out2: endpoint {
remote-endpoint = <&mix_out2>;
};
};
port@60 {
reg = <0x60>;
xbar_mix_out3: endpoint {
remote-endpoint = <&mix_out3>;
};
};
port@61 {
reg = <0x61>;
xbar_mix_out4: endpoint {
remote-endpoint = <&mix_out4>;
};
};
port@62 {
reg = <0x62>;
xbar_mix_out5: endpoint {
remote-endpoint = <&mix_out5>;
};
};
xbar_asrc_in1_port: port@63 {
reg = <0x63>;
xbar_asrc_in1_ep: endpoint {
remote-endpoint = <&asrc_in1_ep>;
};
};
port@64 {
reg = <0x64>;
xbar_asrc_out1_ep: endpoint {
remote-endpoint = <&asrc_out1_ep>;
};
};
xbar_asrc_in2_port: port@65 {
reg = <0x65>;
xbar_asrc_in2_ep: endpoint {
remote-endpoint = <&asrc_in2_ep>;
};
};
port@66 {
reg = <0x66>;
xbar_asrc_out2_ep: endpoint {
remote-endpoint = <&asrc_out2_ep>;
};
};
xbar_asrc_in3_port: port@67 {
reg = <0x67>;
xbar_asrc_in3_ep: endpoint {
remote-endpoint = <&asrc_in3_ep>;
};
};
port@68 {
reg = <0x68>;
xbar_asrc_out3_ep: endpoint {
remote-endpoint = <&asrc_out3_ep>;
};
};
xbar_asrc_in4_port: port@69 {
reg = <0x69>;
xbar_asrc_in4_ep: endpoint {
remote-endpoint = <&asrc_in4_ep>;
};
};
port@6a {
reg = <0x6a>;
xbar_asrc_out4_ep: endpoint {
remote-endpoint = <&asrc_out4_ep>;
};
};
xbar_asrc_in5_port: port@6b {
reg = <0x6b>;
xbar_asrc_in5_ep: endpoint {
remote-endpoint = <&asrc_in5_ep>;
};
};
port@6c {
reg = <0x6c>;
xbar_asrc_out5_ep: endpoint {
remote-endpoint = <&asrc_out5_ep>;
};
};
xbar_asrc_in6_port: port@6d {
reg = <0x6d>;
xbar_asrc_in6_ep: endpoint {
remote-endpoint = <&asrc_in6_ep>;
};
};
port@6e {
reg = <0x6e>;
xbar_asrc_out6_ep: endpoint {
remote-endpoint = <&asrc_out6_ep>;
};
};
xbar_asrc_in7_port: port@6f {
reg = <0x6f>;
xbar_asrc_in7_ep: endpoint {
remote-endpoint = <&asrc_in7_ep>;
};
};
xbar_ope1_in_port: port@70 {
reg = <0x70>;
xbar_ope1_in_ep: endpoint {
remote-endpoint = <&ope1_cif_in_ep>;
};
};
port@71 {
reg = <0x71>;
xbar_ope1_out_ep: endpoint {
remote-endpoint = <&ope1_cif_out_ep>;
};
};
};
};
dma-controller@2930000 {
status = "okay";
};
interrupt-controller@2a40000 {
status = "okay";
};
};
serial@3100000 {
compatible = "nvidia,tegra194-hsuart";
reset-names = "serial";
status = "okay";
};
serial@31d0000 {
current-speed = <115200>;
status = "okay";
};
i2c@31e0000 {
status = "okay";
audio-codec@1c {
compatible = "realtek,rt5640";
reg = <0x1c>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA234_MAIN_GPIO(AC, 5) GPIO_ACTIVE_HIGH>;
clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "mclk";
realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
sound-name-prefix = "CVB-RT";
port {
rt5640_ep: endpoint {
remote-endpoint = <&i2s1_dap>;
mclk-fs = <256>;
};
};
};
};
pwm@32a0000 {
......@@ -2099,6 +90,7 @@ usb2-0 {
mode = "otg";
usb-role-switch;
status = "okay";
port {
hs_typec_p1: endpoint {
remote-endpoint = <&hs_ucsi_ccg_p1>;
......@@ -2109,6 +101,7 @@ hs_typec_p1: endpoint {
usb2-1 {
mode = "host";
status = "okay";
port {
hs_typec_p0: endpoint {
remote-endpoint = <&hs_ucsi_ccg_p0>;
......@@ -2129,6 +122,7 @@ usb2-3 {
usb3-0 {
nvidia,usb2-companion = <1>;
status = "okay";
port {
ss_typec_p0: endpoint {
remote-endpoint = <&ss_ucsi_ccg_p0>;
......@@ -2139,6 +133,7 @@ ss_typec_p0: endpoint {
usb3-1 {
nvidia,usb2-companion = <0>;
status = "okay";
port {
ss_typec_p1: endpoint {
remote-endpoint = <&ss_ucsi_ccg_p1>;
......@@ -2194,57 +189,6 @@ mgbe0_phy: phy@0 {
};
};
pcie@14100000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_3>;
phy-names = "p2u-0";
};
pcie@14160000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
<&p2u_hsio_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
};
pcie@141a0000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
vpcie3v3-supply = <&vdd_3v3_pcie>;
vpcie12v-supply = <&vdd_12v_pcie>;
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
"p2u-5", "p2u-6", "p2u-7";
};
pcie-ep@141a0000 {
status = "disabled";
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
nvidia,refclk-select-gpios = <&gpio_aon
TEGRA234_AON_GPIO(AA, 4)
GPIO_ACTIVE_HIGH>;
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
"p2u-5", "p2u-6", "p2u-7";
};
i2c@c240000 {
status = "okay";
......@@ -2271,6 +215,7 @@ ports {
port@0 {
reg = <0>;
hs_ucsi_ccg_p0: endpoint {
remote-endpoint = <&hs_typec_p0>;
};
......@@ -2278,6 +223,7 @@ hs_ucsi_ccg_p0: endpoint {
port@1 {
reg = <1>;
ss_ucsi_ccg_p0: endpoint {
remote-endpoint = <&ss_typec_p0>;
};
......@@ -2297,6 +243,7 @@ ports {
port@0 {
reg = <0>;
hs_ucsi_ccg_p1: endpoint {
remote-endpoint = <&hs_typec_p1>;
};
......@@ -2304,6 +251,7 @@ hs_ucsi_ccg_p1: endpoint {
port@1 {
reg = <1>;
ss_ucsi_ccg_p1: endpoint {
remote-endpoint = <&ss_typec_p1>;
};
......@@ -2312,6 +260,57 @@ ss_ucsi_ccg_p1: endpoint {
};
};
};
pcie@14100000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_3>;
phy-names = "p2u-0";
};
pcie@14160000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
<&p2u_hsio_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
};
pcie@141a0000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
vpcie3v3-supply = <&vdd_3v3_pcie>;
vpcie12v-supply = <&vdd_12v_pcie>;
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
"p2u-5", "p2u-6", "p2u-7";
};
pcie-ep@141a0000 {
status = "disabled";
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
nvidia,refclk-select-gpios = <&gpio_aon
TEGRA234_AON_GPIO(AA, 4)
GPIO_ACTIVE_HIGH>;
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
"p2u-5", "p2u-6", "p2u-7";
};
};
gpio-keys {
......
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/sound/rt5640.h>
/ {
compatible = "nvidia,p3737-0000";
bus@0 {
aconnect@2900000 {
ahub@2900800 {
i2s@2901000 {
ports {
port@1 {
endpoint {
dai-format = "i2s";
remote-endpoint = <&rt5640_ep>;
};
};
};
};
};
};
i2c@3160000 {
status = "okay";
......@@ -20,6 +37,30 @@ eeprom@56 {
};
};
i2c@31e0000 {
status = "okay";
audio-codec@1c {
compatible = "realtek,rt5640";
reg = <0x1c>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA234_MAIN_GPIO(AC, 5) GPIO_ACTIVE_HIGH>;
clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "mclk";
realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
sound-name-prefix = "CVB-RT";
port {
rt5640_ep: endpoint {
remote-endpoint = <&i2s1_dap>;
mclk-fs = <256>;
};
};
};
};
pwm@3280000 {
status = "okay";
};
......
......@@ -12,6 +12,7 @@ / {
aliases {
serial0 = &tcu;
serial1 = &uarta;
};
chosen {
......@@ -19,104 +20,102 @@ chosen {
};
bus@0 {
host1x@13e00000 {
nvdec@15480000 {
status = "okay";
};
};
pcie@140e0000 {
serial@3100000 {
compatible = "nvidia,tegra194-hsuart";
reset-names = "serial";
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
phys = <&p2u_gbe_4>, <&p2u_gbe_5>;
phy-names = "p2u-0", "p2u-1";
};
pcie@14100000 {
i2c@3160000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_3>;
phy-names = "p2u-0";
};
pcie@14160000 {
i2c@3180000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_7>, <&p2u_hsio_6>, <&p2u_hsio_5>,
<&p2u_hsio_4>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
};
pcie@141a0000 {
i2c@3190000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
"p2u-5", "p2u-6", "p2u-7";
};
pcie@141e0000 {
i2c@31b0000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
phy-names = "p2u-0", "p2u-1";
};
aconnect@2900000 {
i2c@31c0000 {
status = "okay";
};
serial@3100000 {
compatible = "nvidia,tegra194-hsuart";
i2c@31e0000 {
status = "okay";
};
i2c@3160000 {
spi@3270000 {
status = "okay";
};
i2c@3180000 {
hda@3510000 {
nvidia,model = "NVIDIA IGX Orin HDA";
status = "okay";
};
i2c@3190000 {
fuse@3810000 {
status = "okay";
};
i2c@31b0000 {
i2c@c240000 {
status = "okay";
};
i2c@31c0000 {
i2c@c250000 {
status = "okay";
};
i2c@31e0000 {
status = "okay";
host1x@13e00000 {
nvdec@15480000 {
status = "okay";
};
};
spi@3270000 {
pcie@140e0000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
phys = <&p2u_gbe_4>, <&p2u_gbe_5>;
phy-names = "p2u-0", "p2u-1";
};
hda@3510000 {
nvidia,model = "NVIDIA IGX HDA";
pcie@14100000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
vpcie3v3-supply = <&vdd_3v3_wifi>;
phys = <&p2u_hsio_3>;
phy-names = "p2u-0";
};
fuse@3810000 {
pcie@14160000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_7>, <&p2u_hsio_6>, <&p2u_hsio_5>,
<&p2u_hsio_4>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
};
i2c@c240000 {
pcie@141a0000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
"p2u-5", "p2u-6", "p2u-7";
};
i2c@c250000 {
pcie@141e0000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
phy-names = "p2u-0", "p2u-1";
};
};
......@@ -151,4 +150,89 @@ key-suspend {
serial {
status = "okay";
};
sound {
status = "okay";
compatible = "nvidia,tegra186-audio-graph-card";
dais = /* ADMAIF (FE) Ports */
<&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
<&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
<&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
<&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
<&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
/* XBAR Ports */
<&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>,
<&xbar_i2s6_port>, <&xbar_dmic3_port>,
<&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
<&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
<&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
<&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
<&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
<&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
<&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
<&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
<&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
<&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
<&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
<&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
<&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
<&xbar_mix_in1_port>, <&xbar_mix_in2_port>,
<&xbar_mix_in3_port>, <&xbar_mix_in4_port>,
<&xbar_mix_in5_port>, <&xbar_mix_in6_port>,
<&xbar_mix_in7_port>, <&xbar_mix_in8_port>,
<&xbar_mix_in9_port>, <&xbar_mix_in10_port>,
<&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
<&xbar_ope1_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
<&mvc1_out_port>, <&mvc2_out_port>,
<&amx1_out_port>, <&amx2_out_port>,
<&amx3_out_port>, <&amx4_out_port>,
<&adx1_out1_port>, <&adx1_out2_port>,
<&adx1_out3_port>, <&adx1_out4_port>,
<&adx2_out1_port>, <&adx2_out2_port>,
<&adx2_out3_port>, <&adx2_out4_port>,
<&adx3_out1_port>, <&adx3_out2_port>,
<&adx3_out3_port>, <&adx3_out4_port>,
<&adx4_out1_port>, <&adx4_out2_port>,
<&adx4_out3_port>, <&adx4_out4_port>,
<&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>,
<&mix_out4_port>, <&mix_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
<&ope1_out_port>,
/* BE I/O Ports */
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
<&dmic3_port>;
label = "NVIDIA IGX Orin APE";
widgets = "Microphone", "CVB-RT MIC Jack",
"Microphone", "CVB-RT MIC",
"Headphone", "CVB-RT HP Jack",
"Speaker", "CVB-RT SPK";
routing = /* I2S4 <-> RT5640 */
"CVB-RT AIF1 Playback", "I2S4 DAP-Playback",
"I2S4 DAP-Capture", "CVB-RT AIF1 Capture",
/* RT5640 codec controls */
"CVB-RT HP Jack", "CVB-RT HPOL",
"CVB-RT HP Jack", "CVB-RT HPOR",
"CVB-RT IN1P", "CVB-RT MIC Jack",
"CVB-RT IN2P", "CVB-RT MIC Jack",
"CVB-RT IN2N", "CVB-RT MIC Jack",
"CVB-RT IN3P", "CVB-RT MIC Jack",
"CVB-RT SPK", "CVB-RT SPOLP",
"CVB-RT SPK", "CVB-RT SPORP",
"CVB-RT SPK", "CVB-RT LOUTL",
"CVB-RT SPK", "CVB-RT LOUTR",
"CVB-RT DMIC1", "CVB-RT MIC",
"CVB-RT DMIC2", "CVB-RT MIC";
};
};
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/sound/rt5640.h>
/ {
compatible = "nvidia,p3740-0002";
bus@0 {
aconnect@2900000 {
ahub@2900800 {
i2s@2901300 {
ports {
port@1 {
endpoint {
dai-format = "i2s";
remote-endpoint = <&rt5640_ep>;
};
};
};
};
i2s@2901500 {
ports {
port@1 {
endpoint {
bitclock-master;
frame-master;
};
};
};
};
};
};
i2c@31c0000 {
rt5640: audio-codec@1c {
compatible = "realtek,rt5640";
reg = <0x1c>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA234_MAIN_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "mclk";
realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
sound-name-prefix = "CVB-RT";
port {
rt5640_ep: endpoint {
remote-endpoint = <&i2s4_dap>;
mclk-fs = <256>;
};
};
};
/* carrier board ID EEPROM */
eeprom@55 {
compatible = "atmel,24c02";
......@@ -134,4 +184,32 @@ usb@3610000 {
"usb3-0", "usb3-1", "usb3-2";
};
};
vdd_3v3_dp: regulator-vdd-3v3-dp {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3_DP";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vdd_3v3_sys>;
gpio = <&gpio TEGRA234_MAIN_GPIO(H, 6) 0>;
enable-active-high;
regulator-always-on;
};
vdd_3v3_sys: regulator-vdd-3v3-sys {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3_SYS";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_3v3_wifi: regulator-vdd-3v3-wifi {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3_WIFI";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
regulator-boot-on;
enable-active-high;
};
};
......@@ -106,12 +106,18 @@ tj-thermal {
trips {
tj_trip_active0: active-0 {
temperature = <74000>;
temperature = <35000>;
hysteresis = <4000>;
type = "active";
};
tj_trip_active1: active-1 {
temperature = <74000>;
hysteresis = <4000>;
type = "active";
};
tj_trip_active2: active-2 {
temperature = <95000>;
hysteresis = <4000>;
type = "active";
......
......@@ -13,6 +13,8 @@ / {
aliases {
serial0 = &tcu;
serial1 = &uarta;
serial2 = &uarte;
};
chosen {
......@@ -20,8 +22,19 @@ chosen {
};
bus@0 {
serial@3100000 {
compatible = "nvidia,tegra194-hsuart";
reset-names = "serial";
status = "okay";
};
serial@3140000 {
compatible = "nvidia,tegra194-hsuart";
reset-names = "serial";
status = "okay";
};
serial@31d0000 {
current-speed = <115200>;
status = "okay";
};
......@@ -39,50 +52,6 @@ hda@3510000 {
padctl@3520000 {
status = "okay";
};
/* C1 - M.2 Key-E */
pcie@14100000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_3>;
phy-names = "p2u-0";
};
/* C4 - M.2 Key-M */
pcie@14160000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
<&p2u_hsio_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
};
/* C8 - Ethernet */
pcie@140a0000 {
status = "okay";
num-lanes = <2>;
phys = <&p2u_gbe_2>, <&p2u_gbe_3>;
phy-names = "p2u-0", "p2u-1";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
vpcie3v3-supply = <&vdd_3v3_pcie>;
};
/* C7 - M.2 Key-M */
pcie@141e0000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
phy-names = "p2u-0", "p2u-1";
};
};
gpio-keys {
......@@ -113,7 +82,7 @@ key-suspend {
};
pwm-fan {
cooling-levels = <0 187 255>;
cooling-levels = <0 88 187 255>;
};
vdd_3v3_pcie: regulator-vdd-3v3-pcie {
......@@ -141,6 +110,11 @@ map-active-1 {
cooling-device = <&fan 1 2>;
trip = <&tj_trip_active1>;
};
map-active-2 {
cooling-device = <&fan 2 3>;
trip = <&tj_trip_active2>;
};
};
};
};
......
......@@ -12,7 +12,7 @@ / {
model = "NVIDIA Jetson Orin Nano Developer Kit";
pwm-fan {
cooling-levels = <0 187 255>;
cooling-levels = <0 88 187 255>;
};
thermal-zones {
......@@ -27,6 +27,11 @@ map-active-1 {
cooling-device = <&fan 1 2>;
trip = <&tj_trip_active1>;
};
map-active-2 {
cooling-device = <&fan 2 3>;
trip = <&tj_trip_active2>;
};
};
};
};
......
......@@ -29,7 +29,6 @@ eeprom@57 {
};
serial@31d0000 {
current-speed = <115200>;
status = "okay";
};
......@@ -134,6 +133,19 @@ usb@3610000 {
"usb3-1";
};
/* C8 - Ethernet */
pcie@140a0000 {
status = "okay";
num-lanes = <2>;
phys = <&p2u_gbe_2>, <&p2u_gbe_3>;
phy-names = "p2u-0", "p2u-1";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
vpcie3v3-supply = <&vdd_3v3_pcie>;
};
/* C1 - M.2 Key-E */
pcie@14100000 {
status = "okay";
......@@ -155,19 +167,6 @@ pcie@14160000 {
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
};
/* C8 - Ethernet */
pcie@140a0000 {
status = "okay";
num-lanes = <2>;
phys = <&p2u_gbe_2>, <&p2u_gbe_3>;
phy-names = "p2u-0", "p2u-1";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
vpcie3v3-supply = <&vdd_3v3_pcie>;
};
/* C7 - M.2 Key-M */
pcie@141e0000 {
status = "okay";
......
......@@ -19,6 +19,8 @@ chosen {
bus@0 {
serial@3100000 {
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
};
......
......@@ -180,7 +180,8 @@ tegra_ahub: ahub@2900800 {
clocks = <&bpmp TEGRA234_CLK_AHUB>;
clock-names = "ahub";
assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clock-rates = <81600000>;
status = "disabled";
#address-cells = <2>;
......@@ -687,6 +688,15 @@ uarta: serial@3100000 {
status = "disabled";
};
uarte: serial@3140000 {
compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03140000 0x0 0x10000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_UARTE>;
resets = <&bpmp TEGRA234_RESET_UARTE>;
status = "disabled";
};
gen1_i2c: i2c@3160000 {
compatible = "nvidia,tegra194-i2c";
reg = <0x0 0x3160000 0x0 0x100>;
......@@ -808,6 +818,44 @@ dp_aux_ch3_i2c: i2c@31e0000 {
dma-names = "rx", "tx";
};
spi@3210000 {
compatible = "nvidia,tegra210-spi";
reg = <0x0 0x03210000 0x0 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA234_CLK_SPI1>;
assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "spi";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
resets = <&bpmp TEGRA234_RESET_SPI1>;
reset-names = "spi";
dmas = <&gpcdma 15>, <&gpcdma 15>;
dma-names = "rx", "tx";
dma-coherent;
status = "disabled";
};
spi@3230000 {
compatible = "nvidia,tegra210-spi";
reg = <0x0 0x03230000 0x0 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA234_CLK_SPI3>;
clock-names = "spi";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
resets = <&bpmp TEGRA234_RESET_SPI3>;
reset-names = "spi";
dmas = <&gpcdma 17>, <&gpcdma 17>;
dma-names = "rx", "tx";
dma-coherent;
status = "disabled";
};
spi@3270000 {
compatible = "nvidia,tegra234-qspi";
reg = <0x0 0x3270000 0x0 0x1000>;
......@@ -1733,6 +1781,25 @@ gen8_i2c: i2c@c250000 {
dma-names = "rx", "tx";
};
spi@c260000 {
compatible = "nvidia,tegra210-spi";
reg = <0x0 0x0c260000 0x0 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA234_CLK_SPI2>;
clock-names = "spi";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
resets = <&bpmp TEGRA234_RESET_SPI2>;
reset-names = "spi";
dmas = <&gpcdma 19>, <&gpcdma 19>;
dma-names = "rx", "tx";
dma-coherent;
status = "disabled";
};
rtc@c2a0000 {
compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
reg = <0x0 0x0c2a0000 0x0 0x10000>;
......@@ -3589,72 +3656,142 @@ cl0_ch1_opp1: opp-115200000 {
opp-peak-kBps = <816000>;
};
cl0_ch1_opp2: opp-268800000 {
cl0_ch1_opp2: opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp3: opp-268800000 {
opp-hz = /bits/ 64 <268800000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp3: opp-422400000 {
cl0_ch1_opp4: opp-345600000 {
opp-hz = /bits/ 64 <345600000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp5: opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp4: opp-576000000 {
cl0_ch1_opp6: opp-499200000 {
opp-hz = /bits/ 64 <499200000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp7: opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp5: opp-729600000 {
cl0_ch1_opp8: opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp9: opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp6: opp-883200000 {
cl0_ch1_opp10: opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp11: opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp7: opp-1036800000 {
cl0_ch1_opp12: opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp13: opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <816000>;
};
cl0_ch1_opp8: opp-1190400000 {
cl0_ch1_opp14: opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-peak-kBps = <1632000>;
};
cl0_ch1_opp15: opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <816000>;
opp-peak-kBps = <1632000>;
};
cl0_ch1_opp16: opp-1267200000 {
opp-hz = /bits/ 64 <1267200000>;
opp-peak-kBps = <1632000>;
};
cl0_ch1_opp9: opp-1344000000 {
cl0_ch1_opp17: opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <1632000>;
};
cl0_ch1_opp10: opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
cl0_ch1_opp18: opp-1420800000 {
opp-hz = /bits/ 64 <1420800000>;
opp-peak-kBps = <1632000>;
};
cl0_ch1_opp11: opp-1651200000 {
cl0_ch1_opp19: opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <3200000>;
};
cl0_ch1_opp20: opp-1574400000 {
opp-hz = /bits/ 64 <1574400000>;
opp-peak-kBps = <3200000>;
};
cl0_ch1_opp21: opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <2660000>;
opp-peak-kBps = <3200000>;
};
cl0_ch1_opp12: opp-1804800000 {
cl0_ch1_opp22: opp-1728000000 {
opp-hz = /bits/ 64 <1728000000>;
opp-peak-kBps = <3200000>;
};
cl0_ch1_opp23: opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <2660000>;
opp-peak-kBps = <3200000>;
};
cl0_ch1_opp13: opp-1958400000 {
cl0_ch1_opp24: opp-1881600000 {
opp-hz = /bits/ 64 <1881600000>;
opp-peak-kBps = <3200000>;
};
cl0_ch1_opp25: opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <3200000>;
};
cl0_ch1_opp14: opp-2112000000 {
cl0_ch1_opp26: opp-2035200000 {
opp-hz = /bits/ 64 <2035200000>;
opp-peak-kBps = <3200000>;
};
cl0_ch1_opp27: opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <6400000>;
};
cl0_ch1_opp15: opp-2201600000 {
cl0_ch1_opp28: opp-2188800000 {
opp-hz = /bits/ 64 <2188800000>;
opp-peak-kBps = <6400000>;
};
cl0_ch1_opp29: opp-2201600000 {
opp-hz = /bits/ 64 <2201600000>;
opp-peak-kBps = <6400000>;
};
......@@ -3669,72 +3806,142 @@ cl1_ch1_opp1: opp-115200000 {
opp-peak-kBps = <816000>;
};
cl1_ch1_opp2: opp-268800000 {
cl1_ch1_opp2: opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp3: opp-268800000 {
opp-hz = /bits/ 64 <268800000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp3: opp-422400000 {
cl1_ch1_opp4: opp-345600000 {
opp-hz = /bits/ 64 <345600000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp5: opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp4: opp-576000000 {
cl1_ch1_opp6: opp-499200000 {
opp-hz = /bits/ 64 <499200000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp7: opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp5: opp-729600000 {
cl1_ch1_opp8: opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp9: opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp6: opp-883200000 {
cl1_ch1_opp10: opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp11: opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp7: opp-1036800000 {
cl1_ch1_opp12: opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp13: opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <816000>;
};
cl1_ch1_opp8: opp-1190400000 {
cl1_ch1_opp14: opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-peak-kBps = <1632000>;
};
cl1_ch1_opp15: opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <816000>;
opp-peak-kBps = <1632000>;
};
cl1_ch1_opp16: opp-1267200000 {
opp-hz = /bits/ 64 <1267200000>;
opp-peak-kBps = <1632000>;
};
cl1_ch1_opp9: opp-1344000000 {
cl1_ch1_opp17: opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <1632000>;
};
cl1_ch1_opp10: opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
cl1_ch1_opp18: opp-1420800000 {
opp-hz = /bits/ 64 <1420800000>;
opp-peak-kBps = <1632000>;
};
cl1_ch1_opp11: opp-1651200000 {
cl1_ch1_opp19: opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <3200000>;
};
cl1_ch1_opp20: opp-1574400000 {
opp-hz = /bits/ 64 <1574400000>;
opp-peak-kBps = <3200000>;
};
cl1_ch1_opp21: opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <2660000>;
opp-peak-kBps = <3200000>;
};
cl1_ch1_opp12: opp-1804800000 {
cl1_ch1_opp22: opp-1728000000 {
opp-hz = /bits/ 64 <1728000000>;
opp-peak-kBps = <3200000>;
};
cl1_ch1_opp23: opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <2660000>;
opp-peak-kBps = <3200000>;
};
cl1_ch1_opp24: opp-1881600000 {
opp-hz = /bits/ 64 <1881600000>;
opp-peak-kBps = <3200000>;
};
cl1_ch1_opp13: opp-1958400000 {
cl1_ch1_opp25: opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <3200000>;
};
cl1_ch1_opp14: opp-2112000000 {
cl1_ch1_opp26: opp-2035200000 {
opp-hz = /bits/ 64 <2035200000>;
opp-peak-kBps = <3200000>;
};
cl1_ch1_opp27: opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <6400000>;
};
cl1_ch1_opp15: opp-2201600000 {
cl1_ch1_opp28: opp-2188800000 {
opp-hz = /bits/ 64 <2188800000>;
opp-peak-kBps = <6400000>;
};
cl1_ch1_opp29: opp-2201600000 {
opp-hz = /bits/ 64 <2201600000>;
opp-peak-kBps = <6400000>;
};
......@@ -3749,72 +3956,142 @@ cl2_ch1_opp1: opp-115200000 {
opp-peak-kBps = <816000>;
};
cl2_ch1_opp2: opp-268800000 {
cl2_ch1_opp2: opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp3: opp-268800000 {
opp-hz = /bits/ 64 <268800000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp3: opp-422400000 {
cl2_ch1_opp4: opp-345600000 {
opp-hz = /bits/ 64 <345600000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp5: opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp4: opp-576000000 {
cl2_ch1_opp6: opp-499200000 {
opp-hz = /bits/ 64 <499200000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp7: opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp5: opp-729600000 {
cl2_ch1_opp8: opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp9: opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp6: opp-883200000 {
cl2_ch1_opp10: opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp11: opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp7: opp-1036800000 {
cl2_ch1_opp12: opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp13: opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <816000>;
};
cl2_ch1_opp8: opp-1190400000 {
cl2_ch1_opp14: opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-peak-kBps = <1632000>;
};
cl2_ch1_opp15: opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <816000>;
opp-peak-kBps = <1632000>;
};
cl2_ch1_opp9: opp-1344000000 {
cl2_ch1_opp16: opp-1267200000 {
opp-hz = /bits/ 64 <1267200000>;
opp-peak-kBps = <1632000>;
};
cl2_ch1_opp17: opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <1632000>;
};
cl2_ch1_opp10: opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
cl2_ch1_opp18: opp-1420800000 {
opp-hz = /bits/ 64 <1420800000>;
opp-peak-kBps = <1632000>;
};
cl2_ch1_opp11: opp-1651200000 {
cl2_ch1_opp19: opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <3200000>;
};
cl2_ch1_opp20: opp-1574400000 {
opp-hz = /bits/ 64 <1574400000>;
opp-peak-kBps = <3200000>;
};
cl2_ch1_opp21: opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <2660000>;
opp-peak-kBps = <3200000>;
};
cl2_ch1_opp22: opp-1728000000 {
opp-hz = /bits/ 64 <1728000000>;
opp-peak-kBps = <3200000>;
};
cl2_ch1_opp12: opp-1804800000 {
cl2_ch1_opp23: opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <2660000>;
opp-peak-kBps = <3200000>;
};
cl2_ch1_opp13: opp-1958400000 {
cl2_ch1_opp24: opp-1881600000 {
opp-hz = /bits/ 64 <1881600000>;
opp-peak-kBps = <3200000>;
};
cl2_ch1_opp25: opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <3200000>;
};
cl2_ch1_opp14: opp-2112000000 {
cl2_ch1_opp26: opp-2035200000 {
opp-hz = /bits/ 64 <2035200000>;
opp-peak-kBps = <3200000>;
};
cl2_ch1_opp27: opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <6400000>;
};
cl2_ch1_opp15: opp-2201600000 {
cl2_ch1_opp28: opp-2188800000 {
opp-hz = /bits/ 64 <2188800000>;
opp-peak-kBps = <6400000>;
};
cl2_ch1_opp29: opp-2201600000 {
opp-hz = /bits/ 64 <2201600000>;
opp-peak-kBps = <6400000>;
};
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment