Commit d65b1278 authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville

ath9k: Fix temperature compensation

The registers for temperature compensation need to
be programmed only for active chains. Use the TX chainmask
to make sure that this is done properly for QCA953x.
Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent c90d4f7b
...@@ -4792,28 +4792,36 @@ static void ar9003_hw_power_control_override(struct ath_hw *ah, ...@@ -4792,28 +4792,36 @@ static void ar9003_hw_power_control_override(struct ath_hw *ah,
tempslope: tempslope:
if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) { if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
u8 txmask = (eep->baseEepHeader.txrxMask & 0xf0) >> 4;
/* /*
* AR955x has tempSlope register for each chain. * AR955x has tempSlope register for each chain.
* Check whether temp_compensation feature is enabled or not. * Check whether temp_compensation feature is enabled or not.
*/ */
if (eep->baseEepHeader.featureEnable & 0x1) { if (eep->baseEepHeader.featureEnable & 0x1) {
if (frequency < 4000) { if (frequency < 4000) {
if (txmask & BIT(0))
REG_RMW_FIELD(ah, AR_PHY_TPC_19, REG_RMW_FIELD(ah, AR_PHY_TPC_19,
AR_PHY_TPC_19_ALPHA_THERM, AR_PHY_TPC_19_ALPHA_THERM,
eep->base_ext2.tempSlopeLow); eep->base_ext2.tempSlopeLow);
if (txmask & BIT(1))
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
AR_PHY_TPC_19_ALPHA_THERM, AR_PHY_TPC_19_ALPHA_THERM,
temp_slope); temp_slope);
if (txmask & BIT(2))
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
AR_PHY_TPC_19_ALPHA_THERM, AR_PHY_TPC_19_ALPHA_THERM,
eep->base_ext2.tempSlopeHigh); eep->base_ext2.tempSlopeHigh);
} else { } else {
if (txmask & BIT(0))
REG_RMW_FIELD(ah, AR_PHY_TPC_19, REG_RMW_FIELD(ah, AR_PHY_TPC_19,
AR_PHY_TPC_19_ALPHA_THERM, AR_PHY_TPC_19_ALPHA_THERM,
temp_slope); temp_slope);
if (txmask & BIT(1))
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
AR_PHY_TPC_19_ALPHA_THERM, AR_PHY_TPC_19_ALPHA_THERM,
temp_slope1); temp_slope1);
if (txmask & BIT(2))
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
AR_PHY_TPC_19_ALPHA_THERM, AR_PHY_TPC_19_ALPHA_THERM,
temp_slope2); temp_slope2);
...@@ -4823,10 +4831,13 @@ static void ar9003_hw_power_control_override(struct ath_hw *ah, ...@@ -4823,10 +4831,13 @@ static void ar9003_hw_power_control_override(struct ath_hw *ah,
* If temp compensation is not enabled, * If temp compensation is not enabled,
* set all registers to 0. * set all registers to 0.
*/ */
if (txmask & BIT(0))
REG_RMW_FIELD(ah, AR_PHY_TPC_19, REG_RMW_FIELD(ah, AR_PHY_TPC_19,
AR_PHY_TPC_19_ALPHA_THERM, 0); AR_PHY_TPC_19_ALPHA_THERM, 0);
if (txmask & BIT(1))
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
AR_PHY_TPC_19_ALPHA_THERM, 0); AR_PHY_TPC_19_ALPHA_THERM, 0);
if (txmask & BIT(2))
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
AR_PHY_TPC_19_ALPHA_THERM, 0); AR_PHY_TPC_19_ALPHA_THERM, 0);
} }
......
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