Skip to content

L
linux
Commit d672d0b0 authored by David S. Miller's avatar David S. Miller
Browse files
Options

[SPARC64]: header cleanup, extern inline --> static inline

parent d175a2f8
Hide whitespace changes
Inline Side-by-side
Showing with 90 additions and 90 deletions
include/asm-sparc64/checksum.h
View file @ d672d0b0
...@@ -40,7 +40,7 @@ extern unsigned int csum_partial(const unsigned char * buff, int len, unsigned i ...@@ -40,7 +40,7 @@ extern unsigned int csum_partial(const unsigned char * buff, int len, unsigned i
*/ */
extern unsigned int csum_partial_copy_sparc64(const char *src, char *dst, int len, unsigned int sum); extern unsigned int csum_partial_copy_sparc64(const char *src, char *dst, int len, unsigned int sum);
extern __inline__ unsigned int static __inline__ unsigned int
csum_partial_copy_nocheck (const char *src, char *dst, int len, csum_partial_copy_nocheck (const char *src, char *dst, int len,
unsigned int sum) unsigned int sum)
{ {
...@@ -52,7 +52,7 @@ csum_partial_copy_nocheck (const char *src, char *dst, int len, ...@@ -52,7 +52,7 @@ csum_partial_copy_nocheck (const char *src, char *dst, int len,
return ret; return ret;
} }
extern __inline__ unsigned int static __inline__ unsigned int
csum_partial_copy_from_user(const char *src, char *dst, int len, csum_partial_copy_from_user(const char *src, char *dst, int len,
unsigned int sum, int *err) unsigned int sum, int *err)
{ {
...@@ -66,7 +66,7 @@ csum_partial_copy_from_user(const char *src, char *dst, int len, ...@@ -66,7 +66,7 @@ csum_partial_copy_from_user(const char *src, char *dst, int len,
*/ */
#define HAVE_CSUM_COPY_USER #define HAVE_CSUM_COPY_USER
extern unsigned int csum_partial_copy_user_sparc64(const char *src, char *dst, int len, unsigned int sum); extern unsigned int csum_partial_copy_user_sparc64(const char *src, char *dst, int len, unsigned int sum);
extern __inline__ unsigned int static __inline__ unsigned int
csum_and_copy_to_user(const char *src, char *dst, int len, csum_and_copy_to_user(const char *src, char *dst, int len,
unsigned int sum, int *err) unsigned int sum, int *err)
{ {
...@@ -78,7 +78,7 @@ csum_and_copy_to_user(const char *src, char *dst, int len, ...@@ -78,7 +78,7 @@ csum_and_copy_to_user(const char *src, char *dst, int len,
/* ihl is always 5 or greater, almost always is 5, and iph is word aligned /* ihl is always 5 or greater, almost always is 5, and iph is word aligned
* the majority of the time. * the majority of the time.
*/ */
extern __inline__ unsigned short ip_fast_csum(__const__ unsigned char *iph, static __inline__ unsigned short ip_fast_csum(__const__ unsigned char *iph,
unsigned int ihl) unsigned int ihl)
{ {
unsigned short sum; unsigned short sum;
...@@ -119,7 +119,7 @@ extern __inline__ unsigned short ip_fast_csum(__const__ unsigned char *iph, ...@@ -119,7 +119,7 @@ extern __inline__ unsigned short ip_fast_csum(__const__ unsigned char *iph,
} }
/* Fold a partial checksum without adding pseudo headers. */ /* Fold a partial checksum without adding pseudo headers. */
extern __inline__ unsigned short csum_fold(unsigned int sum) static __inline__ unsigned short csum_fold(unsigned int sum)
{ {
unsigned int tmp; unsigned int tmp;
...@@ -134,7 +134,7 @@ extern __inline__ unsigned short csum_fold(unsigned int sum) ...@@ -134,7 +134,7 @@ extern __inline__ unsigned short csum_fold(unsigned int sum)
return (sum & 0xffff); return (sum & 0xffff);
} }
extern __inline__ unsigned long csum_tcpudp_nofold(unsigned long saddr, static __inline__ unsigned long csum_tcpudp_nofold(unsigned long saddr,
unsigned long daddr, unsigned long daddr,
unsigned int len, unsigned int len,
unsigned short proto, unsigned short proto,
...@@ -201,7 +201,7 @@ static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr, ...@@ -201,7 +201,7 @@ static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
} }
/* this routine is used for miscellaneous IP-like checksums, mainly in icmp.c */ /* this routine is used for miscellaneous IP-like checksums, mainly in icmp.c */
extern __inline__ unsigned short ip_compute_csum(unsigned char * buff, int len) static __inline__ unsigned short ip_compute_csum(unsigned char * buff, int len)
{ {
return csum_fold(csum_partial(buff, len, 0)); return csum_fold(csum_partial(buff, len, 0));
} }
......
include/asm-sparc64/delay.h
View file @ d672d0b0
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
extern unsigned long loops_per_jiffy; extern unsigned long loops_per_jiffy;
#endif #endif
extern __inline__ void __delay(unsigned long loops) static __inline__ void __delay(unsigned long loops)
{ {
__asm__ __volatile__( __asm__ __volatile__(
" b,pt %%xcc, 1f\n" " b,pt %%xcc, 1f\n"
...@@ -32,7 +32,7 @@ extern __inline__ void __delay(unsigned long loops) ...@@ -32,7 +32,7 @@ extern __inline__ void __delay(unsigned long loops)
: "cc"); : "cc");
} }
extern __inline__ void __udelay(unsigned long usecs, unsigned long lps) static __inline__ void __udelay(unsigned long usecs, unsigned long lps)
{ {
usecs *= 0x00000000000010c6UL; /* 2**32 / 1000000 */ usecs *= 0x00000000000010c6UL; /* 2**32 / 1000000 */
......
include/asm-sparc64/fpumacro.h
View file @ d672d0b0
...@@ -16,7 +16,7 @@ struct fpustate { ...@@ -16,7 +16,7 @@ struct fpustate {
#define FPUSTATE (struct fpustate *)(current_thread_info()->fpregs) #define FPUSTATE (struct fpustate *)(current_thread_info()->fpregs)
extern __inline__ unsigned long fprs_read(void) static __inline__ unsigned long fprs_read(void)
{ {
unsigned long retval; unsigned long retval;
...@@ -25,7 +25,7 @@ extern __inline__ unsigned long fprs_read(void) ...@@ -25,7 +25,7 @@ extern __inline__ unsigned long fprs_read(void)
return retval; return retval;
} }
extern __inline__ void fprs_write(unsigned long val) static __inline__ void fprs_write(unsigned long val)
{ {
__asm__ __volatile__("wr %0, 0x0, %%fprs" : : "r" (val)); __asm__ __volatile__("wr %0, 0x0, %%fprs" : : "r" (val));
} }
......
include/asm-sparc64/irq.h
View file @ d672d0b0
...@@ -133,21 +133,21 @@ extern int request_fast_irq(unsigned int irq, ...@@ -133,21 +133,21 @@ extern int request_fast_irq(unsigned int irq,
unsigned long flags, __const__ char *devname, unsigned long flags, __const__ char *devname,
void *dev_id); void *dev_id);
extern __inline__ void set_softint(unsigned long bits) static __inline__ void set_softint(unsigned long bits)
{ {
__asm__ __volatile__("wr %0, 0x0, %%set_softint" __asm__ __volatile__("wr %0, 0x0, %%set_softint"
: /* No outputs */ : /* No outputs */
: "r" (bits)); : "r" (bits));
} }
extern __inline__ void clear_softint(unsigned long bits) static __inline__ void clear_softint(unsigned long bits)
{ {
__asm__ __volatile__("wr %0, 0x0, %%clear_softint" __asm__ __volatile__("wr %0, 0x0, %%clear_softint"
: /* No outputs */ : /* No outputs */
: "r" (bits)); : "r" (bits));
} }
extern __inline__ unsigned long get_softint(void) static __inline__ unsigned long get_softint(void)
{ {
unsigned long retval; unsigned long retval;
......
include/asm-sparc64/page.h
View file @ d672d0b0
...@@ -161,7 +161,7 @@ struct sparc_phys_banks { ...@@ -161,7 +161,7 @@ struct sparc_phys_banks {
extern struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS]; extern struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
/* Pure 2^n version of get_order */ /* Pure 2^n version of get_order */
extern __inline__ int get_order(unsigned long size) static __inline__ int get_order(unsigned long size)
{ {
int order; int order;
......
include/asm-sparc64/pci.h
View file @ d672d0b0
...@@ -17,12 +17,12 @@ ...@@ -17,12 +17,12 @@
#define PCI_IRQ_NONE 0xffffffff #define PCI_IRQ_NONE 0xffffffff
extern inline void pcibios_set_master(struct pci_dev *dev) static inline void pcibios_set_master(struct pci_dev *dev)
{ {
/* No special bus mastering setup handling */ /* No special bus mastering setup handling */
} }
extern inline void pcibios_penalize_isa_irq(int irq) static inline void pcibios_penalize_isa_irq(int irq)
{ {
/* We don't do dynamic PCI IRQ allocation */ /* We don't do dynamic PCI IRQ allocation */
} }
......
include/asm-sparc64/pgtable.h
View file @ d672d0b0
...@@ -212,7 +212,7 @@ extern struct page *mem_map_zero; ...@@ -212,7 +212,7 @@ extern struct page *mem_map_zero;
#define page_pte_prot(page, prot) mk_pte(page, prot) #define page_pte_prot(page, prot) mk_pte(page, prot)
#define page_pte(page) page_pte_prot(page, __pgprot(0)) #define page_pte(page) page_pte_prot(page, __pgprot(0))
extern inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot) static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
{ {
pte_t __pte; pte_t __pte;
...@@ -291,7 +291,7 @@ struct vm_area_struct; ...@@ -291,7 +291,7 @@ struct vm_area_struct;
extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
/* Make a non-present pseudo-TTE. */ /* Make a non-present pseudo-TTE. */
extern inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space) static inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space)
{ {
pte_t pte; pte_t pte;
pte_val(pte) = ((page) | pgprot_val(prot) | _PAGE_E) & ~(unsigned long)_PAGE_CACHE; pte_val(pte) = ((page) | pgprot_val(prot) | _PAGE_E) & ~(unsigned long)_PAGE_CACHE;
...@@ -313,7 +313,7 @@ extern inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space) ...@@ -313,7 +313,7 @@ extern inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space)
extern unsigned long prom_virt_to_phys(unsigned long, int *); extern unsigned long prom_virt_to_phys(unsigned long, int *);
extern __inline__ unsigned long static __inline__ unsigned long
sun4u_get_pte (unsigned long addr) sun4u_get_pte (unsigned long addr)
{ {
pgd_t *pgdp; pgd_t *pgdp;
...@@ -330,13 +330,13 @@ sun4u_get_pte (unsigned long addr) ...@@ -330,13 +330,13 @@ sun4u_get_pte (unsigned long addr)
return pte_val(*ptep) & _PAGE_PADDR; return pte_val(*ptep) & _PAGE_PADDR;
} }
extern __inline__ unsigned long static __inline__ unsigned long
__get_phys (unsigned long addr) __get_phys (unsigned long addr)
{ {
return sun4u_get_pte (addr); return sun4u_get_pte (addr);
} }
extern __inline__ int static __inline__ int
__get_iospace (unsigned long addr) __get_iospace (unsigned long addr)
{ {
return ((sun4u_get_pte (addr) & 0xf0000000) >> 28); return ((sun4u_get_pte (addr) & 0xf0000000) >> 28);
......
include/asm-sparc64/psrcompat.h
View file @ d672d0b0
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#define PSR_V8PLUS 0xff000000 /* fake impl/ver, meaning a 64bit CPU is present */ #define PSR_V8PLUS 0xff000000 /* fake impl/ver, meaning a 64bit CPU is present */
#define PSR_XCC 0x000f0000 /* if PSR_V8PLUS, this is %xcc */ #define PSR_XCC 0x000f0000 /* if PSR_V8PLUS, this is %xcc */
extern inline unsigned int tstate_to_psr(unsigned long tstate) static inline unsigned int tstate_to_psr(unsigned long tstate)
{ {
return ((tstate & TSTATE_CWP) | return ((tstate & TSTATE_CWP) |
PSR_S | PSR_S |
...@@ -33,7 +33,7 @@ extern inline unsigned int tstate_to_psr(unsigned long tstate) ...@@ -33,7 +33,7 @@ extern inline unsigned int tstate_to_psr(unsigned long tstate)
PSR_V8PLUS); PSR_V8PLUS);
} }
extern inline unsigned long psr_to_tstate_icc(unsigned int psr) static inline unsigned long psr_to_tstate_icc(unsigned int psr)
{ {
unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12; unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12;
if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS) if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS)
......
include/asm-sparc64/sbus.h
View file @ d672d0b0
...@@ -27,12 +27,12 @@ ...@@ -27,12 +27,12 @@
* numbers + offsets, and vice versa. * numbers + offsets, and vice versa.
*/ */
extern __inline__ unsigned long sbus_devaddr(int slotnum, unsigned long offset) static __inline__ unsigned long sbus_devaddr(int slotnum, unsigned long offset)
{ {
return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<28)+(offset)); return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<28)+(offset));
} }
extern __inline__ int sbus_dev_slot(unsigned long dev_addr) static __inline__ int sbus_dev_slot(unsigned long dev_addr)
{ {
return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>28); return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>28);
} }
......
include/asm-sparc64/siginfo.h
View file @ d672d0b0
...@@ -154,7 +154,7 @@ typedef struct sigevent32 { ...@@ -154,7 +154,7 @@ typedef struct sigevent32 {
#include <linux/string.h> #include <linux/string.h>
extern inline void copy_siginfo(siginfo_t *to, siginfo_t *from) static inline void copy_siginfo(siginfo_t *to, siginfo_t *from)
{ {
if (from->si_code < 0) if (from->si_code < 0)
*to = *from; *to = *from;
......
include/asm-sparc64/smp.h
View file @ d672d0b0
...@@ -89,7 +89,7 @@ static inline int any_online_cpu(unsigned long mask) ...@@ -89,7 +89,7 @@ static inline int any_online_cpu(unsigned long mask)
* General functions that each host system must provide. * General functions that each host system must provide.
*/ */
extern __inline__ int hard_smp_processor_id(void) static __inline__ int hard_smp_processor_id(void)
{ {
if (tlb_type == cheetah || tlb_type == cheetah_plus) { if (tlb_type == cheetah || tlb_type == cheetah_plus) {
unsigned long safari_config; unsigned long safari_config;
...@@ -130,7 +130,7 @@ static __inline__ void smp_send_reschedule(int cpu) ...@@ -130,7 +130,7 @@ static __inline__ void smp_send_reschedule(int cpu)
/* This is a nop as well because we capture all other cpus /* This is a nop as well because we capture all other cpus
* anyways when making the PROM active. * anyways when making the PROM active.
*/ */
extern __inline__ void smp_send_stop(void) { } static __inline__ void smp_send_stop(void) { }
#endif /* !(__ASSEMBLY__) */ #endif /* !(__ASSEMBLY__) */
......
include/asm-sparc64/spinlock.h
View file @ d672d0b0
...@@ -40,7 +40,7 @@ typedef unsigned char spinlock_t; ...@@ -40,7 +40,7 @@ typedef unsigned char spinlock_t;
do { membar("#LoadLoad"); \ do { membar("#LoadLoad"); \
} while(*((volatile unsigned char *)lock)) } while(*((volatile unsigned char *)lock))
extern __inline__ void _raw_spin_lock(spinlock_t *lock) static __inline__ void _raw_spin_lock(spinlock_t *lock)
{ {
__asm__ __volatile__( __asm__ __volatile__(
"1: ldstub [%0], %%g7\n" "1: ldstub [%0], %%g7\n"
...@@ -57,7 +57,7 @@ extern __inline__ void _raw_spin_lock(spinlock_t *lock) ...@@ -57,7 +57,7 @@ extern __inline__ void _raw_spin_lock(spinlock_t *lock)
: "g7", "memory"); : "g7", "memory");
} }
extern __inline__ int _raw_spin_trylock(spinlock_t *lock) static __inline__ int _raw_spin_trylock(spinlock_t *lock)
{ {
unsigned int result; unsigned int result;
__asm__ __volatile__("ldstub [%1], %0\n\t" __asm__ __volatile__("ldstub [%1], %0\n\t"
...@@ -68,7 +68,7 @@ extern __inline__ int _raw_spin_trylock(spinlock_t *lock) ...@@ -68,7 +68,7 @@ extern __inline__ int _raw_spin_trylock(spinlock_t *lock)
return (result == 0); return (result == 0);
} }
extern __inline__ void _raw_spin_unlock(spinlock_t *lock) static __inline__ void _raw_spin_unlock(spinlock_t *lock)
{ {
__asm__ __volatile__("membar #StoreStore | #LoadStore\n\t" __asm__ __volatile__("membar #StoreStore | #LoadStore\n\t"
"stb %%g0, [%0]" "stb %%g0, [%0]"
......
include/asm-sparc64/spitfire.h
View file @ d672d0b0
...@@ -56,7 +56,7 @@ extern enum ultra_tlb_layout tlb_type; ...@@ -56,7 +56,7 @@ extern enum ultra_tlb_layout tlb_type;
SPITFIRE_HIGHEST_LOCKED_TLBENT : \ SPITFIRE_HIGHEST_LOCKED_TLBENT : \
CHEETAH_HIGHEST_LOCKED_TLBENT) CHEETAH_HIGHEST_LOCKED_TLBENT)
extern __inline__ unsigned long spitfire_get_isfsr(void) static __inline__ unsigned long spitfire_get_isfsr(void)
{ {
unsigned long ret; unsigned long ret;
...@@ -66,7 +66,7 @@ extern __inline__ unsigned long spitfire_get_isfsr(void) ...@@ -66,7 +66,7 @@ extern __inline__ unsigned long spitfire_get_isfsr(void)
return ret; return ret;
} }
extern __inline__ unsigned long spitfire_get_dsfsr(void) static __inline__ unsigned long spitfire_get_dsfsr(void)
{ {
unsigned long ret; unsigned long ret;
...@@ -76,7 +76,7 @@ extern __inline__ unsigned long spitfire_get_dsfsr(void) ...@@ -76,7 +76,7 @@ extern __inline__ unsigned long spitfire_get_dsfsr(void)
return ret; return ret;
} }
extern __inline__ unsigned long spitfire_get_sfar(void) static __inline__ unsigned long spitfire_get_sfar(void)
{ {
unsigned long ret; unsigned long ret;
...@@ -86,7 +86,7 @@ extern __inline__ unsigned long spitfire_get_sfar(void) ...@@ -86,7 +86,7 @@ extern __inline__ unsigned long spitfire_get_sfar(void)
return ret; return ret;
} }
extern __inline__ void spitfire_put_isfsr(unsigned long sfsr) static __inline__ void spitfire_put_isfsr(unsigned long sfsr)
{ {
__asm__ __volatile__("stxa %0, [%1] %2\n\t" __asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync" "membar #Sync"
...@@ -94,7 +94,7 @@ extern __inline__ void spitfire_put_isfsr(unsigned long sfsr) ...@@ -94,7 +94,7 @@ extern __inline__ void spitfire_put_isfsr(unsigned long sfsr)
: "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_IMMU)); : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_IMMU));
} }
extern __inline__ void spitfire_put_dsfsr(unsigned long sfsr) static __inline__ void spitfire_put_dsfsr(unsigned long sfsr)
{ {
__asm__ __volatile__("stxa %0, [%1] %2\n\t" __asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync" "membar #Sync"
...@@ -102,7 +102,7 @@ extern __inline__ void spitfire_put_dsfsr(unsigned long sfsr) ...@@ -102,7 +102,7 @@ extern __inline__ void spitfire_put_dsfsr(unsigned long sfsr)
: "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_DMMU)); : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_DMMU));
} }
extern __inline__ unsigned long spitfire_get_primary_context(void) static __inline__ unsigned long spitfire_get_primary_context(void)
{ {
unsigned long ctx; unsigned long ctx;
...@@ -112,7 +112,7 @@ extern __inline__ unsigned long spitfire_get_primary_context(void) ...@@ -112,7 +112,7 @@ extern __inline__ unsigned long spitfire_get_primary_context(void)
return ctx; return ctx;
} }
extern __inline__ void spitfire_set_primary_context(unsigned long ctx) static __inline__ void spitfire_set_primary_context(unsigned long ctx)
{ {
__asm__ __volatile__("stxa %0, [%1] %2\n\t" __asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync" "membar #Sync"
...@@ -122,7 +122,7 @@ extern __inline__ void spitfire_set_primary_context(unsigned long ctx) ...@@ -122,7 +122,7 @@ extern __inline__ void spitfire_set_primary_context(unsigned long ctx)
__asm__ __volatile__ ("membar #Sync" : : : "memory"); __asm__ __volatile__ ("membar #Sync" : : : "memory");
} }
extern __inline__ unsigned long spitfire_get_secondary_context(void) static __inline__ unsigned long spitfire_get_secondary_context(void)
{ {
unsigned long ctx; unsigned long ctx;
...@@ -132,7 +132,7 @@ extern __inline__ unsigned long spitfire_get_secondary_context(void) ...@@ -132,7 +132,7 @@ extern __inline__ unsigned long spitfire_get_secondary_context(void)
return ctx; return ctx;
} }
extern __inline__ void spitfire_set_secondary_context(unsigned long ctx) static __inline__ void spitfire_set_secondary_context(unsigned long ctx)
{ {
__asm__ __volatile__("stxa %0, [%1] %2\n\t" __asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync" "membar #Sync"
...@@ -145,7 +145,7 @@ extern __inline__ void spitfire_set_secondary_context(unsigned long ctx) ...@@ -145,7 +145,7 @@ extern __inline__ void spitfire_set_secondary_context(unsigned long ctx)
/* The data cache is write through, so this just invalidates the /* The data cache is write through, so this just invalidates the
* specified line. * specified line.
*/ */
extern __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag) static __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
{ {
__asm__ __volatile__("stxa %0, [%1] %2\n\t" __asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync" "membar #Sync"
...@@ -160,7 +160,7 @@ extern __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long ...@@ -160,7 +160,7 @@ extern __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long
* a flush instruction (to any address) is sufficient to handle * a flush instruction (to any address) is sufficient to handle
* this issue after the line is invalidated. * this issue after the line is invalidated.
*/ */
extern __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long tag) static __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
{ {
__asm__ __volatile__("stxa %0, [%1] %2\n\t" __asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync" "membar #Sync"
...@@ -168,7 +168,7 @@ extern __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long ...@@ -168,7 +168,7 @@ extern __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long
: "r" (tag), "r" (addr), "i" (ASI_IC_TAG)); : "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
} }
extern __inline__ unsigned long spitfire_get_dtlb_data(int entry) static __inline__ unsigned long spitfire_get_dtlb_data(int entry)
{ {
unsigned long data; unsigned long data;
...@@ -182,7 +182,7 @@ extern __inline__ unsigned long spitfire_get_dtlb_data(int entry) ...@@ -182,7 +182,7 @@ extern __inline__ unsigned long spitfire_get_dtlb_data(int entry)
return data; return data;
} }
extern __inline__ unsigned long spitfire_get_dtlb_tag(int entry) static __inline__ unsigned long spitfire_get_dtlb_tag(int entry)
{ {
unsigned long tag; unsigned long tag;
...@@ -192,7 +192,7 @@ extern __inline__ unsigned long spitfire_get_dtlb_tag(int entry) ...@@ -192,7 +192,7 @@ extern __inline__ unsigned long spitfire_get_dtlb_tag(int entry)
return tag; return tag;
} }
extern __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data) static __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data)
{ {
__asm__ __volatile__("stxa %0, [%1] %2\n\t" __asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync" "membar #Sync"
...@@ -201,7 +201,7 @@ extern __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data) ...@@ -201,7 +201,7 @@ extern __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data)
"i" (ASI_DTLB_DATA_ACCESS)); "i" (ASI_DTLB_DATA_ACCESS));
} }
extern __inline__ unsigned long spitfire_get_itlb_data(int entry) static __inline__ unsigned long spitfire_get_itlb_data(int entry)
{ {
unsigned long data; unsigned long data;
...@@ -215,7 +215,7 @@ extern __inline__ unsigned long spitfire_get_itlb_data(int entry) ...@@ -215,7 +215,7 @@ extern __inline__ unsigned long spitfire_get_itlb_data(int entry)
return data; return data;
} }
extern __inline__ unsigned long spitfire_get_itlb_tag(int entry) static __inline__ unsigned long spitfire_get_itlb_tag(int entry)
{ {
unsigned long tag; unsigned long tag;
...@@ -225,7 +225,7 @@ extern __inline__ unsigned long spitfire_get_itlb_tag(int entry) ...@@ -225,7 +225,7 @@ extern __inline__ unsigned long spitfire_get_itlb_tag(int entry)
return tag; return tag;
} }
extern __inline__ void spitfire_put_itlb_data(int entry, unsigned long data) static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
{ {
__asm__ __volatile__("stxa %0, [%1] %2\n\t" __asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync" "membar #Sync"
...@@ -237,7 +237,7 @@ extern __inline__ void spitfire_put_itlb_data(int entry, unsigned long data) ...@@ -237,7 +237,7 @@ extern __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
/* Spitfire hardware assisted TLB flushes. */ /* Spitfire hardware assisted TLB flushes. */
/* Context level flushes. */ /* Context level flushes. */
extern __inline__ void spitfire_flush_dtlb_primary_context(void) static __inline__ void spitfire_flush_dtlb_primary_context(void)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync" "membar #Sync"
...@@ -245,7 +245,7 @@ extern __inline__ void spitfire_flush_dtlb_primary_context(void) ...@@ -245,7 +245,7 @@ extern __inline__ void spitfire_flush_dtlb_primary_context(void)
: "r" (0x40), "i" (ASI_DMMU_DEMAP)); : "r" (0x40), "i" (ASI_DMMU_DEMAP));
} }
extern __inline__ void spitfire_flush_itlb_primary_context(void) static __inline__ void spitfire_flush_itlb_primary_context(void)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync" "membar #Sync"
...@@ -253,7 +253,7 @@ extern __inline__ void spitfire_flush_itlb_primary_context(void) ...@@ -253,7 +253,7 @@ extern __inline__ void spitfire_flush_itlb_primary_context(void)
: "r" (0x40), "i" (ASI_IMMU_DEMAP)); : "r" (0x40), "i" (ASI_IMMU_DEMAP));
} }
extern __inline__ void spitfire_flush_dtlb_secondary_context(void) static __inline__ void spitfire_flush_dtlb_secondary_context(void)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync" "membar #Sync"
...@@ -261,7 +261,7 @@ extern __inline__ void spitfire_flush_dtlb_secondary_context(void) ...@@ -261,7 +261,7 @@ extern __inline__ void spitfire_flush_dtlb_secondary_context(void)
: "r" (0x50), "i" (ASI_DMMU_DEMAP)); : "r" (0x50), "i" (ASI_DMMU_DEMAP));
} }
extern __inline__ void spitfire_flush_itlb_secondary_context(void) static __inline__ void spitfire_flush_itlb_secondary_context(void)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync" "membar #Sync"
...@@ -269,7 +269,7 @@ extern __inline__ void spitfire_flush_itlb_secondary_context(void) ...@@ -269,7 +269,7 @@ extern __inline__ void spitfire_flush_itlb_secondary_context(void)
: "r" (0x50), "i" (ASI_IMMU_DEMAP)); : "r" (0x50), "i" (ASI_IMMU_DEMAP));
} }
extern __inline__ void spitfire_flush_dtlb_nucleus_context(void) static __inline__ void spitfire_flush_dtlb_nucleus_context(void)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync" "membar #Sync"
...@@ -277,7 +277,7 @@ extern __inline__ void spitfire_flush_dtlb_nucleus_context(void) ...@@ -277,7 +277,7 @@ extern __inline__ void spitfire_flush_dtlb_nucleus_context(void)
: "r" (0x60), "i" (ASI_DMMU_DEMAP)); : "r" (0x60), "i" (ASI_DMMU_DEMAP));
} }
extern __inline__ void spitfire_flush_itlb_nucleus_context(void) static __inline__ void spitfire_flush_itlb_nucleus_context(void)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync" "membar #Sync"
...@@ -286,7 +286,7 @@ extern __inline__ void spitfire_flush_itlb_nucleus_context(void) ...@@ -286,7 +286,7 @@ extern __inline__ void spitfire_flush_itlb_nucleus_context(void)
} }
/* Page level flushes. */ /* Page level flushes. */
extern __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page) static __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync" "membar #Sync"
...@@ -294,7 +294,7 @@ extern __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page) ...@@ -294,7 +294,7 @@ extern __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page)
: "r" (page), "i" (ASI_DMMU_DEMAP)); : "r" (page), "i" (ASI_DMMU_DEMAP));
} }
extern __inline__ void spitfire_flush_itlb_primary_page(unsigned long page) static __inline__ void spitfire_flush_itlb_primary_page(unsigned long page)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync" "membar #Sync"
...@@ -302,7 +302,7 @@ extern __inline__ void spitfire_flush_itlb_primary_page(unsigned long page) ...@@ -302,7 +302,7 @@ extern __inline__ void spitfire_flush_itlb_primary_page(unsigned long page)
: "r" (page), "i" (ASI_IMMU_DEMAP)); : "r" (page), "i" (ASI_IMMU_DEMAP));
} }
extern __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page) static __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync" "membar #Sync"
...@@ -310,7 +310,7 @@ extern __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page) ...@@ -310,7 +310,7 @@ extern __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page)
: "r" (page | 0x10), "i" (ASI_DMMU_DEMAP)); : "r" (page | 0x10), "i" (ASI_DMMU_DEMAP));
} }
extern __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page) static __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync" "membar #Sync"
...@@ -318,7 +318,7 @@ extern __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page) ...@@ -318,7 +318,7 @@ extern __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page)
: "r" (page | 0x10), "i" (ASI_IMMU_DEMAP)); : "r" (page | 0x10), "i" (ASI_IMMU_DEMAP));
} }
extern __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page) static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync" "membar #Sync"
...@@ -326,7 +326,7 @@ extern __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page) ...@@ -326,7 +326,7 @@ extern __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page)
: "r" (page | 0x20), "i" (ASI_DMMU_DEMAP)); : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
} }
extern __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page) static __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync" "membar #Sync"
...@@ -335,7 +335,7 @@ extern __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page) ...@@ -335,7 +335,7 @@ extern __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page)
} }
/* Cheetah has "all non-locked" tlb flushes. */ /* Cheetah has "all non-locked" tlb flushes. */
extern __inline__ void cheetah_flush_dtlb_all(void) static __inline__ void cheetah_flush_dtlb_all(void)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync" "membar #Sync"
...@@ -343,7 +343,7 @@ extern __inline__ void cheetah_flush_dtlb_all(void) ...@@ -343,7 +343,7 @@ extern __inline__ void cheetah_flush_dtlb_all(void)
: "r" (0x80), "i" (ASI_DMMU_DEMAP)); : "r" (0x80), "i" (ASI_DMMU_DEMAP));
} }
extern __inline__ void cheetah_flush_itlb_all(void) static __inline__ void cheetah_flush_itlb_all(void)
{ {
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t" __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync" "membar #Sync"
...@@ -365,7 +365,7 @@ extern __inline__ void cheetah_flush_itlb_all(void) ...@@ -365,7 +365,7 @@ extern __inline__ void cheetah_flush_itlb_all(void)
* ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
* the problem for me. -DaveM * the problem for me. -DaveM
*/ */
extern __inline__ unsigned long cheetah_get_ldtlb_data(int entry) static __inline__ unsigned long cheetah_get_ldtlb_data(int entry)
{ {
unsigned long data; unsigned long data;
...@@ -378,7 +378,7 @@ extern __inline__ unsigned long cheetah_get_ldtlb_data(int entry) ...@@ -378,7 +378,7 @@ extern __inline__ unsigned long cheetah_get_ldtlb_data(int entry)
return data; return data;
} }
extern __inline__ unsigned long cheetah_get_litlb_data(int entry) static __inline__ unsigned long cheetah_get_litlb_data(int entry)
{ {
unsigned long data; unsigned long data;
...@@ -391,7 +391,7 @@ extern __inline__ unsigned long cheetah_get_litlb_data(int entry) ...@@ -391,7 +391,7 @@ extern __inline__ unsigned long cheetah_get_litlb_data(int entry)
return data; return data;
} }
extern __inline__ unsigned long cheetah_get_ldtlb_tag(int entry) static __inline__ unsigned long cheetah_get_ldtlb_tag(int entry)
{ {
unsigned long tag; unsigned long tag;
...@@ -403,7 +403,7 @@ extern __inline__ unsigned long cheetah_get_ldtlb_tag(int entry) ...@@ -403,7 +403,7 @@ extern __inline__ unsigned long cheetah_get_ldtlb_tag(int entry)
return tag; return tag;
} }
extern __inline__ unsigned long cheetah_get_litlb_tag(int entry) static __inline__ unsigned long cheetah_get_litlb_tag(int entry)
{ {
unsigned long tag; unsigned long tag;
...@@ -415,7 +415,7 @@ extern __inline__ unsigned long cheetah_get_litlb_tag(int entry) ...@@ -415,7 +415,7 @@ extern __inline__ unsigned long cheetah_get_litlb_tag(int entry)
return tag; return tag;
} }
extern __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data) static __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data)
{ {
__asm__ __volatile__("stxa %0, [%1] %2\n\t" __asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync" "membar #Sync"
...@@ -425,7 +425,7 @@ extern __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data) ...@@ -425,7 +425,7 @@ extern __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data)
"i" (ASI_DTLB_DATA_ACCESS)); "i" (ASI_DTLB_DATA_ACCESS));
} }
extern __inline__ void cheetah_put_litlb_data(int entry, unsigned long data) static __inline__ void cheetah_put_litlb_data(int entry, unsigned long data)
{ {
__asm__ __volatile__("stxa %0, [%1] %2\n\t" __asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync" "membar #Sync"
...@@ -435,7 +435,7 @@ extern __inline__ void cheetah_put_litlb_data(int entry, unsigned long data) ...@@ -435,7 +435,7 @@ extern __inline__ void cheetah_put_litlb_data(int entry, unsigned long data)
"i" (ASI_ITLB_DATA_ACCESS)); "i" (ASI_ITLB_DATA_ACCESS));
} }
extern __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb) static __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb)
{ {
unsigned long data; unsigned long data;
...@@ -447,7 +447,7 @@ extern __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb) ...@@ -447,7 +447,7 @@ extern __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb)
return data; return data;
} }
extern __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb) static __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
{ {
unsigned long tag; unsigned long tag;
...@@ -457,7 +457,7 @@ extern __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb) ...@@ -457,7 +457,7 @@ extern __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
return tag; return tag;
} }
extern __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb) static __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
{ {
__asm__ __volatile__("stxa %0, [%1] %2\n\t" __asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync" "membar #Sync"
...@@ -467,7 +467,7 @@ extern __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int ...@@ -467,7 +467,7 @@ extern __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int
"i" (ASI_DTLB_DATA_ACCESS)); "i" (ASI_DTLB_DATA_ACCESS));
} }
extern __inline__ unsigned long cheetah_get_itlb_data(int entry) static __inline__ unsigned long cheetah_get_itlb_data(int entry)
{ {
unsigned long data; unsigned long data;
...@@ -480,7 +480,7 @@ extern __inline__ unsigned long cheetah_get_itlb_data(int entry) ...@@ -480,7 +480,7 @@ extern __inline__ unsigned long cheetah_get_itlb_data(int entry)
return data; return data;
} }
extern __inline__ unsigned long cheetah_get_itlb_tag(int entry) static __inline__ unsigned long cheetah_get_itlb_tag(int entry)
{ {
unsigned long tag; unsigned long tag;
...@@ -490,7 +490,7 @@ extern __inline__ unsigned long cheetah_get_itlb_tag(int entry) ...@@ -490,7 +490,7 @@ extern __inline__ unsigned long cheetah_get_itlb_tag(int entry)
return tag; return tag;
} }
extern __inline__ void cheetah_put_itlb_data(int entry, unsigned long data) static __inline__ void cheetah_put_itlb_data(int entry, unsigned long data)
{ {
__asm__ __volatile__("stxa %0, [%1] %2\n\t" __asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync" "membar #Sync"
......
include/asm-sparc64/system.h
View file @ d672d0b0
...@@ -217,7 +217,7 @@ do { if (test_thread_flag(TIF_PERFCTR)) { \ ...@@ -217,7 +217,7 @@ do { if (test_thread_flag(TIF_PERFCTR)) { \
} \ } \
} while(0) } while(0)
extern __inline__ unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val) static __inline__ unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
{ {
__asm__ __volatile__( __asm__ __volatile__(
" mov %0, %%g5\n" " mov %0, %%g5\n"
...@@ -233,7 +233,7 @@ extern __inline__ unsigned long xchg32(__volatile__ unsigned int *m, unsigned in ...@@ -233,7 +233,7 @@ extern __inline__ unsigned long xchg32(__volatile__ unsigned int *m, unsigned in
return val; return val;
} }
extern __inline__ unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val) static __inline__ unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
{ {
__asm__ __volatile__( __asm__ __volatile__(
" mov %0, %%g5\n" " mov %0, %%g5\n"
...@@ -277,7 +277,7 @@ extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noret ...@@ -277,7 +277,7 @@ extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noret
#define __HAVE_ARCH_CMPXCHG 1 #define __HAVE_ARCH_CMPXCHG 1
extern __inline__ unsigned long static __inline__ unsigned long
__cmpxchg_u32(volatile int *m, int old, int new) __cmpxchg_u32(volatile int *m, int old, int new)
{ {
__asm__ __volatile__("cas [%2], %3, %0\n\t" __asm__ __volatile__("cas [%2], %3, %0\n\t"
...@@ -289,7 +289,7 @@ __cmpxchg_u32(volatile int *m, int old, int new) ...@@ -289,7 +289,7 @@ __cmpxchg_u32(volatile int *m, int old, int new)
return new; return new;
} }
extern __inline__ unsigned long static __inline__ unsigned long
__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new) __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
{ {
__asm__ __volatile__("casx [%2], %3, %0\n\t" __asm__ __volatile__("casx [%2], %3, %0\n\t"
......
include/asm-sparc64/uaccess.h
View file @ d672d0b0
...@@ -52,7 +52,7 @@ do { \ ...@@ -52,7 +52,7 @@ do { \
#define __access_ok(addr,size) 1 #define __access_ok(addr,size) 1
#define access_ok(type,addr,size) 1 #define access_ok(type,addr,size) 1
extern inline int verify_area(int type, const void * addr, unsigned long size) static inline int verify_area(int type, const void * addr, unsigned long size)
{ {
return 0; return 0;
} }
...@@ -270,7 +270,7 @@ extern __kernel_size_t __copy_in_user(void *to, const void *from, ...@@ -270,7 +270,7 @@ extern __kernel_size_t __copy_in_user(void *to, const void *from,
__copy_in_user((void *)(to), \ __copy_in_user((void *)(to), \
(void *) (from), (__kernel_size_t)(n)) (void *) (from), (__kernel_size_t)(n))
extern __inline__ __kernel_size_t __clear_user(void *addr, __kernel_size_t size) static __inline__ __kernel_size_t __clear_user(void *addr, __kernel_size_t size)
{ {
extern __kernel_size_t __bzero_noasi(void *addr, __kernel_size_t size); extern __kernel_size_t __bzero_noasi(void *addr, __kernel_size_t size);
......
include/asm-sparc64/upa.h
View file @ d672d0b0
...@@ -25,7 +25,7 @@ ...@@ -25,7 +25,7 @@
/* UPA I/O space accessors */ /* UPA I/O space accessors */
#if defined(__KERNEL__) && !defined(__ASSEMBLY__) #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
extern __inline__ unsigned char _upa_readb(unsigned long addr) static __inline__ unsigned char _upa_readb(unsigned long addr)
{ {
unsigned char ret; unsigned char ret;
...@@ -36,7 +36,7 @@ extern __inline__ unsigned char _upa_readb(unsigned long addr) ...@@ -36,7 +36,7 @@ extern __inline__ unsigned char _upa_readb(unsigned long addr)
return ret; return ret;
} }
extern __inline__ unsigned short _upa_readw(unsigned long addr) static __inline__ unsigned short _upa_readw(unsigned long addr)
{ {
unsigned short ret; unsigned short ret;
...@@ -47,7 +47,7 @@ extern __inline__ unsigned short _upa_readw(unsigned long addr) ...@@ -47,7 +47,7 @@ extern __inline__ unsigned short _upa_readw(unsigned long addr)
return ret; return ret;
} }
extern __inline__ unsigned int _upa_readl(unsigned long addr) static __inline__ unsigned int _upa_readl(unsigned long addr)
{ {
unsigned int ret; unsigned int ret;
...@@ -58,7 +58,7 @@ extern __inline__ unsigned int _upa_readl(unsigned long addr) ...@@ -58,7 +58,7 @@ extern __inline__ unsigned int _upa_readl(unsigned long addr)
return ret; return ret;
} }
extern __inline__ unsigned long _upa_readq(unsigned long addr) static __inline__ unsigned long _upa_readq(unsigned long addr)
{ {
unsigned long ret; unsigned long ret;
...@@ -69,28 +69,28 @@ extern __inline__ unsigned long _upa_readq(unsigned long addr) ...@@ -69,28 +69,28 @@ extern __inline__ unsigned long _upa_readq(unsigned long addr)
return ret; return ret;
} }
extern __inline__ void _upa_writeb(unsigned char b, unsigned long addr) static __inline__ void _upa_writeb(unsigned char b, unsigned long addr)
{ {
__asm__ __volatile__("stba\t%0, [%1] %2\t/* upa_writeb */" __asm__ __volatile__("stba\t%0, [%1] %2\t/* upa_writeb */"
: /* no outputs */ : /* no outputs */
: "r" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); : "r" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
} }
extern __inline__ void _upa_writew(unsigned short w, unsigned long addr) static __inline__ void _upa_writew(unsigned short w, unsigned long addr)
{ {
__asm__ __volatile__("stha\t%0, [%1] %2\t/* upa_writew */" __asm__ __volatile__("stha\t%0, [%1] %2\t/* upa_writew */"
: /* no outputs */ : /* no outputs */
: "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
} }
extern __inline__ void _upa_writel(unsigned int l, unsigned long addr) static __inline__ void _upa_writel(unsigned int l, unsigned long addr)
{ {
__asm__ __volatile__("stwa\t%0, [%1] %2\t/* upa_writel */" __asm__ __volatile__("stwa\t%0, [%1] %2\t/* upa_writel */"
: /* no outputs */ : /* no outputs */
: "r" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); : "r" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
} }
extern __inline__ void _upa_writeq(unsigned long q, unsigned long addr) static __inline__ void _upa_writeq(unsigned long q, unsigned long addr)
{ {
__asm__ __volatile__("stxa\t%0, [%1] %2\t/* upa_writeq */" __asm__ __volatile__("stxa\t%0, [%1] %2\t/* upa_writeq */"
: /* no outputs */ : /* no outputs */
......
include/asm-sparc64/visasm.h
View file @ d672d0b0
...@@ -42,7 +42,7 @@ ...@@ -42,7 +42,7 @@
wr %o5, 0, %fprs; wr %o5, 0, %fprs;
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
extern __inline__ void save_and_clear_fpu(void) { static __inline__ void save_and_clear_fpu(void) {
__asm__ __volatile__ ( __asm__ __volatile__ (
" rd %%fprs, %%o5\n" " rd %%fprs, %%o5\n"
" andcc %%o5, %0, %%g0\n" " andcc %%o5, %0, %%g0\n"
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7