Commit d6838f26 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson

arm64: dts: qcom: sdm845: switch usb_1 phy to use combo usb+dp phy

Change sdm845's usb_1_qmpphy to use combo usb+dp phy bindings, rather
than just usb phy.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220810035424.2796777-2-bjorn.andersson@linaro.org
parent ff02ac62
...@@ -3959,9 +3959,10 @@ usb_2_hsphy: phy@88e3000 { ...@@ -3959,9 +3959,10 @@ usb_2_hsphy: phy@88e3000 {
}; };
usb_1_qmpphy: phy@88e9000 { usb_1_qmpphy: phy@88e9000 {
compatible = "qcom,sdm845-qmp-usb3-phy"; compatible = "qcom,sdm845-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>, reg = <0 0x088e9000 0 0x18c>,
<0 0x088e8000 0 0x10>; <0 0x088e8000 0 0x38>,
<0 0x088ea000 0 0x40>;
status = "disabled"; status = "disabled";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
...@@ -3973,11 +3974,11 @@ usb_1_qmpphy: phy@88e9000 { ...@@ -3973,11 +3974,11 @@ usb_1_qmpphy: phy@88e9000 {
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux"; clock-names = "aux", "cfg_ahb", "ref", "com_aux";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>; <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common"; reset-names = "phy", "common";
usb_1_ssphy: phy@88e9200 { usb_1_ssphy: usb3-phy@88e9200 {
reg = <0 0x088e9200 0 0x128>, reg = <0 0x088e9200 0 0x128>,
<0 0x088e9400 0 0x200>, <0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x218>, <0 0x088e9c00 0 0x218>,
...@@ -3990,6 +3991,16 @@ usb_1_ssphy: phy@88e9200 { ...@@ -3990,6 +3991,16 @@ usb_1_ssphy: phy@88e9200 {
clock-names = "pipe0"; clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src"; clock-output-names = "usb3_phy_pipe_clk_src";
}; };
dp_phy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>,
<0 0x088ea400 0 0x200>,
<0 0x088eaa00 0 0x200>,
<0 0x088ea600 0 0x200>,
<0 0x088ea800 0 0x200>;
#clock-cells = <1>;
#phy-cells = <0>;
};
}; };
usb_2_qmpphy: phy@88eb000 { usb_2_qmpphy: phy@88eb000 {
...@@ -4812,8 +4823,8 @@ dispcc: clock-controller@af00000 { ...@@ -4812,8 +4823,8 @@ dispcc: clock-controller@af00000 {
<&dsi0_phy 1>, <&dsi0_phy 1>,
<&dsi1_phy 0>, <&dsi1_phy 0>,
<&dsi1_phy 1>, <&dsi1_phy 1>,
<0>, <&dp_phy 0>,
<0>; <&dp_phy 1>;
clock-names = "bi_tcxo", clock-names = "bi_tcxo",
"gcc_disp_gpll0_clk_src", "gcc_disp_gpll0_clk_src",
"gcc_disp_gpll0_div_clk_src", "gcc_disp_gpll0_div_clk_src",
......
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