perf vendor events: Add nehalemex counter information

Add counter information necessary for optimizing event grouping the
perf tool.

The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/

The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1
and later patches.
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-26-irogers@google.com

tools/perf/pmu-events/arch/x86/nehalemex/counter.json

+[
+    {
+        "Unit": "core",
+        "CountersNumFixed": "4",
+        "CountersNumGeneric": "4"
+    }
+]
\ No newline at end of file

tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json

 [
     {
         "BriefDescription": "X87 Floating point assists (Precise Event)",
+        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.ALL",
         "PEBS": "1",
@@ -9,6 +10,7 @@
     },
     {
         "BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)",
+        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.INPUT",
         "PEBS": "1",
@@ -17,6 +19,7 @@
     },
     {
         "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
+        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.OUTPUT",
         "PEBS": "1",
@@ -25,6 +28,7 @@
     },
     {
         "BriefDescription": "MMX Uops",
+        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.MMX",
         "SampleAfterValue": "2000000",
@@ -32,6 +36,7 @@
     },
     {
         "BriefDescription": "SSE2 integer Uops",
+        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
         "SampleAfterValue": "2000000",
@@ -39,6 +44,7 @@
     },
     {
         "BriefDescription": "SSE* FP double precision Uops",
+        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
         "SampleAfterValue": "2000000",
@@ -46,6 +52,7 @@
     },
     {
         "BriefDescription": "SSE and SSE2 FP Uops",
+        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP",
         "SampleAfterValue": "2000000",
@@ -53,6 +60,7 @@
     },
     {
         "BriefDescription": "SSE FP packed Uops",
+        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
         "SampleAfterValue": "2000000",
@@ -60,6 +68,7 @@
     },
     {
         "BriefDescription": "SSE FP scalar Uops",
+        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
         "SampleAfterValue": "2000000",
@@ -67,6 +76,7 @@
     },
     {
         "BriefDescription": "SSE* FP single precision Uops",
+        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
         "SampleAfterValue": "2000000",
@@ -74,6 +84,7 @@
     },
     {
         "BriefDescription": "Computational floating-point operations executed",
+        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.X87",
         "SampleAfterValue": "2000000",
@@ -81,6 +92,7 @@
     },
     {
         "BriefDescription": "All Floating Point to and from MMX transitions",
+        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.ANY",
         "SampleAfterValue": "2000000",
@@ -88,6 +100,7 @@
     },
     {
         "BriefDescription": "Transitions from MMX to Floating Point instructions",
+        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.TO_FP",
         "SampleAfterValue": "2000000",
@@ -95,6 +108,7 @@
     },
     {
         "BriefDescription": "Transitions from Floating Point to MMX instructions",
+        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.TO_MMX",
         "SampleAfterValue": "2000000",
@@ -102,6 +116,7 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer pack operations",
+        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACK",
         "SampleAfterValue": "200000",
@@ -109,6 +124,7 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer arithmetic operations",
+        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_ARITH",
         "SampleAfterValue": "200000",
@@ -116,6 +132,7 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer logical operations",
+        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_LOGICAL",
         "SampleAfterValue": "200000",
@@ -123,6 +140,7 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer multiply operations",
+        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_MPY",
         "SampleAfterValue": "200000",
@@ -130,6 +148,7 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer shift operations",
+        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_SHIFT",
         "SampleAfterValue": "200000",
@@ -137,6 +156,7 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer shuffle/move operations",
+        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.SHUFFLE_MOVE",
         "SampleAfterValue": "200000",
@@ -144,6 +164,7 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer unpack operations",
+        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.UNPACK",
         "SampleAfterValue": "200000",
@@ -151,6 +172,7 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit pack operations",
+        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACK",
         "SampleAfterValue": "200000",
@@ -158,6 +180,7 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit arithmetic operations",
+        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_ARITH",
         "SampleAfterValue": "200000",
@@ -165,6 +188,7 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit logical operations",
+        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_LOGICAL",
         "SampleAfterValue": "200000",
@@ -172,6 +196,7 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit packed multiply operations",
+        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_MPY",
         "SampleAfterValue": "200000",
@@ -179,6 +204,7 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit shift operations",
+        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_SHIFT",
         "SampleAfterValue": "200000",
@@ -186,6 +212,7 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit shuffle/move operations",
+        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.SHUFFLE_MOVE",
         "SampleAfterValue": "200000",
@@ -193,6 +220,7 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit unpack operations",
+        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.UNPACK",
         "SampleAfterValue": "200000",

tools/perf/pmu-events/arch/x86/nehalemex/frontend.json

 [
     {
         "BriefDescription": "Instructions decoded",
+        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MACRO_INSTS.DECODED",
         "SampleAfterValue": "2000000",
@@ -8,6 +9,7 @@
     },
     {
         "BriefDescription": "Macro-fused instructions decoded",
+        "Counter": "0,1,2,3",
         "EventCode": "0xA6",
         "EventName": "MACRO_INSTS.FUSIONS_DECODED",
         "SampleAfterValue": "2000000",
@@ -15,6 +17,7 @@
     },
     {
         "BriefDescription": "Two Uop instructions decoded",
+        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "TWO_UOP_INSTS_DECODED",
         "SampleAfterValue": "2000000",

tools/perf/pmu-events/arch/x86/nehalemex/other.json

 [
     {
         "BriefDescription": "ES segment renames",
+        "Counter": "0,1,2,3",
         "EventCode": "0xD5",
         "EventName": "ES_REG_RENAMES",
         "SampleAfterValue": "2000000",
@@ -8,6 +9,7 @@
     },
     {
         "BriefDescription": "I/O transactions",
+        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "IO_TRANSACTIONS",
         "SampleAfterValue": "2000000",
@@ -15,6 +17,7 @@
     },
     {
         "BriefDescription": "L1I instruction fetch stall cycles",
+        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.CYCLES_STALLED",
         "SampleAfterValue": "2000000",
@@ -22,6 +25,7 @@
     },
     {
         "BriefDescription": "L1I instruction fetch hits",
+        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.HITS",
         "SampleAfterValue": "2000000",
@@ -29,6 +33,7 @@
     },
     {
         "BriefDescription": "L1I instruction fetch misses",
+        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.MISSES",
         "SampleAfterValue": "2000000",
@@ -36,6 +41,7 @@
     },
     {
         "BriefDescription": "L1I Instruction fetches",
+        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.READS",
         "SampleAfterValue": "2000000",
@@ -43,6 +49,7 @@
     },
     {
         "BriefDescription": "Large ITLB hit",
+        "Counter": "0,1,2,3",
         "EventCode": "0x82",
         "EventName": "LARGE_ITLB.HIT",
         "SampleAfterValue": "200000",
@@ -50,6 +57,7 @@
     },
     {
         "BriefDescription": "All loads dispatched",
+        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.ANY",
         "SampleAfterValue": "2000000",
@@ -57,6 +65,7 @@
     },
     {
         "BriefDescription": "Loads dispatched from the MOB",
+        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.MOB",
         "SampleAfterValue": "2000000",
@@ -64,6 +73,7 @@
     },
     {
         "BriefDescription": "Loads dispatched that bypass the MOB",
+        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.RS",
         "SampleAfterValue": "2000000",
@@ -71,6 +81,7 @@
     },
     {
         "BriefDescription": "Loads dispatched from stage 305",
+        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.RS_DELAYED",
         "SampleAfterValue": "2000000",
@@ -78,6 +89,7 @@
     },
     {
         "BriefDescription": "False dependencies due to partial address aliasing",
+        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "PARTIAL_ADDRESS_ALIAS",
         "SampleAfterValue": "200000",
@@ -85,6 +97,7 @@
     },
     {
         "BriefDescription": "All Store buffer stall cycles",
+        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "SB_DRAIN.ANY",
         "SampleAfterValue": "200000",
@@ -92,6 +105,7 @@
     },
     {
         "BriefDescription": "Segment rename stall cycles",
+        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "SEG_RENAME_STALLS",
         "SampleAfterValue": "2000000",
@@ -99,6 +113,7 @@
     },
     {
         "BriefDescription": "Thread responded HIT to snoop",
+        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HIT",
         "SampleAfterValue": "100000",
@@ -106,6 +121,7 @@
     },
     {
         "BriefDescription": "Thread responded HITE to snoop",
+        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HITE",
         "SampleAfterValue": "100000",
@@ -113,6 +129,7 @@
     },
     {
         "BriefDescription": "Thread responded HITM to snoop",
+        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HITM",
         "SampleAfterValue": "100000",
@@ -120,6 +137,7 @@
     },
     {
         "BriefDescription": "Super Queue full stall cycles",
+        "Counter": "0,1,2,3",
         "EventCode": "0xF6",
         "EventName": "SQ_FULL_STALL_CYCLES",
         "SampleAfterValue": "2000000",

tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json

 [
     {
         "BriefDescription": "DTLB load misses",
+        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -8,6 +9,7 @@
     },
     {
         "BriefDescription": "DTLB load miss caused by low part of address",
+        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
         "SampleAfterValue": "200000",
@@ -15,6 +17,7 @@
     },
     {
         "BriefDescription": "DTLB second level hit",
+        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "SampleAfterValue": "2000000",
@@ -22,6 +25,7 @@
     },
     {
         "BriefDescription": "DTLB load miss page walks complete",
+        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -29,6 +33,7 @@
     },
     {
         "BriefDescription": "DTLB misses",
+        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -36,6 +41,7 @@
     },
     {
         "BriefDescription": "DTLB first level misses but second level hit",
+        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.STLB_HIT",
         "SampleAfterValue": "200000",
@@ -43,6 +49,7 @@
     },
     {
         "BriefDescription": "DTLB miss page walks",
+        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -50,6 +57,7 @@
     },
     {
         "BriefDescription": "ITLB flushes",
+        "Counter": "0,1,2,3",
         "EventCode": "0xAE",
         "EventName": "ITLB_FLUSH",
         "SampleAfterValue": "2000000",
@@ -57,6 +65,7 @@
     },
     {
         "BriefDescription": "ITLB miss",
+        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -64,6 +73,7 @@
     },
     {
         "BriefDescription": "ITLB miss page walks",
+        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -71,6 +81,7 @@
     },
     {
         "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
+        "Counter": "0,1,2,3",
         "EventCode": "0xC8",
         "EventName": "ITLB_MISS_RETIRED",
         "PEBS": "1",
@@ -79,6 +90,7 @@
     },
     {
         "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
+        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
         "PEBS": "1",
@@ -87,6 +99,7 @@
     },
     {
         "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
+        "Counter": "0,1,2,3",
         "EventCode": "0xC",
         "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
         "PEBS": "1",