Commit d69f9ecb authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Mark Brown

ASoC: SOF: Intel: hda: add 'is_chain_dma_supported' callback

Reuse existing function to get the interface mask and expose it to the
SOF core with a callback - the main user is the IPC4 topology so only
HDaudio platforms provide this callback.
Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: default avatarRander Wang <rander.wang@intel.com>
Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://msgid.link/r/20240213101247.28887-4-peter.ujfalusi@linux.intel.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent ba91d091
...@@ -83,6 +83,7 @@ struct snd_sof_dsp_ops sof_hda_common_ops = { ...@@ -83,6 +83,7 @@ struct snd_sof_dsp_ops sof_hda_common_ops = {
/* DAI drivers */ /* DAI drivers */
.drv = skl_dai, .drv = skl_dai,
.num_drv = SOF_SKL_NUM_DAIS, .num_drv = SOF_SKL_NUM_DAIS,
.is_chain_dma_supported = hda_is_chain_dma_supported,
/* PM */ /* PM */
.suspend = hda_dsp_suspend, .suspend = hda_dsp_suspend,
......
...@@ -46,44 +46,83 @@ ...@@ -46,44 +46,83 @@
#define EXCEPT_MAX_HDR_SIZE 0x400 #define EXCEPT_MAX_HDR_SIZE 0x400
#define HDA_EXT_ROM_STATUS_SIZE 8 #define HDA_EXT_ROM_STATUS_SIZE 8
static u32 hda_get_interface_mask(struct snd_sof_dev *sdev) static void hda_get_interfaces(struct snd_sof_dev *sdev, u32 *interface_mask)
{ {
const struct sof_intel_dsp_desc *chip; const struct sof_intel_dsp_desc *chip;
u32 interface_mask[2] = { 0 };
chip = get_chip_info(sdev->pdata); chip = get_chip_info(sdev->pdata);
switch (chip->hw_ip_version) { switch (chip->hw_ip_version) {
case SOF_INTEL_TANGIER: case SOF_INTEL_TANGIER:
case SOF_INTEL_BAYTRAIL: case SOF_INTEL_BAYTRAIL:
case SOF_INTEL_BROADWELL: case SOF_INTEL_BROADWELL:
interface_mask[0] = BIT(SOF_DAI_INTEL_SSP); interface_mask[SOF_DAI_DSP_ACCESS] = BIT(SOF_DAI_INTEL_SSP);
break; break;
case SOF_INTEL_CAVS_1_5: case SOF_INTEL_CAVS_1_5:
case SOF_INTEL_CAVS_1_5_PLUS: case SOF_INTEL_CAVS_1_5_PLUS:
interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | interface_mask[SOF_DAI_DSP_ACCESS] =
BIT(SOF_DAI_INTEL_HDA); BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | BIT(SOF_DAI_INTEL_HDA);
interface_mask[1] = BIT(SOF_DAI_INTEL_HDA); interface_mask[SOF_DAI_HOST_ACCESS] = BIT(SOF_DAI_INTEL_HDA);
break; break;
case SOF_INTEL_CAVS_1_8: case SOF_INTEL_CAVS_1_8:
case SOF_INTEL_CAVS_2_0: case SOF_INTEL_CAVS_2_0:
case SOF_INTEL_CAVS_2_5: case SOF_INTEL_CAVS_2_5:
case SOF_INTEL_ACE_1_0: case SOF_INTEL_ACE_1_0:
interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | interface_mask[SOF_DAI_DSP_ACCESS] =
BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH); BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) |
interface_mask[1] = BIT(SOF_DAI_INTEL_HDA); BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH);
interface_mask[SOF_DAI_HOST_ACCESS] = BIT(SOF_DAI_INTEL_HDA);
break; break;
case SOF_INTEL_ACE_2_0: case SOF_INTEL_ACE_2_0:
interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | interface_mask[SOF_DAI_DSP_ACCESS] =
BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH); BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) |
interface_mask[1] = interface_mask[0]; /* all interfaces accessible without DSP */ BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH);
/* all interfaces accessible without DSP */
interface_mask[SOF_DAI_HOST_ACCESS] =
interface_mask[SOF_DAI_DSP_ACCESS];
break; break;
default: default:
break; break;
} }
}
static u32 hda_get_interface_mask(struct snd_sof_dev *sdev)
{
u32 interface_mask[SOF_DAI_ACCESS_NUM] = { 0 };
hda_get_interfaces(sdev, interface_mask);
return interface_mask[sdev->dspless_mode_selected]; return interface_mask[sdev->dspless_mode_selected];
} }
bool hda_is_chain_dma_supported(struct snd_sof_dev *sdev, u32 dai_type)
{
u32 interface_mask[SOF_DAI_ACCESS_NUM] = { 0 };
const struct sof_intel_dsp_desc *chip;
if (sdev->dspless_mode_selected)
return false;
hda_get_interfaces(sdev, interface_mask);
if (!(interface_mask[SOF_DAI_DSP_ACCESS] & BIT(dai_type)))
return false;
if (dai_type == SOF_DAI_INTEL_HDA)
return true;
switch (dai_type) {
case SOF_DAI_INTEL_SSP:
case SOF_DAI_INTEL_DMIC:
case SOF_DAI_INTEL_ALH:
chip = get_chip_info(sdev->pdata);
if (chip->hw_ip_version < SOF_INTEL_ACE_2_0)
return false;
return true;
default:
return false;
}
}
#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
/* /*
......
...@@ -573,6 +573,11 @@ struct sof_intel_hda_stream { ...@@ -573,6 +573,11 @@ struct sof_intel_hda_stream {
#define SOF_STREAM_SD_OFFSET_CRST 0x1 #define SOF_STREAM_SD_OFFSET_CRST 0x1
/*
* DAI support
*/
bool hda_is_chain_dma_supported(struct snd_sof_dev *sdev, u32 dai_type);
/* /*
* DSP Core services. * DSP Core services.
*/ */
......
...@@ -157,6 +157,13 @@ struct sof_firmware { ...@@ -157,6 +157,13 @@ struct sof_firmware {
u32 payload_offset; u32 payload_offset;
}; };
enum sof_dai_access {
SOF_DAI_DSP_ACCESS, /* access from DSP only */
SOF_DAI_HOST_ACCESS, /* access from host only */
SOF_DAI_ACCESS_NUM
};
/* /*
* SOF DSP HW abstraction operations. * SOF DSP HW abstraction operations.
* Used to abstract DSP HW architecture and any IO busses between host CPU * Used to abstract DSP HW architecture and any IO busses between host CPU
......
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