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Commit d6e0cbb1 authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher
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drm/amdgpu: implement querying ras error count for mmhub 

get mmhub ea ras error count by accessing EDC_CNT register
Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarGuchun Chen <guchun.chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f0f50dcf
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drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
View file @ d6e0cbb1
...@@ -21,11 +21,13 @@ ...@@ -21,11 +21,13 @@
* *
*/ */
#include "amdgpu.h" #include "amdgpu.h"
#include "amdgpu_ras.h"
#include "mmhub_v1_0.h" #include "mmhub_v1_0.h"
#include "mmhub/mmhub_1_0_offset.h" #include "mmhub/mmhub_1_0_offset.h"
#include "mmhub/mmhub_1_0_sh_mask.h" #include "mmhub/mmhub_1_0_sh_mask.h"
#include "mmhub/mmhub_1_0_default.h" #include "mmhub/mmhub_1_0_default.h"
#include "mmhub/mmhub_9_4_0_offset.h"
#include "vega10_enum.h" #include "vega10_enum.h"
#include "soc15_common.h" #include "soc15_common.h"
...@@ -33,6 +35,9 @@ ...@@ -33,6 +35,9 @@
#define mmDAGB0_CNTL_MISC2_RV 0x008f #define mmDAGB0_CNTL_MISC2_RV 0x008f
#define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
#define EA_EDC_CNT_MASK 0x3
#define EA_EDC_CNT_SHIFT 0x2
u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
{ {
u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
...@@ -557,6 +562,56 @@ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) ...@@ -557,6 +562,56 @@ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev, static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
void *ras_error_status) void *ras_error_status)
{ {
int i;
uint32_t ea0_edc_cnt, ea0_edc_cnt2;
uint32_t ea1_edc_cnt, ea1_edc_cnt2;
struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
/* EDC CNT will be cleared automatically after read */
ea0_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT_VG20);
ea0_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20);
ea1_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT_VG20);
ea1_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20);
/* error count of each error type is recorded by 2 bits,
* ce and ue count in EDC_CNT
*/
for (i = 0; i < 5; i++) {
err_data->ce_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
err_data->ce_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
}
/* successive ue count in EDC_CNT */
for (i = 0; i < 5; i++) {
err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
}
/* ce and ue count in EDC_CNT2 */
for (i = 0; i < 3; i++) {
err_data->ce_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
err_data->ce_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
}
/* successive ue count in EDC_CNT2 */
for (i = 0; i < 6; i++) {
err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
}
} }
const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = { const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
......
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h
View file @ d6e0cbb1
...@@ -21,6 +21,27 @@ ...@@ -21,6 +21,27 @@
#ifndef _mmhub_9_4_0_OFFSET_HEADER #ifndef _mmhub_9_4_0_OFFSET_HEADER
#define _mmhub_9_4_0_OFFSET_HEADER #define _mmhub_9_4_0_OFFSET_HEADER
/* MMEA */
#define mmMMEA0_SDP_ARB_FINAL_VG20 0x01ee
#define mmMMEA0_SDP_ARB_FINAL_VG20_BASE_IDX 0
#define mmMMEA0_EDC_CNT_VG20 0x0206
#define mmMMEA0_EDC_CNT_VG20_BASE_IDX 0
#define mmMMEA0_EDC_CNT2_VG20 0x0207
#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX 0
#define mmMMEA0_EDC_MODE_VG20 0x0210
#define mmMMEA0_EDC_MODE_VG20_BASE_IDX 0
#define mmMMEA0_ERR_STATUS_VG20 0x0211
#define mmMMEA0_ERR_STATUS_VG20_BASE_IDX 0
#define mmMMEA1_SDP_ARB_FINAL_VG20 0x032e
#define mmMMEA1_SDP_ARB_FINAL_VG20_BASE_IDX 0
#define mmMMEA1_EDC_CNT_VG20 0x0346
#define mmMMEA1_EDC_CNT_VG20_BASE_IDX 0
#define mmMMEA1_EDC_CNT2_VG20 0x0347
#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX 0
#define mmMMEA1_EDC_MODE_VG20 0x0350
#define mmMMEA1_EDC_MODE_VG20_BASE_IDX 0
#define mmMMEA1_ERR_STATUS_VG20 0x0351
#define mmMMEA1_ERR_STATUS_VG20_BASE_IDX 0
// addressBlock: mmhub_utcl2_vmsharedpfdec // addressBlock: mmhub_utcl2_vmsharedpfdec
// base address: 0x6a040 // base address: 0x6a040
......
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h
View file @ d6e0cbb1
...@@ -21,6 +21,228 @@ ...@@ -21,6 +21,228 @@
#ifndef _mmhub_9_4_0_SH_MASK_HEADER #ifndef _mmhub_9_4_0_SH_MASK_HEADER
#define _mmhub_9_4_0_SH_MASK_HEADER #define _mmhub_9_4_0_SH_MASK_HEADER
//MMEA0_SDP_ARB_FINAL
#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
//MMEA0_EDC_CNT
#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
//MMEA0_EDC_CNT2
#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10
#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12
#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16
#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
//MMEA0_EDC_MODE
#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11
#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14
#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d
#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f
#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L
#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L
#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L
#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L
//MMEA0_ERR_STATUS
#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd
#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
#define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
//MMEA1_SDP_ARB_FINAL
#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
//MMEA1_EDC_CNT
#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
//MMEA1_EDC_CNT2
#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10
#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12
#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16
#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
//MMEA1_EDC_MODE
#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
#define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11
#define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14
#define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d
#define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f
#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
#define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L
#define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L
#define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L
#define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L
//MMEA1_ERR_STATUS
#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
#define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd
#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
#define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
// addressBlock: mmhub_utcl2_vmsharedpfdec // addressBlock: mmhub_utcl2_vmsharedpfdec
//MC_VM_XGMI_LFB_CNTL //MC_VM_XGMI_LFB_CNTL
......
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