Merge bk://kernel.bkbits.net/davem/net-2.6

into ppc970.osdl.org:/home/torvalds/v2.6/linux

CREDITS

@@ -1308,11 +1308,10 @@ S: USA
 
 N: Benjamin Herrenschmidt
 E: benh@kernel.crashing.org
-E: benh@mipsys.com
-D: Various parts of PPC & PowerMac
-S: 122, boulevard Baille
-S: 13005 Marseille
-S: France
+D: Various parts of PPC/PPC64 & PowerMac
+S: 312/107 Canberra Avenue
+S: Griffith, ACT 2603 
+S: Australia
 
 N: Sebastian Hetze
 E: she@lunetix.de

arch/ppc/kernel/cpu_setup_power4.S

@@ -18,24 +18,37 @@
 #include <asm/offsets.h>
 #include <asm/cache.h>
 
-_GLOBAL(__power4_cpu_preinit)
+_GLOBAL(__970_cpu_preinit)
 	/*
-	 * On the PPC970, we have to turn off real-mode cache inhibit
-	 * early, before we first turn the MMU off.
+	 * Deal only with PPC970 and PPC970FX.
 	 */
 	mfspr	r0,SPRN_PVR
 	srwi	r0,r0,16
-	cmpwi	r0,0x39
+	cmpwi	cr0,r0,0x39
+	cmpwi	cr1,r0,0x3c
+	cror	4*cr0+eq,4*cr0+eq,4*cr1+eq
 	bnelr
 
+	/* Make sure HID4:rm_ci is off before MMU is turned off, that large
+	 * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
+	 * HID5:DCBZ32_ill
+	 */
 	li	r0,0
+	mfspr	r11,SPRN_HID4
+	rldimi	r11,r0,40,23	/* clear bit 23 (rm_ci) */
+	rldimi	r11,r0,2,61	/* clear bit 61 (lg_pg_en) */
 	sync
-	mtspr	SPRN_HID4,r0
+	mtspr	SPRN_HID4,r11
 	isync
 	sync
-	mtspr	SPRN_HID5,r0
+	mfspr	r11,SPRN_HID5
+	rldimi	r11,r0,6,56	/* clear bits 56 & 57 (DCBZ*) */
+	sync
+	mtspr	SPRN_HID5,r11
 	isync
+	sync
 
+	/* Setup some basic HID1 features */
 	mfspr	r0,SPRN_HID1
 	li	r11,0x1200		/* enable i-fetch cacheability */
 	sldi	r11,r11,44		/* and prefetch */
@@ -43,6 +56,8 @@ _GLOBAL(__power4_cpu_preinit)
 	mtspr	SPRN_HID1,r0
 	mtspr	SPRN_HID1,r0
 	isync
+
+	/* Clear HIOR */
 	li	r0,0
 	sync
 	mtspr	SPRN_HIOR,0		/* Clear interrupt prefix */

arch/ppc/kernel/cputable.c

@@ -323,6 +323,17 @@ struct cpu_spec	cpu_specs[] = {
 	32, 32,
 	__setup_cpu_745x
     },
+    {	/* 7447A */
+    	0xffff0000, 0x80030000, "7447A",
+	CPU_FTR_COMMON |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+	CPU_FTR_HAS_HIGH_BATS,
+	COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+	32, 32,
+	__setup_cpu_745x
+    },
     {	/* 82xx (8240, 8245, 8260 are all 603e cores) */
 	0x7fff0000, 0x00810000, "82xx",
 	CPU_FTR_COMMON |

arch/ppc/kernel/head.S

@@ -153,7 +153,7 @@ __start:
  * like real mode cache inhibit or exception base
  */
 #ifdef CONFIG_POWER4
-	bl	__power4_cpu_preinit
+	bl	__970_cpu_preinit
 #endif /* CONFIG_POWER4 */
 
 #ifdef CONFIG_APUS

arch/ppc/platforms/pmac_feature.c

@@ -578,7 +578,6 @@ heathrow_sleep(struct macio_chip* macio, int secondary)
 
 	/* Let things settle */
 	(void)MACIO_IN32(HEATHROW_FCR);
-	mdelay(1);
 }
 
 static void __pmac
@@ -2102,7 +2101,7 @@ static struct pmac_mb_def pmac_mb_defs[] __pmacdata = {
 		0,
 	},
 	{	"PowerMac3,6",			"PowerMac G4 Windtunnel",
-		PMAC_TYPE_WINDTUNNEL,		rackmac_features,
+		PMAC_TYPE_WINDTUNNEL,		core99_features,
 		0,
 	},
 	{	"PowerBook5,1",			"PowerBook G4 17\"",
@@ -2129,6 +2128,10 @@ static struct pmac_mb_def pmac_mb_defs[] __pmacdata = {
 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
 		PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
 	},
+	{	"PowerBook6,5",			"iBook G4",
+		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
+		PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
+	},
 #else /* CONFIG_POWER4 */
 	{	"PowerMac7,2",			"PowerMac G5",
 		PMAC_TYPE_POWERMAC_G5,		g5_features,

arch/ppc64/kernel/cpu_setup_power4.S

@@ -18,31 +18,53 @@
 #include <asm/offsets.h>
 #include <asm/cache.h>
 
-_GLOBAL(__power4_cpu_preinit)
+_GLOBAL(__970_cpu_preinit)
 	/*
-	 * On the PPC970, we have to turn off real-mode cache inhibit
-	 * early, before we first turn the MMU off.
+	 * Do nothing if not running in HV mode
+	 */
+	mfmsr	r0
+	rldicl.	r0,r0,4,63
+	beqlr
+
+	/*
+	 * Deal only with PPC970 and PPC970FX.
 	 */
 	mfspr	r0,SPRN_PVR
 	srwi	r0,r0,16
-	cmpwi	r0,0x39
+	cmpwi	cr0,r0,0x39
+	cmpwi	cr1,r0,0x3c
+	cror	4*cr0+eq,4*cr0+eq,4*cr1+eq
 	bnelr
 
+	/* Make sure HID4:rm_ci is off before MMU is turned off, that large
+	 * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
+	 * HID5:DCBZ32_ill
+	 */
 	li	r0,0
+	mfspr	r3,SPRN_HID4
+	rldimi	r3,r0,40,23	/* clear bit 23 (rm_ci) */
+	rldimi	r3,r0,2,61	/* clear bit 61 (lg_pg_en) */
 	sync
-	mtspr	SPRN_HID4,r0
+	mtspr	SPRN_HID4,r3
 	isync
 	sync
-	mtspr	SPRN_HID5,r0
+	mfspr	r3,SPRN_HID5
+	rldimi	r3,r0,6,56	/* clear bits 56 & 57 (DCBZ*) */
+	sync
+	mtspr	SPRN_HID5,r3
 	isync
+	sync
 
+	/* Setup some basic HID1 features */
 	mfspr	r0,SPRN_HID1
-	li	r11,0x1200		/* enable i-fetch cacheability */
-	sldi	r11,r11,44		/* and prefetch */
-	or	r0,r0,r11
+	li	r3,0x1200		/* enable i-fetch cacheability */
+	sldi	r3,r3,44		/* and prefetch */
+	or	r0,r0,r3
 	mtspr	SPRN_HID1,r0
 	mtspr	SPRN_HID1,r0
 	isync
+
+	/* Clear HIOR */
 	li	r0,0
 	sync
 	mtspr	SPRN_HIOR,0		/* Clear interrupt prefix */

arch/ppc64/kernel/head.S

@@ -1469,7 +1469,7 @@ _GLOBAL(__start_initialization_pSeries)
 	mr	r23,r3			/* Save phys address we are running at */
 
 	/* Setup some critical 970 SPRs before switching MMU off */
-	bl	.__power4_cpu_preinit
+	bl	.__970_cpu_preinit
 
 	li	r24,0			/* cpu # */
 

include/asm-ppc/dma-mapping.h

@@ -184,4 +184,10 @@ static inline void dma_cache_sync(void *vaddr, size_t size,
 {
 	consistent_sync(vaddr, size, (int)direction);
 }
+
+static inline int dma_mapping_error(dma_addr_t dma_addr)
+{
+	return 0;
+}
+
 #endif				/* __ASM_PPC_DMA_MAPPING_H */

include/asm-ppc/pci.h

@@ -290,6 +290,11 @@ pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr,
 	/* Nothing to do. */
 }
 
+static inline int pci_dma_mapping_error(dma_addr_t dma_addr)
+{
+	return 0;
+}
+
 /* Return the index of the PCI controller for device PDEV. */
 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index