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Commit d7805757 authored by Ansuel Smith's avatar Ansuel Smith Committed by David S. Miller
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net: dsa: qca8k: handle error with qca8k_write operation 

qca8k_write can fail. Rework any user to handle error values and
correctly return.
Signed-off-by: default avatarAnsuel Smith <ansuelsmth@gmail.com>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 028f5f8e
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Showing with 67 additions and 35 deletions
drivers/net/dsa/qca8k.c
View file @ d7805757
...@@ -168,7 +168,7 @@ qca8k_read(struct qca8k_priv *priv, u32 reg) ...@@ -168,7 +168,7 @@ qca8k_read(struct qca8k_priv *priv, u32 reg)
return val; return val;
} }
static void static int
qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
{ {
struct mii_bus *bus = priv->bus; struct mii_bus *bus = priv->bus;
...@@ -187,6 +187,7 @@ qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) ...@@ -187,6 +187,7 @@ qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
exit: exit:
mutex_unlock(&bus->mdio_lock); mutex_unlock(&bus->mdio_lock);
return ret;
} }
static u32 static u32
...@@ -247,9 +248,7 @@ qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val) ...@@ -247,9 +248,7 @@ qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
{ {
struct qca8k_priv *priv = (struct qca8k_priv *)ctx; struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
qca8k_write(priv, reg, val); return qca8k_write(priv, reg, val);
return 0;
} }
static const struct regmap_range qca8k_readable_ranges[] = { static const struct regmap_range qca8k_readable_ranges[] = {
...@@ -367,6 +366,7 @@ static int ...@@ -367,6 +366,7 @@ static int
qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
{ {
u32 reg; u32 reg;
int ret;
/* Set the command and FDB index */ /* Set the command and FDB index */
reg = QCA8K_ATU_FUNC_BUSY; reg = QCA8K_ATU_FUNC_BUSY;
...@@ -377,7 +377,9 @@ qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) ...@@ -377,7 +377,9 @@ qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
} }
/* Write the function register triggering the table access */ /* Write the function register triggering the table access */
qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg); ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
if (ret)
return ret;
/* wait for completion */ /* wait for completion */
if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY)) if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))
...@@ -447,6 +449,7 @@ static int ...@@ -447,6 +449,7 @@ static int
qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid) qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
{ {
u32 reg; u32 reg;
int ret;
/* Set the command and VLAN index */ /* Set the command and VLAN index */
reg = QCA8K_VTU_FUNC1_BUSY; reg = QCA8K_VTU_FUNC1_BUSY;
...@@ -454,7 +457,9 @@ qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid) ...@@ -454,7 +457,9 @@ qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
reg |= vid << QCA8K_VTU_FUNC1_VID_S; reg |= vid << QCA8K_VTU_FUNC1_VID_S;
/* Write the function register triggering the table access */ /* Write the function register triggering the table access */
qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg); ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
if (ret)
return ret;
/* wait for completion */ /* wait for completion */
if (qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY)) if (qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY))
...@@ -502,7 +507,9 @@ qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged) ...@@ -502,7 +507,9 @@ qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged)
reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG << reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<
QCA8K_VTU_FUNC0_EG_MODE_S(port); QCA8K_VTU_FUNC0_EG_MODE_S(port);
qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
if (ret)
return ret;
ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
out: out:
...@@ -545,7 +552,9 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid) ...@@ -545,7 +552,9 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
if (del) { if (del) {
ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid); ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
} else { } else {
qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
if (ret)
return ret;
ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
} }
...@@ -555,15 +564,20 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid) ...@@ -555,15 +564,20 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
return ret; return ret;
} }
static void static int
qca8k_mib_init(struct qca8k_priv *priv) qca8k_mib_init(struct qca8k_priv *priv)
{ {
int ret;
mutex_lock(&priv->reg_mutex); mutex_lock(&priv->reg_mutex);
qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY); qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
mutex_unlock(&priv->reg_mutex); mutex_unlock(&priv->reg_mutex);
return ret;
} }
static void static void
...@@ -600,6 +614,7 @@ static int ...@@ -600,6 +614,7 @@ static int
qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data)
{ {
u32 phy, val; u32 phy, val;
int ret;
if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
return -EINVAL; return -EINVAL;
...@@ -613,7 +628,9 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) ...@@ -613,7 +628,9 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data)
QCA8K_MDIO_MASTER_REG_ADDR(regnum) | QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
QCA8K_MDIO_MASTER_DATA(data); QCA8K_MDIO_MASTER_DATA(data);
qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
if (ret)
return ret;
return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
QCA8K_MDIO_MASTER_BUSY); QCA8K_MDIO_MASTER_BUSY);
...@@ -623,6 +640,7 @@ static int ...@@ -623,6 +640,7 @@ static int
qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum)
{ {
u32 phy, val; u32 phy, val;
int ret;
if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
return -EINVAL; return -EINVAL;
...@@ -635,7 +653,9 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) ...@@ -635,7 +653,9 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum)
QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
QCA8K_MDIO_MASTER_REG_ADDR(regnum); QCA8K_MDIO_MASTER_REG_ADDR(regnum);
qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
if (ret)
return ret;
if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
QCA8K_MDIO_MASTER_BUSY)) QCA8K_MDIO_MASTER_BUSY))
...@@ -766,12 +786,18 @@ qca8k_setup(struct dsa_switch *ds) ...@@ -766,12 +786,18 @@ qca8k_setup(struct dsa_switch *ds)
QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
/* Enable MIB counters */ /* Enable MIB counters */
qca8k_mib_init(priv); ret = qca8k_mib_init(priv);
if (ret)
dev_warn(priv->dev, "mib init failed");
/* Enable QCA header mode on the cpu port */ /* Enable QCA header mode on the cpu port */
qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT), ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
if (ret) {
dev_err(priv->dev, "failed enabling QCA header mode");
return ret;
}
/* Disable forwarding by default on all ports */ /* Disable forwarding by default on all ports */
for (i = 0; i < QCA8K_NUM_PORTS; i++) for (i = 0; i < QCA8K_NUM_PORTS; i++)
...@@ -783,11 +809,13 @@ qca8k_setup(struct dsa_switch *ds) ...@@ -783,11 +809,13 @@ qca8k_setup(struct dsa_switch *ds)
qca8k_port_set_status(priv, i, 0); qca8k_port_set_status(priv, i, 0);
/* Forward all unknown frames to CPU port for Linux processing */ /* Forward all unknown frames to CPU port for Linux processing */
qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
if (ret)
return ret;
/* Setup connection between CPU port & user ports */ /* Setup connection between CPU port & user ports */
for (i = 0; i < QCA8K_NUM_PORTS; i++) { for (i = 0; i < QCA8K_NUM_PORTS; i++) {
...@@ -815,16 +843,20 @@ qca8k_setup(struct dsa_switch *ds) ...@@ -815,16 +843,20 @@ qca8k_setup(struct dsa_switch *ds)
qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i), qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
0xfff << shift, 0xfff << shift,
QCA8K_PORT_VID_DEF << shift); QCA8K_PORT_VID_DEF << shift);
qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i), ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) | QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF)); QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
if (ret)
return ret;
} }
} }
/* Setup our port MTUs to match power on defaults */ /* Setup our port MTUs to match power on defaults */
for (i = 0; i < QCA8K_NUM_PORTS; i++) for (i = 0; i < QCA8K_NUM_PORTS; i++)
priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;
qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN); ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
if (ret)
dev_warn(priv->dev, "failed setting MTU settings");
/* Flush the FDB table */ /* Flush the FDB table */
qca8k_fdb_flush(priv); qca8k_fdb_flush(priv);
...@@ -1140,8 +1172,8 @@ qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee) ...@@ -1140,8 +1172,8 @@ qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
{ {
struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port); u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
int ret = 0;
u32 reg; u32 reg;
int ret;
mutex_lock(&priv->reg_mutex); mutex_lock(&priv->reg_mutex);
reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL); reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
...@@ -1154,7 +1186,7 @@ qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee) ...@@ -1154,7 +1186,7 @@ qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
reg |= lpi_en; reg |= lpi_en;
else else
reg &= ~lpi_en; reg &= ~lpi_en;
qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
exit: exit:
mutex_unlock(&priv->reg_mutex); mutex_unlock(&priv->reg_mutex);
...@@ -1284,9 +1316,7 @@ qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) ...@@ -1284,9 +1316,7 @@ qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
mtu = priv->port_mtu[i]; mtu = priv->port_mtu[i];
/* Include L2 header / FCS length */ /* Include L2 header / FCS length */
qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN); return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);
return 0;
} }
static int static int
...@@ -1381,7 +1411,7 @@ qca8k_port_vlan_add(struct dsa_switch *ds, int port, ...@@ -1381,7 +1411,7 @@ qca8k_port_vlan_add(struct dsa_switch *ds, int port,
bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
struct qca8k_priv *priv = ds->priv; struct qca8k_priv *priv = ds->priv;
int ret = 0; int ret;
ret = qca8k_vlan_add(priv, port, vlan->vid, untagged); ret = qca8k_vlan_add(priv, port, vlan->vid, untagged);
if (ret) { if (ret) {
...@@ -1394,9 +1424,11 @@ qca8k_port_vlan_add(struct dsa_switch *ds, int port, ...@@ -1394,9 +1424,11 @@ qca8k_port_vlan_add(struct dsa_switch *ds, int port,
qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
0xfff << shift, vlan->vid << shift); 0xfff << shift, vlan->vid << shift);
qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
QCA8K_PORT_VLAN_CVID(vlan->vid) | QCA8K_PORT_VLAN_CVID(vlan->vid) |
QCA8K_PORT_VLAN_SVID(vlan->vid)); QCA8K_PORT_VLAN_SVID(vlan->vid));
if (ret)
return ret;
} }
return 0; return 0;
...@@ -1407,7 +1439,7 @@ qca8k_port_vlan_del(struct dsa_switch *ds, int port, ...@@ -1407,7 +1439,7 @@ qca8k_port_vlan_del(struct dsa_switch *ds, int port,
const struct switchdev_obj_port_vlan *vlan) const struct switchdev_obj_port_vlan *vlan)
{ {
struct qca8k_priv *priv = ds->priv; struct qca8k_priv *priv = ds->priv;
int ret = 0; int ret;
ret = qca8k_vlan_del(priv, port, vlan->vid); ret = qca8k_vlan_del(priv, port, vlan->vid);
if (ret) if (ret)
......
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