Commit d7d3d26f authored by Mike Turquette's avatar Mike Turquette

Merge tag 'for_3.17/samsung-clk' of...

Merge tag 'for_3.17/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next-samsung

Samsung clock patches for 3.17

1) non-critical fixes (without need to push to stable):

d5e136a2 clk: samsung: Register clk provider only after registering its all clocks
305cfab0 clk: samsung: Make of_device_id array const
e9d52956 clk: samsung: exynos5420: Setup clocks before system suspend
f65d5189 clk: samsung: trivial: Correct typo in author's name

2) Exynos CLKOUT driver:

800c9797 clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy
01f7ec26 clk: samsung: exynos4: Add CLKOUT clock hierarchy
1e832e51 clk: samsung: Add driver to control CLKOUT line on Exynos SoCs
d19bb397 ARM: dts: exynos: Update PMU node with CLKOUT related data

3) Clock hierarchy extensions:

17d3f1d2 clk: exynos4: Add PPMU IP block source clocks.
ca5b4029 clk: samsung: register exynos5420 apll/kpll configuration data

4) ARM CLKDOWN functionality enablement for Exynos4 and 3250:

42773b28 clk: samsung: exynos4: Enable ARMCLK down feature
45c5b0a6 clk: samsung: exynos3250: Enable ARMCLK down feature
parents abeab450 f65d5189
......@@ -12,8 +12,38 @@ Properties:
- reg : offset and length of the register set.
- #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
The single specifier cell is used as index to list of clocks
provided by PMU, which is currently:
0 : SoC clock output (CLKOUT pin)
- clock-names : list of clock names for particular CLKOUT mux inputs in
following format:
"clkoutN", where N is a decimal number corresponding to
CLKOUT mux control bits value for given input, e.g.
"clkout0", "clkout7", "clkout15".
- clocks : list of phandles and specifiers to all input clocks listed in
clock-names property.
Example :
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5250-pmu", "syscon";
reg = <0x10040000 0x5000>;
#clock-cells = <1>;
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
"clkout4", "clkout8", "clkout9";
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
<&clock CLK_XUSBXTI>;
};
Example of clock consumer :
usb3503: usb3503@08 {
/* ... */
clock-names = "refclk";
clocks = <&pmu_system_controller 0>;
/* ... */
};
......@@ -31,6 +31,16 @@ aliases {
pinctrl2 = &pinctrl_2;
};
pmu_system_controller: system-controller@10020000 {
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
"clkout4", "clkout8", "clkout9";
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
<&clock CLK_XUSBXTI>;
#clock-cells = <1>;
};
sysram@02020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x20000>;
......
......@@ -139,6 +139,13 @@ pinctrl_3: pinctrl@106E0000 {
pmu_system_controller: system-controller@10020000 {
compatible = "samsung,exynos4212-pmu", "syscon";
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
"clkout4", "clkout8", "clkout9";
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
<&clock CLK_XUSBXTI>;
#clock-cells = <1>;
};
g2d@10800000 {
......
......@@ -191,6 +191,9 @@ pinctrl_3: pinctrl@03860000 {
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5250-pmu", "syscon";
reg = <0x10040000 0x5000>;
clock-names = "clkout16";
clocks = <&clock CLK_FIN_PLL>;
#clock-cells = <1>;
};
sysreg_system_controller: syscon@10050000 {
......
......@@ -724,6 +724,9 @@ gsc_1: video-scaler@13e10000 {
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5420-pmu", "syscon";
reg = <0x10040000 0x5000>;
clock-names = "clkout16";
clocks = <&clock CLK_FIN_PLL>;
#clock-cells = <1>;
};
sysreg_system_controller: syscon@10050000 {
......
......@@ -11,6 +11,7 @@ obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
......
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Tomasz Figa <t.figa@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Clock driver for Exynos clock output
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
#define EXYNOS_CLKOUT_NR_CLKS 1
#define EXYNOS_CLKOUT_PARENTS 32
#define EXYNOS_PMU_DEBUG_REG 0xa00
#define EXYNOS_CLKOUT_DISABLE_SHIFT 0
#define EXYNOS_CLKOUT_MUX_SHIFT 8
#define EXYNOS4_CLKOUT_MUX_MASK 0xf
#define EXYNOS5_CLKOUT_MUX_MASK 0x1f
struct exynos_clkout {
struct clk_gate gate;
struct clk_mux mux;
spinlock_t slock;
struct clk_onecell_data data;
struct clk *clk_table[EXYNOS_CLKOUT_NR_CLKS];
void __iomem *reg;
u32 pmu_debug_save;
};
static struct exynos_clkout *clkout;
static int exynos_clkout_suspend(void)
{
clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);
return 0;
}
static void exynos_clkout_resume(void)
{
writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
}
static struct syscore_ops exynos_clkout_syscore_ops = {
.suspend = exynos_clkout_suspend,
.resume = exynos_clkout_resume,
};
static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask)
{
const char *parent_names[EXYNOS_CLKOUT_PARENTS];
struct clk *parents[EXYNOS_CLKOUT_PARENTS];
int parent_count;
int ret;
int i;
clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
if (!clkout)
return;
spin_lock_init(&clkout->slock);
parent_count = 0;
for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
char name[] = "clkoutXX";
snprintf(name, sizeof(name), "clkout%d", i);
parents[i] = of_clk_get_by_name(node, name);
if (IS_ERR(parents[i])) {
parent_names[i] = "none";
continue;
}
parent_names[i] = __clk_get_name(parents[i]);
parent_count = i + 1;
}
if (!parent_count)
goto free_clkout;
clkout->reg = of_iomap(node, 0);
if (!clkout->reg)
goto clks_put;
clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
clkout->gate.lock = &clkout->slock;
clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
clkout->mux.mask = mux_mask;
clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
clkout->mux.lock = &clkout->slock;
clkout->clk_table[0] = clk_register_composite(NULL, "clkout",
parent_names, parent_count, &clkout->mux.hw,
&clk_mux_ops, NULL, NULL, &clkout->gate.hw,
&clk_gate_ops, CLK_SET_RATE_PARENT
| CLK_SET_RATE_NO_REPARENT);
if (IS_ERR(clkout->clk_table[0]))
goto err_unmap;
clkout->data.clks = clkout->clk_table;
clkout->data.clk_num = EXYNOS_CLKOUT_NR_CLKS;
ret = of_clk_add_provider(node, of_clk_src_onecell_get, &clkout->data);
if (ret)
goto err_clk_unreg;
register_syscore_ops(&exynos_clkout_syscore_ops);
return;
err_clk_unreg:
clk_unregister(clkout->clk_table[0]);
err_unmap:
iounmap(clkout->reg);
clks_put:
for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
if (!IS_ERR(parents[i]))
clk_put(parents[i]);
free_clkout:
kfree(clkout);
pr_err("%s: failed to register clkout clock\n", __func__);
}
static void __init exynos4_clkout_init(struct device_node *node)
{
exynos_clkout_init(node, EXYNOS4_CLKOUT_MUX_MASK);
}
CLK_OF_DECLARE(exynos4210_clkout, "samsung,exynos4210-pmu",
exynos4_clkout_init);
CLK_OF_DECLARE(exynos4212_clkout, "samsung,exynos4212-pmu",
exynos4_clkout_init);
CLK_OF_DECLARE(exynos4412_clkout, "samsung,exynos4412-pmu",
exynos4_clkout_init);
static void __init exynos5_clkout_init(struct device_node *node)
{
exynos_clkout_init(node, EXYNOS5_CLKOUT_MUX_MASK);
}
CLK_OF_DECLARE(exynos5250_clkout, "samsung,exynos5250-pmu",
exynos5_clkout_init);
CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu",
exynos5_clkout_init);
......@@ -87,6 +87,22 @@
#define SRC_CPU 0x14200
#define DIV_CPU0 0x14500
#define DIV_CPU1 0x14504
#define PWR_CTRL1 0x15020
#define PWR_CTRL2 0x15024
/* Below definitions are used for PWR_CTRL settings */
#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
/* list of PLLs to be registered */
enum exynos3250_plls {
......@@ -168,6 +184,8 @@ static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
SRC_CPU,
DIV_CPU0,
DIV_CPU1,
PWR_CTRL1,
PWR_CTRL2,
};
static int exynos3250_clk_suspend(void)
......@@ -748,6 +766,27 @@ static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = {
UPLL_LOCK, UPLL_CON0, NULL),
};
static void __init exynos3_core_down_clock(void)
{
unsigned int tmp;
/*
* Enable arm clock down (in idle) and set arm divider
* ratios in WFI/WFE state.
*/
tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
__raw_writel(tmp, reg_base + PWR_CTRL1);
/*
* Disable the clock up feature on Exynos4x12, in case it was
* enabled by bootloader.
*/
__raw_writel(0x0, reg_base + PWR_CTRL2);
}
static void __init exynos3250_cmu_init(struct device_node *np)
{
struct samsung_clk_provider *ctx;
......@@ -775,6 +814,10 @@ static void __init exynos3250_cmu_init(struct device_node *np)
samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
exynos3_core_down_clock();
exynos3250_clk_sleep_init();
samsung_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
This diff is collapsed.
......@@ -748,7 +748,7 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
static struct of_device_id ext_clk_match[] __initdata = {
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
{ },
};
......@@ -820,6 +820,8 @@ static void __init exynos5250_clk_init(struct device_node *np)
exynos5250_clk_sleep_init();
samsung_clk_of_add_provider(np, ctx);
pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
_get_rate("div_arm2"));
}
......
......@@ -206,6 +206,8 @@ void __init exynos5260_cmu_register_one(struct device_node *np,
if (cmu->clk_regs)
exynos5260_clk_sleep_init(reg_base, cmu->clk_regs,
cmu->nr_clk_regs);
samsung_clk_of_add_provider(np, ctx);
}
......
......@@ -204,6 +204,8 @@ static void __init exynos5410_clk_init(struct device_node *np)
samsung_clk_register_gate(ctx, exynos5410_gate_clks,
ARRAY_SIZE(exynos5410_gate_clks));
samsung_clk_of_add_provider(np, ctx);
pr_debug("Exynos5410: clock setup completed.\n");
}
CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
......@@ -28,6 +28,7 @@
#define GATE_BUS_CPU 0x700
#define GATE_SCLK_CPU 0x800
#define CLKOUT_CMU_CPU 0xa00
#define SRC_MASK_CPERI 0x4300
#define GATE_IP_G2D 0x8800
#define CPLL_LOCK 0x10020
#define DPLL_LOCK 0x10030
......@@ -70,6 +71,8 @@
#define SRC_TOP11 0x10284
#define SRC_TOP12 0x10288
#define SRC_TOP13 0x1028c /* 5800 specific */
#define SRC_MASK_TOP0 0x10300
#define SRC_MASK_TOP1 0x10304
#define SRC_MASK_TOP2 0x10308
#define SRC_MASK_TOP7 0x1031c
#define SRC_MASK_DISP10 0x1032c
......@@ -77,6 +80,7 @@
#define SRC_MASK_FSYS 0x10340
#define SRC_MASK_PERIC0 0x10350
#define SRC_MASK_PERIC1 0x10354
#define SRC_MASK_ISP 0x10370
#define DIV_TOP0 0x10500
#define DIV_TOP1 0x10504
#define DIV_TOP2 0x10508
......@@ -98,6 +102,7 @@
#define DIV2_RATIO0 0x10590
#define DIV4_RATIO 0x105a0
#define GATE_BUS_TOP 0x10700
#define GATE_BUS_DISP1 0x10728
#define GATE_BUS_GEN 0x1073c
#define GATE_BUS_FSYS0 0x10740
#define GATE_BUS_FSYS2 0x10748
......@@ -190,6 +195,10 @@ static unsigned long exynos5x_clk_regs[] __initdata = {
SRC_MASK_FSYS,
SRC_MASK_PERIC0,
SRC_MASK_PERIC1,
SRC_MASK_TOP0,
SRC_MASK_TOP1,
SRC_MASK_MAU,
SRC_MASK_ISP,
SRC_ISP,
DIV_TOP0,
DIV_TOP1,
......@@ -208,6 +217,7 @@ static unsigned long exynos5x_clk_regs[] __initdata = {
SCLK_DIV_ISP1,
DIV2_RATIO0,
DIV4_RATIO,
GATE_BUS_DISP1,
GATE_BUS_TOP,
GATE_BUS_GEN,
GATE_BUS_FSYS0,
......@@ -249,6 +259,22 @@ static unsigned long exynos5800_clk_regs[] __initdata = {
GATE_IP_CAM,
};
static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
{ .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
{ .offset = SRC_MASK_TOP0, .value = 0x11111111, },
{ .offset = SRC_MASK_TOP1, .value = 0x11101111, },
{ .offset = SRC_MASK_TOP2, .value = 0x11111110, },
{ .offset = SRC_MASK_TOP7, .value = 0x00111100, },
{ .offset = SRC_MASK_DISP10, .value = 0x11111110, },
{ .offset = SRC_MASK_MAU, .value = 0x10000000, },
{ .offset = SRC_MASK_FSYS, .value = 0x11111110, },
{ .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
{ .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
{ .offset = SRC_MASK_ISP, .value = 0x11111000, },
{ .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
{ .offset = GATE_IP_PERIC, .value = 0xffffffff, },
};
static int exynos5420_clk_suspend(void)
{
samsung_clk_save(reg_base, exynos5x_save,
......@@ -258,6 +284,9 @@ static int exynos5420_clk_suspend(void)
samsung_clk_save(reg_base, exynos5800_save,
ARRAY_SIZE(exynos5800_clk_regs));
samsung_clk_restore(reg_base, exynos5420_set_clksrc,
ARRAY_SIZE(exynos5420_set_clksrc));
return 0;
}
......@@ -1167,6 +1196,28 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
};
static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = {
PLL_35XX_RATE(2000000000, 250, 3, 0),
PLL_35XX_RATE(1900000000, 475, 6, 0),
PLL_35XX_RATE(1800000000, 225, 3, 0),
PLL_35XX_RATE(1700000000, 425, 6, 0),
PLL_35XX_RATE(1600000000, 200, 3, 0),
PLL_35XX_RATE(1500000000, 250, 4, 0),
PLL_35XX_RATE(1400000000, 175, 3, 0),
PLL_35XX_RATE(1300000000, 325, 6, 0),
PLL_35XX_RATE(1200000000, 200, 2, 1),
PLL_35XX_RATE(1100000000, 275, 3, 1),
PLL_35XX_RATE(1000000000, 250, 3, 1),
PLL_35XX_RATE(900000000, 150, 2, 1),
PLL_35XX_RATE(800000000, 200, 3, 1),
PLL_35XX_RATE(700000000, 175, 3, 1),
PLL_35XX_RATE(600000000, 200, 2, 2),
PLL_35XX_RATE(500000000, 250, 3, 2),
PLL_35XX_RATE(400000000, 200, 3, 2),
PLL_35XX_RATE(300000000, 200, 2, 3),
PLL_35XX_RATE(200000000, 200, 3, 3),
};
static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
[apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
APLL_CON0, NULL),
......@@ -1192,7 +1243,7 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
KPLL_CON0, NULL),
};
static struct of_device_id ext_clk_match[] __initdata = {
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
{ },
};
......@@ -1220,6 +1271,12 @@ static void __init exynos5x_clk_init(struct device_node *np,
samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
ext_clk_match);
if (_get_rate("fin_pll") == 24 * MHZ) {
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
}
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
reg_base);
samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
......@@ -1251,6 +1308,8 @@ static void __init exynos5x_clk_init(struct device_node *np,
}
exynos5420_clk_sleep_init();
samsung_clk_of_add_provider(np, ctx);
}
static void __init exynos5420_clk_init(struct device_node *np)
......
......@@ -84,7 +84,7 @@ static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
};
static struct of_device_id ext_clk_match[] __initdata = {
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = "samsung,clock-xtal", .data = (void *)0, },
{},
};
......@@ -123,6 +123,8 @@ static void __init exynos5440_clk_init(struct device_node *np)
samsung_clk_register_gate(ctx, exynos5440_gate_clks,
ARRAY_SIZE(exynos5440_gate_clks));
samsung_clk_of_add_provider(np, ctx);
pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
pr_info("exynos5440 clock initialization complete\n");
}
......
......@@ -466,6 +466,8 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
}
s3c2410_clk_sleep_init();
samsung_clk_of_add_provider(np, ctx);
}
static void __init s3c2410_clk_init(struct device_node *np)
......
......@@ -265,6 +265,8 @@ void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
ARRAY_SIZE(s3c2412_aliases));
s3c2412_clk_sleep_init();
samsung_clk_of_add_provider(np, ctx);
}
static void __init s3c2412_clk_init(struct device_node *np)
......
......@@ -445,6 +445,8 @@ void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
}
s3c2443_clk_sleep_init();
samsung_clk_of_add_provider(np, ctx);
}
static void __init s3c2416_clk_init(struct device_node *np)
......
......@@ -518,6 +518,8 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
ARRAY_SIZE(s3c64xx_clock_aliases));
s3c64xx_clk_sleep_init();
samsung_clk_of_add_provider(np, ctx);
pr_info("%s clocks: apll = %lu, mpll = %lu\n"
"\tepll = %lu, arm_clk = %lu\n",
is_s3c6400 ? "S3C6400" : "S3C6410",
......
......@@ -53,7 +53,6 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
{
struct samsung_clk_provider *ctx;
struct clk **clk_table;
int ret;
int i;
ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
......@@ -72,15 +71,17 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
ctx->clk_data.clk_num = nr_clks;
spin_lock_init(&ctx->lock);
if (!np)
return ctx;
}
ret = of_clk_add_provider(np, of_clk_src_onecell_get,
&ctx->clk_data);
if (ret)
panic("could not register clock provide\n");
return ctx;
void __init samsung_clk_of_add_provider(struct device_node *np,
struct samsung_clk_provider *ctx)
{
if (np) {
if (of_clk_add_provider(np, of_clk_src_onecell_get,
&ctx->clk_data))
panic("could not register clk provider\n");
}
}
/* add a clock instance to the clock lookup table used for dt based lookup */
......@@ -284,7 +285,7 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
struct samsung_fixed_rate_clock *fixed_rate_clk,
unsigned int nr_fixed_rate_clk,
struct of_device_id *clk_matches)
const struct of_device_id *clk_matches)
{
const struct of_device_id *match;
struct device_node *clk_np;
......
......@@ -327,11 +327,13 @@ struct samsung_pll_clock {
extern struct samsung_clk_provider *__init samsung_clk_init(
struct device_node *np, void __iomem *base,
unsigned long nr_clks);
extern void __init samsung_clk_of_add_provider(struct device_node *np,
struct samsung_clk_provider *ctx);
extern void __init samsung_clk_of_register_fixed_ext(
struct samsung_clk_provider *ctx,
struct samsung_fixed_rate_clock *fixed_rate_clk,
unsigned int nr_fixed_rate_clk,
struct of_device_id *clk_matches);
const struct of_device_id *clk_matches);
extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
struct clk *clk, unsigned int id);
......
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Haja <a.hajda@samsung.com>
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -34,6 +34,11 @@
#define CLK_MOUT_CORE 19
#define CLK_MOUT_APLL 20
#define CLK_SCLK_HDMIPHY 22
#define CLK_OUT_DMC 23
#define CLK_OUT_TOP 24
#define CLK_OUT_LEFTBUS 25
#define CLK_OUT_RIGHTBUS 26
#define CLK_OUT_CPU 27
/* gate for special clocks (sclk) */
#define CLK_SCLK_FIMC0 128
......@@ -230,6 +235,24 @@
#define CLK_MOUT_G3D 394
#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
/* gate clocks - ppmu */
#define CLK_PPMULEFT 400
#define CLK_PPMURIGHT 401
#define CLK_PPMUCAMIF 402
#define CLK_PPMUTV 403
#define CLK_PPMUMFC_L 404
#define CLK_PPMUMFC_R 405
#define CLK_PPMUG3D 406
#define CLK_PPMUIMAGE 407
#define CLK_PPMULCD0 408
#define CLK_PPMULCD1 409 /* Exynos4210 only */
#define CLK_PPMUFILE 410
#define CLK_PPMUGPS 411
#define CLK_PPMUDMC0 412
#define CLK_PPMUDMC1 413
#define CLK_PPMUCPU 414
#define CLK_PPMUACP 415
/* div clocks */
#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
#define CLK_DIV_ISP1 451 /* Exynos4x12 only */
......
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Haja <a.hajda@samsung.com>
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Haja <a.hajda@samsung.com>
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Andrzej Haja <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
* Author: Andrzej Hajda <a.hajda@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......
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