Commit d8027093 authored by Chris Wilson's avatar Chris Wilson

drm/i915: Split GEM resetting into 3 phases

Currently we do a reset prepare/finish around the call to reset the GPU,
but it looks like we need a later stage after the hw has been
reinitialised to allow GEM to restart itself. Start by splitting the 2
GEM phases into 3:

  prepare - before the reset, check if GEM recovered, then stop GEM

  reset - after the reset, update GEM bookkeeping

  finish - after the re-initialisation following the reset, restart GEM
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170208143033.11651-2-chris@chris-wilson.co.uk
parent 20a8a74a
...@@ -1836,7 +1836,7 @@ void i915_reset(struct drm_i915_private *dev_priv) ...@@ -1836,7 +1836,7 @@ void i915_reset(struct drm_i915_private *dev_priv)
goto error; goto error;
} }
i915_gem_reset_finish(dev_priv); i915_gem_reset(dev_priv);
intel_overlay_reset(dev_priv); intel_overlay_reset(dev_priv);
/* Ok, now get things going again... */ /* Ok, now get things going again... */
...@@ -1859,6 +1859,7 @@ void i915_reset(struct drm_i915_private *dev_priv) ...@@ -1859,6 +1859,7 @@ void i915_reset(struct drm_i915_private *dev_priv)
goto error; goto error;
} }
i915_gem_reset_finish(dev_priv);
i915_queue_hangcheck(dev_priv); i915_queue_hangcheck(dev_priv);
wakeup: wakeup:
......
...@@ -3362,6 +3362,7 @@ static inline u32 i915_reset_count(struct i915_gpu_error *error) ...@@ -3362,6 +3362,7 @@ static inline u32 i915_reset_count(struct i915_gpu_error *error)
} }
int i915_gem_reset_prepare(struct drm_i915_private *dev_priv); int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
void i915_gem_reset(struct drm_i915_private *dev_priv);
void i915_gem_reset_finish(struct drm_i915_private *dev_priv); void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
void i915_gem_set_wedged(struct drm_i915_private *dev_priv); void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
......
...@@ -2758,7 +2758,7 @@ static void i915_gem_reset_engine(struct intel_engine_cs *engine) ...@@ -2758,7 +2758,7 @@ static void i915_gem_reset_engine(struct intel_engine_cs *engine)
engine->reset_hw(engine, request); engine->reset_hw(engine, request);
} }
void i915_gem_reset_finish(struct drm_i915_private *dev_priv) void i915_gem_reset(struct drm_i915_private *dev_priv)
{ {
struct intel_engine_cs *engine; struct intel_engine_cs *engine;
enum intel_engine_id id; enum intel_engine_id id;
...@@ -2780,6 +2780,11 @@ void i915_gem_reset_finish(struct drm_i915_private *dev_priv) ...@@ -2780,6 +2780,11 @@ void i915_gem_reset_finish(struct drm_i915_private *dev_priv)
} }
} }
void i915_gem_reset_finish(struct drm_i915_private *dev_priv)
{
lockdep_assert_held(&dev_priv->drm.struct_mutex);
}
static void nop_submit_request(struct drm_i915_gem_request *request) static void nop_submit_request(struct drm_i915_gem_request *request)
{ {
dma_fence_set_error(&request->fence, -EIO); dma_fence_set_error(&request->fence, -EIO);
......
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