Commit d86d46af authored by Boris Brezillon's avatar Boris Brezillon Committed by Stephen Boyd

clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock

The VEC clock requires needs to be set at exactly 108MHz. Allow rate
change propagation on PLLH_AUX to match this requirement wihtout
impacting other IPs (PLLH is currently only used by the HDMI encoder,
which cannot be enabled when the VEC encoder is enabled).
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: default avatarEric Anholt <eric@anholt.net>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 155e8b3b
...@@ -1861,7 +1861,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { ...@@ -1861,7 +1861,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
.ctl_reg = CM_VECCTL, .ctl_reg = CM_VECCTL,
.div_reg = CM_VECDIV, .div_reg = CM_VECDIV,
.int_bits = 4, .int_bits = 4,
.frac_bits = 0), .frac_bits = 0,
/*
* Allow rate change propagation only on PLLH_AUX which is
* assigned index 7 in the parent array.
*/
.set_rate_parent = BIT(7)),
/* dsi clocks */ /* dsi clocks */
[BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
......
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