[PATCH] sparse alpha: long constants

Long constants marked as such

arch/alpha/kernel/core_cia.c

@@ -762,7 +762,7 @@ do_init_arch(int is_pyxis)
 		*(vip)CIA_IOC_PCI_W3_MASK = 0xfff00000;
 		*(vip)CIA_IOC_PCI_T3_BASE = 0 >> 2;
 
-		alpha_mv.pci_dac_offset = 0x200000000;
+		alpha_mv.pci_dac_offset = 0x200000000UL;
 		*(vip)CIA_IOC_PCI_W_DAC = alpha_mv.pci_dac_offset >> 32;
 	}
 

arch/alpha/kernel/core_irongate.c

@@ -287,9 +287,9 @@ irongate_init_arch(void)
 	hose->sparse_mem_base = 0;
 	hose->sparse_io_base = 0;
 	hose->dense_mem_base
-	  = (IRONGATE_MEM & 0xffffffffff) | 0x80000000000;
+	  = (IRONGATE_MEM & 0xffffffffffUL) | 0x80000000000UL;
 	hose->dense_io_base
-	  = (IRONGATE_IO & 0xffffffffff) | 0x80000000000;
+	  = (IRONGATE_IO & 0xffffffffffUL) | 0x80000000000UL;
 
 	hose->sg_isa = hose->sg_pci = NULL;
 	__direct_map_base = 0;

arch/alpha/kernel/core_titan.c

@@ -258,9 +258,9 @@ titan_init_one_pachip_port(titan_pachip_port *port, int index)
 	hose->sparse_mem_base = 0;
 	hose->sparse_io_base = 0;
 	hose->dense_mem_base
-	  = (TITAN_MEM(index) & 0xffffffffff) | 0x80000000000;
+	  = (TITAN_MEM(index) & 0xffffffffffUL) | 0x80000000000UL;
 	hose->dense_io_base
-	  = (TITAN_IO(index) & 0xffffffffff) | 0x80000000000;
+	  = (TITAN_IO(index) & 0xffffffffffUL) | 0x80000000000UL;
 
 	hose->config_space_base = TITAN_CONF(index);
 	hose->index = index;

arch/alpha/kernel/core_wildfire.c

@@ -285,8 +285,8 @@ wildfire_hardware_probe(void)
 		    fe = WILDFIRE_fe(soft_qbb, i);
 
 		    if ((iop->iop_hose[i].init.csr & 1) == 1 &&
-			((ne->ne_what_am_i.csr & 0xf00000300) == 0x100000300) &&
-			((fe->fe_what_am_i.csr & 0xf00000300) == 0x100000200))
+			((ne->ne_what_am_i.csr & 0xf00000300UL) == 0x100000300UL) &&
+			((fe->fe_what_am_i.csr & 0xf00000300UL) == 0x100000200UL))
 		    {
 		        wildfire_pca_mask |= 1 << ((soft_qbb << 2) + i);
 		    }

arch/alpha/kernel/setup.c

@@ -1359,7 +1359,7 @@ determine_cpu_caches (unsigned int cpu_type)
 		L1I = L1D = CSHAPE(8*1024, 5, 1);
 		L3 = -1;
 
-		car = *(vuip) phys_to_virt (0x120000078);
+		car = *(vuip) phys_to_virt (0x120000078UL);
 		size = 64*1024 * (1 << ((car >> 5) & 7));
 		/* No typo -- 8 byte cacheline size.  Whodathunk.  */
 		L2 = (car & 1 ? CSHAPE (size, 3, 1) : -1);
@@ -1374,7 +1374,7 @@ determine_cpu_caches (unsigned int cpu_type)
 		L1I = L1D = CSHAPE(8*1024, 5, 1);
 
 		/* Check the line size of the Scache.  */
-		sc_ctl = *(vulp) phys_to_virt (0xfffff000a8);
+		sc_ctl = *(vulp) phys_to_virt (0xfffff000a8UL);
 		width = sc_ctl & 0x1000 ? 6 : 5;
 		L2 = CSHAPE (96*1024, width, 3);
 
@@ -1406,7 +1406,7 @@ determine_cpu_caches (unsigned int cpu_type)
 		}
 		L3 = -1;
 
-		cbox_config = *(vulp) phys_to_virt (0xfffff00008);
+		cbox_config = *(vulp) phys_to_virt (0xfffff00008UL);
 		size = 512*1024 * (1 << ((cbox_config >> 12) & 3));
 
 #if 0

arch/alpha/kernel/sys_sx164.c

@@ -51,7 +51,7 @@ sx164_init_irq(void)
 	if (alpha_using_srm)
 		init_srm_irqs(40, 0x3f0000);
 	else
-		init_pyxis_irqs(0xff00003f0000);
+		init_pyxis_irqs(0xff00003f0000UL);
 
 	setup_irq(16+6, &timer_cascade_irqaction);
 }

arch/alpha/math-emu/math.c

@@ -171,7 +171,7 @@ alpha_fp_emul (unsigned long pc)
 					_FP_FRAC_SET_1(DB, _FP_ZEROFRAC_1);
 			}
 			FP_CMP_D(res, DA, DB, 3);
-			vc = 0x4000000000000000;
+			vc = 0x4000000000000000UL;
 			/* CMPTEQ, CMPTUN don't trap on QNaN,
 			   while CMPTLT and CMPTLE do */
 			if (res == 3

arch/alpha/mm/init.c

@@ -152,9 +152,9 @@ switch_to_system_map(void)
 
 	/* Set the vptb.  This is often done by the bootloader, but 
 	   shouldn't be required.  */
-	if (hwrpb->vptb != 0xfffffffe00000000) {
-		wrvptptr(0xfffffffe00000000);
-		hwrpb->vptb = 0xfffffffe00000000;
+	if (hwrpb->vptb != 0xfffffffe00000000UL) {
+		wrvptptr(0xfffffffe00000000UL);
+		hwrpb->vptb = 0xfffffffe00000000UL;
 		hwrpb_update_checksum(hwrpb);
 	}
 
@@ -301,8 +301,8 @@ srm_paging_stop (void)
 	/* Move the vptb back to where the SRM console expects it.  */
 	swapper_pg_dir[1] = swapper_pg_dir[1023];
 	tbia();
-	wrvptptr(0x200000000);
-	hwrpb->vptb = 0x200000000;
+	wrvptptr(0x200000000UL);
+	hwrpb->vptb = 0x200000000UL;
 	hwrpb_update_checksum(hwrpb);
 
 	/* Reload the page tables that the console had in use.  */

include/asm-alpha/core_polaris.h

@@ -18,13 +18,13 @@
  */
 
 /* Polaris memory regions */
-#define POLARIS_SPARSE_MEM_BASE		(IDENT_ADDR + 0xf800000000)
-#define POLARIS_DENSE_MEM_BASE		(IDENT_ADDR + 0xf900000000)
-#define POLARIS_SPARSE_IO_BASE		(IDENT_ADDR + 0xf980000000)
-#define POLARIS_SPARSE_CONFIG_BASE	(IDENT_ADDR + 0xf9c0000000)
-#define POLARIS_IACK_BASE		(IDENT_ADDR + 0xf9f8000000)
-#define POLARIS_DENSE_IO_BASE		(IDENT_ADDR + 0xf9fc000000)
-#define POLARIS_DENSE_CONFIG_BASE	(IDENT_ADDR + 0xf9fe000000)
+#define POLARIS_SPARSE_MEM_BASE		(IDENT_ADDR + 0xf800000000UL)
+#define POLARIS_DENSE_MEM_BASE		(IDENT_ADDR + 0xf900000000UL)
+#define POLARIS_SPARSE_IO_BASE		(IDENT_ADDR + 0xf980000000UL)
+#define POLARIS_SPARSE_CONFIG_BASE	(IDENT_ADDR + 0xf9c0000000UL)
+#define POLARIS_IACK_BASE		(IDENT_ADDR + 0xf9f8000000UL)
+#define POLARIS_DENSE_IO_BASE		(IDENT_ADDR + 0xf9fc000000UL)
+#define POLARIS_DENSE_CONFIG_BASE	(IDENT_ADDR + 0xf9fe000000UL)
 
 #define POLARIS_IACK_SC			POLARIS_IACK_BASE
 

include/asm-alpha/io.h

@@ -9,9 +9,9 @@
  * Virtual -> physical identity mapping starts at this offset
  */
 #ifdef USE_48_BIT_KSEG
-#define IDENT_ADDR     0xffff800000000000
+#define IDENT_ADDR     0xffff800000000000UL
 #else
-#define IDENT_ADDR     0xfffffc0000000000
+#define IDENT_ADDR     0xfffffc0000000000UL
 #endif
 
 #ifdef __KERNEL__

include/asm-alpha/page.h

@@ -73,10 +73,13 @@ extern __inline__ int get_order(unsigned long size)
 	return order;
 }
 
-#endif /* !__ASSEMBLY__ */
+#ifdef USE_48_BIT_KSEG
+#define PAGE_OFFSET		0xffff800000000000UL
+#else
+#define PAGE_OFFSET		0xfffffc0000000000UL
+#endif
 
-/* to align the pointer to the (next) page boundary */
-#define PAGE_ALIGN(addr)	(((addr)+PAGE_SIZE-1)&PAGE_MASK)
+#else
 
 #ifdef USE_48_BIT_KSEG
 #define PAGE_OFFSET		0xffff800000000000
@@ -84,6 +87,11 @@ extern __inline__ int get_order(unsigned long size)
 #define PAGE_OFFSET		0xfffffc0000000000
 #endif
 
+#endif /* !__ASSEMBLY__ */
+
+/* to align the pointer to the (next) page boundary */
+#define PAGE_ALIGN(addr)	(((addr)+PAGE_SIZE-1)&PAGE_MASK)
+
 #define __pa(x)			((unsigned long) (x) - PAGE_OFFSET)
 #define __va(x)			((void *)((unsigned long) (x) + PAGE_OFFSET))
 #ifndef CONFIG_DISCONTIGMEM

include/asm-alpha/pgtable.h

@@ -83,7 +83,7 @@
 #define __DIRTY_BITS	(_PAGE_DIRTY | _PAGE_KWE | _PAGE_UWE)
 #define __ACCESS_BITS	(_PAGE_ACCESSED | _PAGE_KRE | _PAGE_URE)
 
-#define _PFN_MASK	0xFFFFFFFF00000000
+#define _PFN_MASK	0xFFFFFFFF00000000UL
 
 #define _PAGE_TABLE	(_PAGE_VALID | __DIRTY_BITS | __ACCESS_BITS)
 #define _PAGE_CHG_MASK	(_PFN_MASK | __DIRTY_BITS | __ACCESS_BITS)