Commit d9a40271 authored by Achiad Shochat's avatar Achiad Shochat Committed by David S. Miller

net/mlx5e: HW LRO changes/fixes

- Change the maximum LRO session size from 16KB to 64KB
- Reduce the LRO session timeout from 512us to 32us in
  order to reduce the TCP latency of non-LRO'ed flows.
- Fix skb_shinfo(skb)->gso_size and set skb_shinfo(skb)->gso_type.
- Fix a bug accessing un-initialized mdev pointer.
Signed-off-by: default avatarAchiad Shochat <achiad@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e842b100
...@@ -50,7 +50,7 @@ ...@@ -50,7 +50,7 @@
#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (16 * 1024) #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
......
...@@ -1300,7 +1300,7 @@ static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv) ...@@ -1300,7 +1300,7 @@ static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
ROUGH_MAX_L2_L3_HDR_SZ) >> 8); ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
MLX5_SET(tirc, tirc, lro_timeout_period_usecs, MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
MLX5_CAP_ETH(priv->mdev, MLX5_CAP_ETH(priv->mdev,
lro_timer_supported_periods[3])); lro_timer_supported_periods[2]));
} }
static int mlx5e_modify_tir_lro(struct mlx5e_priv *priv, int tt) static int mlx5e_modify_tir_lro(struct mlx5e_priv *priv, int tt)
...@@ -1940,7 +1940,6 @@ static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev, ...@@ -1940,7 +1940,6 @@ static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++)
priv->params.indirection_rqt[i] = i % num_channels; priv->params.indirection_rqt[i] = i % num_channels;
priv->params.lro_en = false && !!MLX5_CAP_ETH(priv->mdev, lro_cap);
priv->params.lro_wqe_sz = priv->params.lro_wqe_sz =
MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
......
...@@ -111,10 +111,12 @@ static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe) ...@@ -111,10 +111,12 @@ static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe)
tcp = (struct tcphdr *)(skb->data + ETH_HLEN + tcp = (struct tcphdr *)(skb->data + ETH_HLEN +
sizeof(struct iphdr)); sizeof(struct iphdr));
ipv6 = NULL; ipv6 = NULL;
skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
} else { } else {
tcp = (struct tcphdr *)(skb->data + ETH_HLEN + tcp = (struct tcphdr *)(skb->data + ETH_HLEN +
sizeof(struct ipv6hdr)); sizeof(struct ipv6hdr));
ipv4 = NULL; ipv4 = NULL;
skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
} }
if (get_cqe_lro_tcppsh(cqe)) if (get_cqe_lro_tcppsh(cqe))
...@@ -162,7 +164,7 @@ static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, ...@@ -162,7 +164,7 @@ static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
if (lro_num_seg > 1) { if (lro_num_seg > 1) {
mlx5e_lro_update_hdr(skb, cqe); mlx5e_lro_update_hdr(skb, cqe);
skb_shinfo(skb)->gso_size = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
rq->stats.lro_packets++; rq->stats.lro_packets++;
rq->stats.lro_bytes += cqe_bcnt; rq->stats.lro_bytes += cqe_bcnt;
} }
......
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