Commit d9cfe75a authored by Linus Torvalds's avatar Linus Torvalds

DRI texmem branch merge cleanups. Texture ages are unsigned, and

radeon should use generic texture structure now.
parent 28c05818
...@@ -162,7 +162,7 @@ typedef struct drm_r128_sarea { ...@@ -162,7 +162,7 @@ typedef struct drm_r128_sarea {
unsigned int last_dispatch; unsigned int last_dispatch;
drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1]; drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1];
int tex_age[R128_NR_TEX_HEAPS]; unsigned int tex_age[R128_NR_TEX_HEAPS];
int ctx_owner; int ctx_owner;
} drm_r128_sarea_t; } drm_r128_sarea_t;
......
...@@ -322,12 +322,6 @@ typedef struct { ...@@ -322,12 +322,6 @@ typedef struct {
} drm_radeon_state_t; } drm_radeon_state_t;
typedef struct {
unsigned char next, prev;
unsigned char in_use;
int age;
} drm_radeon_tex_region_t;
typedef struct { typedef struct {
/* The channel for communication of state information to the /* The channel for communication of state information to the
* kernel on firing a vertex buffer with either of the * kernel on firing a vertex buffer with either of the
...@@ -350,8 +344,8 @@ typedef struct { ...@@ -350,8 +344,8 @@ typedef struct {
unsigned int last_dispatch; unsigned int last_dispatch;
unsigned int last_clear; unsigned int last_clear;
drm_radeon_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1]; drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
int tex_age[RADEON_NR_TEX_HEAPS]; unsigned int tex_age[RADEON_NR_TEX_HEAPS];
int ctx_owner; int ctx_owner;
int pfState; /* number of 3d windows (0,1,2ormore) */ int pfState; /* number of 3d windows (0,1,2ormore) */
int pfCurrentPage; /* which buffer is being displayed? */ int pfCurrentPage; /* which buffer is being displayed? */
......
...@@ -581,6 +581,7 @@ extern void radeon_do_release(drm_device_t *dev); ...@@ -581,6 +581,7 @@ extern void radeon_do_release(drm_device_t *dev);
#define RADEON_TXFORMAT_ARGB4444 5 #define RADEON_TXFORMAT_ARGB4444 5
#define RADEON_TXFORMAT_ARGB8888 6 #define RADEON_TXFORMAT_ARGB8888 6
#define RADEON_TXFORMAT_RGBA8888 7 #define RADEON_TXFORMAT_RGBA8888 7
#define RADEON_TXFORMAT_Y8 8
#define RADEON_TXFORMAT_VYUY422 10 #define RADEON_TXFORMAT_VYUY422 10
#define RADEON_TXFORMAT_YVYU422 11 #define RADEON_TXFORMAT_YVYU422 11
#define RADEON_TXFORMAT_DXT1 12 #define RADEON_TXFORMAT_DXT1 12
......
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