Commit d9d3e8ed authored by Alex Deucher's avatar Alex Deucher Committed by Greg Kroah-Hartman

drm/radeon: fix hdmi mode enable on RS600/RS690/RS740

commit dcb85290 upstream.

These chips were previously skipped since they are
pre-R600.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
[bwh: Backported to 3.2: adjust context]
Signed-off-by: default avatarBen Hutchings <ben@decadent.org.uk>
[wml: Backported to 3.4:
- adjust context
- no !ASIC_IS_DCE3(rdev)]
Signed-off-by: default avatarWeng Meiling <wengmeiling.weng@huawei.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 63034aee
...@@ -530,7 +530,7 @@ void r600_hdmi_enable(struct drm_encoder *encoder) ...@@ -530,7 +530,7 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1); WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1);
} else if (ASIC_IS_DCE3(rdev)) { } else if (ASIC_IS_DCE3(rdev)) {
/* TODO */ /* TODO */
} else if (rdev->family >= CHIP_R600) { } else if (ASIC_IS_DCE2(rdev)) {
switch (radeon_encoder->encoder_id) { switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN, WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
...@@ -602,7 +602,7 @@ void r600_hdmi_disable(struct drm_encoder *encoder) ...@@ -602,7 +602,7 @@ void r600_hdmi_disable(struct drm_encoder *encoder)
WREG32_P(radeon_encoder->hdmi_config_offset + 0xc, 0, ~0x1); WREG32_P(radeon_encoder->hdmi_config_offset + 0xc, 0, ~0x1);
} else if (ASIC_IS_DCE32(rdev)) { } else if (ASIC_IS_DCE32(rdev)) {
WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0, ~0x1); WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0, ~0x1);
} else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { } else if (ASIC_IS_DCE2(rdev) && !ASIC_IS_DCE3(rdev)) {
switch (radeon_encoder->encoder_id) { switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
WREG32_P(AVIVO_TMDSA_CNTL, 0, WREG32_P(AVIVO_TMDSA_CNTL, 0,
......
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