Commit da15797e authored by Hans J. Koch's avatar Hans J. Koch Committed by Thomas Gleixner

ARM: Add the clock framework for Telechips TCC8xxx processors.

This adds definitions and low-level functions to handle clocks in
TCC8xxx processors.
Signed-off-by: default avatar"Hans J. Koch" <hjk@linutronix.de>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 83ef3338
#
# Makefile for TCC8K boards and common files.
#
# Common support
obj-y += clock.o
This diff is collapsed.
#ifndef MACH_TCC8K_COMMON_H
#define MACH_TCC8K_COMMON_H
extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq);
#endif
# "Telechips Platform Common Modules"
obj-y := system.o
obj-y := clock.o system.o
/*
* Clock framework for Telechips SoCs
* Based on arch/arm/plat-mxc/clock.c
*
* Copyright (C) 2004 - 2005 Nokia corporation
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
* Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
* Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
* Copyright 2010 Hans J. Koch, hjk@linutronix.de
*
* Licensed under the terms of the GPL v2.
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/string.h>
#include <mach/clock.h>
#include <mach/hardware.h>
static DEFINE_MUTEX(clocks_mutex);
/*-------------------------------------------------------------------------
* Standard clock functions defined in include/linux/clk.h
*-------------------------------------------------------------------------*/
static void __clk_disable(struct clk *clk)
{
BUG_ON(clk->refcount == 0);
if (!(--clk->refcount) && clk->disable) {
/* Unconditionally disable the clock in hardware */
clk->disable(clk);
/* recursively disable parents */
if (clk->parent)
__clk_disable(clk->parent);
}
}
static int __clk_enable(struct clk *clk)
{
int ret = 0;
if (clk->refcount++ == 0 && clk->enable) {
if (clk->parent)
ret = __clk_enable(clk->parent);
if (ret)
return ret;
else
return clk->enable(clk);
}
return 0;
}
/* This function increments the reference count on the clock and enables the
* clock if not already enabled. The parent clock tree is recursively enabled
*/
int clk_enable(struct clk *clk)
{
int ret = 0;
if (!clk)
return -EINVAL;
mutex_lock(&clocks_mutex);
ret = __clk_enable(clk);
mutex_unlock(&clocks_mutex);
return ret;
}
EXPORT_SYMBOL_GPL(clk_enable);
/* This function decrements the reference count on the clock and disables
* the clock when reference count is 0. The parent clock tree is
* recursively disabled
*/
void clk_disable(struct clk *clk)
{
if (!clk)
return;
mutex_lock(&clocks_mutex);
__clk_disable(clk);
mutex_unlock(&clocks_mutex);
}
EXPORT_SYMBOL_GPL(clk_disable);
/* Retrieve the *current* clock rate. If the clock itself
* does not provide a special calculation routine, ask
* its parent and so on, until one is able to return
* a valid clock rate
*/
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk)
return 0UL;
if (clk->get_rate)
return clk->get_rate(clk);
return clk_get_rate(clk->parent);
}
EXPORT_SYMBOL_GPL(clk_get_rate);
/* Round the requested clock rate to the nearest supported
* rate that is less than or equal to the requested rate.
* This is dependent on the clock's current parent.
*/
long clk_round_rate(struct clk *clk, unsigned long rate)
{
if (!clk)
return 0;
if (!clk->round_rate)
return 0;
return clk->round_rate(clk, rate);
}
EXPORT_SYMBOL_GPL(clk_round_rate);
/* Set the clock to the requested clock rate. The rate must
* match a supported rate exactly based on what clk_round_rate returns
*/
int clk_set_rate(struct clk *clk, unsigned long rate)
{
int ret = -EINVAL;
if (!clk)
return ret;
if (!clk->set_rate || !rate)
return ret;
mutex_lock(&clocks_mutex);
ret = clk->set_rate(clk, rate);
mutex_unlock(&clocks_mutex);
return ret;
}
EXPORT_SYMBOL_GPL(clk_set_rate);
/* Set the clock's parent to another clock source */
int clk_set_parent(struct clk *clk, struct clk *parent)
{
struct clk *old;
int ret = -EINVAL;
if (!clk)
return ret;
if (!clk->set_parent || !parent)
return ret;
mutex_lock(&clocks_mutex);
old = clk->parent;
if (clk->refcount)
__clk_enable(parent);
ret = clk->set_parent(clk, parent);
if (ret)
old = parent;
if (clk->refcount)
__clk_disable(old);
mutex_unlock(&clocks_mutex);
return ret;
}
EXPORT_SYMBOL_GPL(clk_set_parent);
/* Retrieve the clock's parent clock source */
struct clk *clk_get_parent(struct clk *clk)
{
if (!clk)
return NULL;
return clk->parent;
}
EXPORT_SYMBOL_GPL(clk_get_parent);
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif
/*
* Low level clock header file for Telechips TCC architecture
* (C) 2010 Hans J. Koch <hjk@linutronix.de>
*
* Licensed under the GPL v2.
*/
#ifndef __ASM_ARCH_TCC_CLOCK_H__
#define __ASM_ARCH_TCC_CLOCK_H__
#ifndef __ASSEMBLY__
struct clk {
struct clk *parent;
/* id number of a root clock, 0 for normal clocks */
int root_id;
/* Reference count of clock enable/disable */
int refcount;
/* Address of associated BCLKCTRx register. Must be set. */
void __iomem *bclkctr;
/* Bit position for BCLKCTRx. Must be set. */
int bclk_shift;
/* Address of ACLKxxx register, if any. */
void __iomem *aclkreg;
/* get the current clock rate (always a fresh value) */
unsigned long (*get_rate) (struct clk *);
/* Function ptr to set the clock to a new rate. The rate must match a
supported rate returned from round_rate. Leave blank if clock is not
programmable */
int (*set_rate) (struct clk *, unsigned long);
/* Function ptr to round the requested clock rate to the nearest
supported rate that is less than or equal to the requested rate. */
unsigned long (*round_rate) (struct clk *, unsigned long);
/* Function ptr to enable the clock. Leave blank if clock can not
be gated. */
int (*enable) (struct clk *);
/* Function ptr to disable the clock. Leave blank if clock can not
be gated. */
void (*disable) (struct clk *);
/* Function ptr to set the parent clock of the clock. */
int (*set_parent) (struct clk *, struct clk *);
};
int clk_register(struct clk *clk);
void clk_unregister(struct clk *clk);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
......@@ -30,13 +30,13 @@
#define EXT_MEM_CTRL_BASE 0xf0000000
#define EXT_MEM_CTRL_SIZE SZ_4K
#define CS1_BASE_VIRT 0xf7000000
#define AHB_PERI_BASE_VIRT 0xf4000000
#define APB0_PERI_BASE_VIRT 0xf1000000
#define APB1_PERI_BASE_VIRT 0xf2000000
#define EXT_MEM_CTRL_BASE_VIRT 0xf3000000
#define INT_SRAM_BASE_VIRT 0xf5000000
#define DATA_TCM_BASE_VIRT 0xf6000000
#define CS1_BASE_VIRT (void __iomem *)0xf7000000
#define AHB_PERI_BASE_VIRT (void __iomem *)0xf4000000
#define APB0_PERI_BASE_VIRT (void __iomem *)0xf1000000
#define APB1_PERI_BASE_VIRT (void __iomem *)0xf2000000
#define EXT_MEM_CTRL_BASE_VIRT (void __iomem *)0xf3000000
#define INT_SRAM_BASE_VIRT (void __iomem *)0xf5000000
#define DATA_TCM_BASE_VIRT (void __iomem *)0xf6000000
#define __REG(x) (*((volatile u32 *)(x)))
......@@ -649,8 +649,7 @@
#define PMGPIO_APB_OFFS 0x800
/* Clock controller registers */
#define CKC_BASE (APB1_PERI_BASE_VIRT + 0x6000)
#define CKC_BASE_PHYS (APB1_PERI_BASE + 0x6000)
#define CKC_BASE ((void __iomem *)(APB1_PERI_BASE_VIRT + 0x6000))
#define CLKCTRL_OFFS 0x00
#define PLL0CFG_OFFS 0x04
......@@ -724,8 +723,20 @@
/* SWRESET1 bits */
#define SWRESET1_USBH1 (1 << 20)
/* System clock sources */
/* System clock sources.
* Note: These are the clock sources that serve as parents for
* all other clocks. They have no parents themselves.
*
* These values are used for struct clk->root_id. All clocks
* that are not system clock sources have this value set to
* CLK_SRC_NOROOT.
* The values for system clocks start with CLK_SRC_PLL0 == 0
* because this gives us exactly the values needed for the lower
* 4 bits of ACLK_* registers. Therefore, CLK_SRC_NOROOT is
* defined as -1 to not disturb the order.
*/
enum root_clks {
CLK_SRC_NOROOT = -1,
CLK_SRC_PLL0 = 0,
CLK_SRC_PLL1,
CLK_SRC_PLL0DIV,
......
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