Skip to content

L
linux
Commit da3ef7f6 authored by James Clark's avatar James Clark Committed by Arnaldo Carvalho de Melo
Browse files
Options

perf vendor events power9: Fix commas so PMU event files are valid JSON 

No functional change.

Remove extra commas in the power9 JSON files so that the files
can be parsed and validated by other utilities such as Python
that fail to parse invalid JSON.

Before:

  $ diffstat -l -p1 /wb/1.patch | while read filename ; do echo $filename ; cat $filename | json_verify ; done
  tools/perf/pmu-events/arch/powerpc/power9/cache.json
  parse error: invalid object key (must be a string)
                                          [   {,     "EventCode": "0x300
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/powerpc/power9/floating-point.json
  parse error: invalid object key (must be a string)
                                          [   {,     "EventCode": "0x141
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/powerpc/power9/frontend.json
  parse error: invalid object key (must be a string)
                                          [   {,     "EventCode": "0x250
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/powerpc/power9/marked.json
  parse error: invalid object key (must be a string)
                                          [   {,     "EventCode": "0x301
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/powerpc/power9/memory.json
  parse error: invalid object key (must be a string)
                                          [   {,     "EventCode": "0x300
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/powerpc/power9/other.json
  parse error: invalid object key (must be a string)
                                          [   {,     "EventCode": "0x308
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/powerpc/power9/pipeline.json
  parse error: invalid object key (must be a string)
                                          [   {,     "EventCode": "0x4D0
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/powerpc/power9/pmc.json
  parse error: invalid object key (must be a string)
                                          [   {,     "EventCode": "0x200
                       (right here) ------^
  JSON is invalid
  tools/perf/pmu-events/arch/powerpc/power9/translation.json
  parse error: invalid object key (must be a string)
                                          [   {,     "EventCode": "0x1E"
                       (right here) ------^
  JSON is invalid
  $

After:

  $ diffstat -l -p1 /wb/1.patch | while read filename ; do echo $filename ; cat $filename | json_verify ; done
  tools/perf/pmu-events/arch/powerpc/power9/cache.json
  JSON is valid
  tools/perf/pmu-events/arch/powerpc/power9/floating-point.json
  JSON is valid
  tools/perf/pmu-events/arch/powerpc/power9/frontend.json
  JSON is valid
  tools/perf/pmu-events/arch/powerpc/power9/marked.json
  JSON is valid
  tools/perf/pmu-events/arch/powerpc/power9/memory.json
  JSON is valid
  tools/perf/pmu-events/arch/powerpc/power9/other.json
  JSON is valid
  tools/perf/pmu-events/arch/powerpc/power9/pipeline.json
  JSON is valid
  tools/perf/pmu-events/arch/powerpc/power9/pmc.json
  JSON is valid
  tools/perf/pmu-events/arch/powerpc/power9/translation.json
  JSON is valid
  $
Signed-off-by: default avatarJames Clark <james.clark@arm.com>
Tested-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kevin Mooney <kevin.mooney@arm.com>
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Cc: Mamatha Inamdar <mamatha4@linux.vnet.ibm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
Cc: nd@arm.com
Link: http://lore.kernel.org/lkml/20191112160342.26470-3-james.clark@arm.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 835e5bd9
Expand all Show whitespace changes
Inline Side-by-side
Showing with 894 additions and 894 deletions
tools/perf/pmu-events/arch/powerpc/power9/cache.json
View file @ da3ef7f6
[ [
{, {
"EventCode": "0x300F4", "EventCode": "0x300F4",
"EventName": "PM_THRD_CONC_RUN_INST", "EventName": "PM_THRD_CONC_RUN_INST",
"BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set" "BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set"
}, },
{, {
"EventCode": "0x1E056", "EventCode": "0x1E056",
"EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD", "EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD",
"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion" "BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion"
}, },
{, {
"EventCode": "0x4D016", "EventCode": "0x4D016",
"EventName": "PM_CMPLU_STALL_FXLONG", "EventName": "PM_CMPLU_STALL_FXLONG",
"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)" "BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)"
}, },
{, {
"EventCode": "0x2D016", "EventCode": "0x2D016",
"EventName": "PM_CMPLU_STALL_FXU", "EventName": "PM_CMPLU_STALL_FXU",
"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes" "BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
}, },
{, {
"EventCode": "0x4D12A", "EventCode": "0x4D12A",
"EventName": "PM_MRK_DATA_FROM_RL4_CYC", "EventName": "PM_MRK_DATA_FROM_RL4_CYC",
"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load" "BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load"
}, },
{, {
"EventCode": "0x1003C", "EventCode": "0x1003C",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3", "EventName": "PM_CMPLU_STALL_DMISS_L2L3",
"BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3" "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3"
}, },
{, {
"EventCode": "0x4C014", "EventCode": "0x4C014",
"EventName": "PM_CMPLU_STALL_LMQ_FULL", "EventName": "PM_CMPLU_STALL_LMQ_FULL",
"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full" "BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full"
}, },
{, {
"EventCode": "0x14048", "EventCode": "0x14048",
"EventName": "PM_INST_FROM_ON_CHIP_CACHE", "EventName": "PM_INST_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)" "BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)"
}, },
{, {
"EventCode": "0x4D014", "EventCode": "0x4D014",
"EventName": "PM_CMPLU_STALL_LOAD_FINISH", "EventName": "PM_CMPLU_STALL_LOAD_FINISH",
"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish" "BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish"
}, },
{, {
"EventCode": "0x2404A", "EventCode": "0x2404A",
"EventName": "PM_INST_FROM_RL4", "EventName": "PM_INST_FROM_RL4",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)" "BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
}, },
{, {
"EventCode": "0x1404A", "EventCode": "0x1404A",
"EventName": "PM_INST_FROM_RL2L3_SHR", "EventName": "PM_INST_FROM_RL2L3_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)" "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
}, },
{, {
"EventCode": "0x401EA", "EventCode": "0x401EA",
"EventName": "PM_THRESH_EXC_128", "EventName": "PM_THRESH_EXC_128",
"BriefDescription": "Threshold counter exceeded a value of 128" "BriefDescription": "Threshold counter exceeded a value of 128"
}, },
{, {
"EventCode": "0x400F6", "EventCode": "0x400F6",
"EventName": "PM_BR_MPRED_CMPL", "EventName": "PM_BR_MPRED_CMPL",
"BriefDescription": "Number of Branch Mispredicts" "BriefDescription": "Number of Branch Mispredicts"
}, },
{, {
"EventCode": "0x2F140", "EventCode": "0x2F140",
"EventName": "PM_MRK_DPTEG_FROM_L2_MEPF", "EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
}, },
{, {
"EventCode": "0x101E6", "EventCode": "0x101E6",
"EventName": "PM_THRESH_EXC_4096", "EventName": "PM_THRESH_EXC_4096",
"BriefDescription": "Threshold counter exceed a count of 4096" "BriefDescription": "Threshold counter exceed a count of 4096"
}, },
{, {
"EventCode": "0x3F14A", "EventCode": "0x3F14A",
"EventName": "PM_MRK_DPTEG_FROM_RMEM", "EventName": "PM_MRK_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
}, },
{, {
"EventCode": "0x4C016", "EventCode": "0x4C016",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT", "EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict" "BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict"
}, },
{, {
"EventCode": "0x2C01A", "EventCode": "0x2C01A",
"EventName": "PM_CMPLU_STALL_LHS", "EventName": "PM_CMPLU_STALL_LHS",
"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data" "BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data"
}, },
{, {
"EventCode": "0x401E4", "EventCode": "0x401E4",
"EventName": "PM_MRK_DTLB_MISS", "EventName": "PM_MRK_DTLB_MISS",
"BriefDescription": "Marked dtlb miss" "BriefDescription": "Marked dtlb miss"
}, },
{, {
"EventCode": "0x24046", "EventCode": "0x24046",
"EventName": "PM_INST_FROM_RL2L3_MOD", "EventName": "PM_INST_FROM_RL2L3_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)" "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
}, },
{, {
"EventCode": "0x1002A", "EventCode": "0x1002A",
"EventName": "PM_CMPLU_STALL_LARX", "EventName": "PM_CMPLU_STALL_LARX",
"BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied" "BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied"
......
tools/perf/pmu-events/arch/powerpc/power9/floating-point.json
View file @ da3ef7f6
[ [
{, {
"EventCode": "0x1415A", "EventCode": "0x1415A",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC", "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load" "BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load"
}, },
{, {
"EventCode": "0x10058", "EventCode": "0x10058",
"EventName": "PM_MEM_LOC_THRESH_IFU", "EventName": "PM_MEM_LOC_THRESH_IFU",
"BriefDescription": "Local Memory above threshold for IFU speculation control" "BriefDescription": "Local Memory above threshold for IFU speculation control"
}, },
{, {
"EventCode": "0x2D028", "EventCode": "0x2D028",
"EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2", "EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2",
"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache" "BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache"
}, },
{, {
"EventCode": "0x30012", "EventCode": "0x30012",
"EventName": "PM_FLUSH_COMPLETION", "EventName": "PM_FLUSH_COMPLETION",
"BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush" "BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush"
}, },
{, {
"EventCode": "0x2D154", "EventCode": "0x2D154",
"EventName": "PM_MRK_DERAT_MISS_64K", "EventName": "PM_MRK_DERAT_MISS_64K",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K" "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K"
}, },
{, {
"EventCode": "0x4016E", "EventCode": "0x4016E",
"EventName": "PM_THRESH_NOT_MET", "EventName": "PM_THRESH_NOT_MET",
"BriefDescription": "Threshold counter did not meet threshold" "BriefDescription": "Threshold counter did not meet threshold"
......
tools/perf/pmu-events/arch/powerpc/power9/memory.json
View file @ da3ef7f6
[ [
{, {
"EventCode": "0x3006E", "EventCode": "0x3006E",
"EventName": "PM_NEST_REF_CLK", "EventName": "PM_NEST_REF_CLK",
"BriefDescription": "Multiply by 4 to obtain the number of PB cycles" "BriefDescription": "Multiply by 4 to obtain the number of PB cycles"
}, },
{, {
"EventCode": "0x20010", "EventCode": "0x20010",
"EventName": "PM_PMC1_OVERFLOW", "EventName": "PM_PMC1_OVERFLOW",
"BriefDescription": "Overflow from counter 1" "BriefDescription": "Overflow from counter 1"
}, },
{, {
"EventCode": "0x2005A", "EventCode": "0x2005A",
"EventName": "PM_DARQ1_7_9_ENTRIES", "EventName": "PM_DARQ1_7_9_ENTRIES",
"BriefDescription": "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use" "BriefDescription": "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use"
}, },
{, {
"EventCode": "0x3C048", "EventCode": "0x3C048",
"EventName": "PM_DATA_FROM_DL2L3_SHR", "EventName": "PM_DATA_FROM_DL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load" "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load"
}, },
{, {
"EventCode": "0x10008", "EventCode": "0x10008",
"EventName": "PM_RUN_SPURR", "EventName": "PM_RUN_SPURR",
"BriefDescription": "Run SPURR" "BriefDescription": "Run SPURR"
}, },
{, {
"EventCode": "0x200F6", "EventCode": "0x200F6",
"EventName": "PM_LSU_DERAT_MISS", "EventName": "PM_LSU_DERAT_MISS",
"BriefDescription": "DERAT Reloaded due to a DERAT miss" "BriefDescription": "DERAT Reloaded due to a DERAT miss"
}, },
{, {
"EventCode": "0x4C048", "EventCode": "0x4C048",
"EventName": "PM_DATA_FROM_DL2L3_MOD", "EventName": "PM_DATA_FROM_DL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load" "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load"
}, },
{, {
"EventCode": "0x1D15E", "EventCode": "0x1D15E",
"EventName": "PM_MRK_RUN_CYC", "EventName": "PM_MRK_RUN_CYC",
"BriefDescription": "Run cycles in which a marked instruction is in the pipeline" "BriefDescription": "Run cycles in which a marked instruction is in the pipeline"
}, },
{, {
"EventCode": "0x4003E", "EventCode": "0x4003E",
"EventName": "PM_LD_CMPL", "EventName": "PM_LD_CMPL",
"BriefDescription": "count of Loads completed" "BriefDescription": "count of Loads completed"
}, },
{, {
"EventCode": "0x4C042", "EventCode": "0x4C042",
"EventName": "PM_DATA_FROM_L3", "EventName": "PM_DATA_FROM_L3",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load" "BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load"
}, },
{, {
"EventCode": "0x4D02C", "EventCode": "0x4D02C",
"EventName": "PM_PMC1_REWIND", "EventName": "PM_PMC1_REWIND",
"BriefDescription": "PMC1 rewind event" "BriefDescription": "PMC1 rewind event"
}, },
{, {
"EventCode": "0x15158", "EventCode": "0x15158",
"EventName": "PM_SYNC_MRK_L2HIT", "EventName": "PM_SYNC_MRK_L2HIT",
"BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt" "BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt"
}, },
{, {
"EventCode": "0x3404A", "EventCode": "0x3404A",
"EventName": "PM_INST_FROM_RMEM", "EventName": "PM_INST_FROM_RMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)" "BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
}, },
{, {
"EventCode": "0x301E2", "EventCode": "0x301E2",
"EventName": "PM_MRK_ST_CMPL", "EventName": "PM_MRK_ST_CMPL",
"BriefDescription": "Marked store completed and sent to nest" "BriefDescription": "Marked store completed and sent to nest"
}, },
{, {
"EventCode": "0x1C050", "EventCode": "0x1C050",
"EventName": "PM_DATA_CHIP_PUMP_CPRED", "EventName": "PM_DATA_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load" "BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load"
}, },
{, {
"EventCode": "0x4C040", "EventCode": "0x4C040",
"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER", "EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load" "BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load"
}, },
{, {
"EventCode": "0x2E05C", "EventCode": "0x2E05C",
"EventName": "PM_LSU_REJECT_ERAT_MISS", "EventName": "PM_LSU_REJECT_ERAT_MISS",
"BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)" "BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)"
}, },
{, {
"EventCode": "0x1000A", "EventCode": "0x1000A",
"EventName": "PM_PMC3_REWIND", "EventName": "PM_PMC3_REWIND",
"BriefDescription": "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change." "BriefDescription": "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change."
}, },
{, {
"EventCode": "0x3C058", "EventCode": "0x3C058",
"EventName": "PM_LARX_FIN", "EventName": "PM_LARX_FIN",
"BriefDescription": "Larx finished" "BriefDescription": "Larx finished"
}, },
{, {
"EventCode": "0x1C040", "EventCode": "0x1C040",
"EventName": "PM_DATA_FROM_L2_NO_CONFLICT", "EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load" "BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load"
}, },
{, {
"EventCode": "0x2C040", "EventCode": "0x2C040",
"EventName": "PM_DATA_FROM_L2_MEPF", "EventName": "PM_DATA_FROM_L2_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load" "BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load"
}, },
{, {
"EventCode": "0x2E05A", "EventCode": "0x2E05A",
"EventName": "PM_LRQ_REJECT", "EventName": "PM_LRQ_REJECT",
"BriefDescription": "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects" "BriefDescription": "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects"
}, },
{, {
"EventCode": "0x2C05C", "EventCode": "0x2C05C",
"EventName": "PM_INST_GRP_PUMP_CPRED", "EventName": "PM_INST_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)" "BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)"
}, },
{, {
"EventCode": "0x4D056", "EventCode": "0x4D056",
"EventName": "PM_NON_FMA_FLOP_CMPL", "EventName": "PM_NON_FMA_FLOP_CMPL",
"BriefDescription": "Non FMA instruction completed" "BriefDescription": "Non FMA instruction completed"
}, },
{, {
"EventCode": "0x3E050", "EventCode": "0x3E050",
"EventName": "PM_DARQ1_4_6_ENTRIES", "EventName": "PM_DARQ1_4_6_ENTRIES",
"BriefDescription": "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use" "BriefDescription": "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use"
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7