Commit db066501 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "A smallish set of fixes that we've been sitting on for a while now,
  flushing the queue here so they go in.  Summary:

  A handful of fixes for OMAP, i.MX, Allwinner and Tegra:

   - A clock rate and a PHY setup fix for i.MX6Q/DL
   - A couple of fixes for the reduced serial bus (sunxi-rsb) on
     Allwinner
   - UART wakeirq fix for an OMAP4 board, timer config fixes for AM43XX.
   - Suspend fix for Tegra124 Chromebooks
   - Fix for missing implicit include that's different between
     ARM/ARM64"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: tegra: Fix suspend hang on Tegra124 Chromebooks
  bus: sunxi-rsb: Fix peripheral IC mapping runtime address
  bus: sunxi-rsb: Fix primary PMIC mapping hardware address
  ARM: dts: Fix UART wakeirq for omap4 duovero parlor
  ARM: OMAP2+: AM43xx: select ARM TWD timer
  ARM: OMAP2+: am43xx: enable GENERIC_CLOCKEVENTS_BROADCAST
  fsl-ifc: add missing include on ARM64
  ARM: dts: imx6: Fix Ethernet PHY mode on Ventana boards
  ARM: dts: imx: Fix the assigned-clock mismatch issue on imx6q/dl
  bus: sunxi-rsb: unlock on error in sunxi_rsb_read()
  ARM: dts: sunxi: sun6i-a31s-primo81.dts: add touchscreen axis swapping property
parents 2c96961f 80373d37
...@@ -154,7 +154,7 @@ flash: m25p80@0 { ...@@ -154,7 +154,7 @@ flash: m25p80@0 {
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
}; };
......
...@@ -94,7 +94,7 @@ reg_usb_otg_vbus: regulator@2 { ...@@ -94,7 +94,7 @@ reg_usb_otg_vbus: regulator@2 {
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
......
...@@ -154,7 +154,7 @@ &can1 { ...@@ -154,7 +154,7 @@ &can1 {
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
......
...@@ -155,7 +155,7 @@ &can1 { ...@@ -155,7 +155,7 @@ &can1 {
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
......
...@@ -145,7 +145,7 @@ &can1 { ...@@ -145,7 +145,7 @@ &can1 {
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
......
...@@ -113,14 +113,14 @@ backlight { ...@@ -113,14 +113,14 @@ backlight {
&clks { &clks {
assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
<&clks IMX6QDL_PLL4_BYPASS>, <&clks IMX6QDL_PLL4_BYPASS>,
<&clks IMX6QDL_CLK_PLL4_POST_DIV>,
<&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>; <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_PLL4_POST_DIV>;
assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
<&clks IMX6QDL_PLL4_BYPASS_SRC>, <&clks IMX6QDL_PLL4_BYPASS_SRC>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>; <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
assigned-clock-rates = <0>, <0>, <24576000>; assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
}; };
&ecspi1 { &ecspi1 {
......
...@@ -189,3 +189,7 @@ hdmi_out: endpoint { ...@@ -189,3 +189,7 @@ hdmi_out: endpoint {
}; };
}; };
&uart3 {
interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART3_RX>;
};
...@@ -83,6 +83,7 @@ ctp@5d { ...@@ -83,6 +83,7 @@ ctp@5d {
reg = <0x5d>; reg = <0x5d>;
interrupt-parent = <&pio>; interrupt-parent = <&pio>;
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */
touchscreen-swapped-x-y;
}; };
}; };
......
...@@ -399,7 +399,7 @@ sdhci@0,700b0600 { /* eMMC on this bus */ ...@@ -399,7 +399,7 @@ sdhci@0,700b0600 { /* eMMC on this bus */
/* CPU DFLL clock */ /* CPU DFLL clock */
clock@0,70110000 { clock@0,70110000 {
status = "okay"; status = "disabled";
vdd-cpu-supply = <&vdd_cpu>; vdd-cpu-supply = <&vdd_cpu>;
nvidia,i2c-fs-rate = <400000>; nvidia,i2c-fs-rate = <400000>;
}; };
......
...@@ -65,6 +65,8 @@ config SOC_AM43XX ...@@ -65,6 +65,8 @@ config SOC_AM43XX
select MACH_OMAP_GENERIC select MACH_OMAP_GENERIC
select MIGHT_HAVE_CACHE_L2X0 select MIGHT_HAVE_CACHE_L2X0
select HAVE_ARM_SCU select HAVE_ARM_SCU
select GENERIC_CLOCKEVENTS_BROADCAST
select HAVE_ARM_TWD
config SOC_DRA7XX config SOC_DRA7XX
bool "TI DRA7XX" bool "TI DRA7XX"
......
...@@ -320,6 +320,12 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, ...@@ -320,6 +320,12 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
return r; return r;
} }
#if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
void tick_broadcast(const struct cpumask *mask)
{
}
#endif
static void __init omap2_gp_clockevent_init(int gptimer_id, static void __init omap2_gp_clockevent_init(int gptimer_id,
const char *fck_source, const char *fck_source,
const char *property) const char *property)
......
...@@ -342,13 +342,13 @@ static int sunxi_rsb_read(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr, ...@@ -342,13 +342,13 @@ static int sunxi_rsb_read(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr,
ret = _sunxi_rsb_run_xfer(rsb); ret = _sunxi_rsb_run_xfer(rsb);
if (ret) if (ret)
goto out; goto unlock;
*buf = readl(rsb->regs + RSB_DATA); *buf = readl(rsb->regs + RSB_DATA);
unlock:
mutex_unlock(&rsb->lock); mutex_unlock(&rsb->lock);
out:
return ret; return ret;
} }
...@@ -527,9 +527,9 @@ static int sunxi_rsb_init_device_mode(struct sunxi_rsb *rsb) ...@@ -527,9 +527,9 @@ static int sunxi_rsb_init_device_mode(struct sunxi_rsb *rsb)
*/ */
static const struct sunxi_rsb_addr_map sunxi_rsb_addr_maps[] = { static const struct sunxi_rsb_addr_map sunxi_rsb_addr_maps[] = {
{ 0x3e3, 0x2d }, /* Primary PMIC: AXP223, AXP809, AXP81X, ... */ { 0x3a3, 0x2d }, /* Primary PMIC: AXP223, AXP809, AXP81X, ... */
{ 0x745, 0x3a }, /* Secondary PMIC: AXP806, ... */ { 0x745, 0x3a }, /* Secondary PMIC: AXP806, ... */
{ 0xe89, 0x45 }, /* Peripheral IC: AC100, ... */ { 0xe89, 0x4e }, /* Peripheral IC: AC100, ... */
}; };
static u8 sunxi_rsb_get_rtaddr(u16 hwaddr) static u8 sunxi_rsb_get_rtaddr(u16 hwaddr)
......
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
#include <linux/module.h> #include <linux/module.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/compiler.h> #include <linux/compiler.h>
#include <linux/sched.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/types.h> #include <linux/types.h>
#include <linux/slab.h> #include <linux/slab.h>
......
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