Commit dbca8310 authored by Joshua Aberback's avatar Joshua Aberback Committed by Alex Deucher

drm/amd/display: Clean up flip pending timeout handling

[Why]
Adjust timeout handling code for easier runtime manipulation
during debug. Change has no functional effect by default.
Reviewed-by: default avatarAric Cyr <aric.cyr@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarJoshua Aberback <joshua.aberback@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e24b2fda
...@@ -1269,20 +1269,21 @@ void dcn20_pipe_control_lock( ...@@ -1269,20 +1269,21 @@ void dcn20_pipe_control_lock(
} }
if (flip_immediate && lock) { if (flip_immediate && lock) {
const int TIMEOUT_FOR_FLIP_PENDING = 100000; const int TIMEOUT_FOR_FLIP_PENDING_US = 100000;
unsigned int polling_interval_us = 1;
int i; int i;
temp_pipe = pipe; temp_pipe = pipe;
while (temp_pipe) { while (temp_pipe) {
if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) { if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) {
for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING_US / polling_interval_us; ++i) {
if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp)) if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))
break; break;
udelay(1); udelay(polling_interval_us);
} }
/* no reason it should take this long for immediate flips */ /* no reason it should take this long for immediate flips */
ASSERT(i != TIMEOUT_FOR_FLIP_PENDING); ASSERT(i != TIMEOUT_FOR_FLIP_PENDING_US);
} }
temp_pipe = temp_pipe->bottom_pipe; temp_pipe = temp_pipe->bottom_pipe;
} }
...@@ -1952,7 +1953,8 @@ void dcn20_post_unlock_program_front_end( ...@@ -1952,7 +1953,8 @@ void dcn20_post_unlock_program_front_end(
struct dc_state *context) struct dc_state *context)
{ {
int i; int i;
const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; const unsigned int TIMEOUT_FOR_PIPE_ENABLE_US = 100000;
unsigned int polling_interval_us = 1;
struct dce_hwseq *hwseq = dc->hwseq; struct dce_hwseq *hwseq = dc->hwseq;
DC_LOGGER_INIT(dc->ctx->logger); DC_LOGGER_INIT(dc->ctx->logger);
...@@ -1974,10 +1976,9 @@ void dcn20_post_unlock_program_front_end( ...@@ -1974,10 +1976,9 @@ void dcn20_post_unlock_program_front_end(
pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
struct hubp *hubp = pipe->plane_res.hubp; struct hubp *hubp = pipe->plane_res.hubp;
int j = 0; int j = 0;
for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_US / polling_interval_us
for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
&& hubp->funcs->hubp_is_flip_pending(hubp); j++) && hubp->funcs->hubp_is_flip_pending(hubp); j++)
udelay(1); udelay(polling_interval_us);
} }
} }
......
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