Commit dbf2f8e3 authored by Mac Chiang's avatar Mac Chiang Committed by Mark Brown

ASoC: Intel: sof_rt5682: add 512FS MCLK clock configuration

codec system clock source support 512FS MCLK synchronous directly, so
no need to set PLL configuration when MCLK 24.576MHz.
Suggested-by: default avatarShuming Fan <shumingf@realtek.com>
Signed-off-by: default avatarMac Chiang <mac.chiang@intel.com>
Acked-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220120054012.15849-1-mac.chiang@intel.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 330dc183
...@@ -369,11 +369,16 @@ static int sof_rt5682_hw_params(struct snd_pcm_substream *substream, ...@@ -369,11 +369,16 @@ static int sof_rt5682_hw_params(struct snd_pcm_substream *substream,
pll_out = params_rate(params) * 512; pll_out = params_rate(params) * 512;
/* Configure pll for codec */ /* when MCLK is 512FS, no need to set PLL configuration additionally. */
ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source, pll_in, if (pll_in == pll_out)
pll_out); clk_id = RT5682S_SCLK_S_MCLK;
if (ret < 0) else {
dev_err(rtd->dev, "snd_soc_dai_set_pll err = %d\n", ret); /* Configure pll for codec */
ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source, pll_in,
pll_out);
if (ret < 0)
dev_err(rtd->dev, "snd_soc_dai_set_pll err = %d\n", ret);
}
/* Configure sysclk for codec */ /* Configure sysclk for codec */
ret = snd_soc_dai_set_sysclk(codec_dai, clk_id, ret = snd_soc_dai_set_sysclk(codec_dai, clk_id,
......
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