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Commit dc185ae6 authored by David S. Miller's avatar David S. Miller
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Merge branch 'hns3-debugfs' 

Huazhong Tan says:

====================
net: hns3: refactor some debugfs commands

This series refactors the debugfs command to the new
process and removes the useless debugfs file node cmd
for the HNS3 ethernet driver.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 2682ea32 b4689aaf
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Showing with 1585 additions and 1037 deletions
drivers/net/ethernet/hisilicon/hns3/hnae3.h
View file @ dc185ae6
......@@ -254,6 +254,13 @@ enum hnae3_dbg_cmd {
HNAE3_DBG_CMD_TM_NODES,
HNAE3_DBG_CMD_TM_PRI,
HNAE3_DBG_CMD_TM_QSET,
HNAE3_DBG_CMD_TM_MAP,
HNAE3_DBG_CMD_TM_PG,
HNAE3_DBG_CMD_TM_PORT,
HNAE3_DBG_CMD_TC_SCH_INFO,
HNAE3_DBG_CMD_QOS_PAUSE_CFG,
HNAE3_DBG_CMD_QOS_PRI_MAP,
HNAE3_DBG_CMD_QOS_BUF_CFG,
HNAE3_DBG_CMD_DEV_INFO,
HNAE3_DBG_CMD_TX_BD,
HNAE3_DBG_CMD_RX_BD,
......@@ -265,6 +272,23 @@ enum hnae3_dbg_cmd {
HNAE3_DBG_CMD_RESET_INFO,
HNAE3_DBG_CMD_IMP_INFO,
HNAE3_DBG_CMD_NCL_CONFIG,
HNAE3_DBG_CMD_REG_BIOS_COMMON,
HNAE3_DBG_CMD_REG_SSU,
HNAE3_DBG_CMD_REG_IGU_EGU,
HNAE3_DBG_CMD_REG_RPU,
HNAE3_DBG_CMD_REG_NCSI,
HNAE3_DBG_CMD_REG_RTC,
HNAE3_DBG_CMD_REG_PPP,
HNAE3_DBG_CMD_REG_RCB,
HNAE3_DBG_CMD_REG_TQP,
HNAE3_DBG_CMD_REG_MAC,
HNAE3_DBG_CMD_REG_DCB,
HNAE3_DBG_CMD_QUEUE_MAP,
HNAE3_DBG_CMD_RX_QUEUE_INFO,
HNAE3_DBG_CMD_TX_QUEUE_INFO,
HNAE3_DBG_CMD_FD_TCAM,
HNAE3_DBG_CMD_MAC_TNL_STATUS,
HNAE3_DBG_CMD_SERV_INFO,
HNAE3_DBG_CMD_UNKNOWN,
};
......@@ -644,7 +668,6 @@ struct hnae3_ae_ops {
void (*enable_fd)(struct hnae3_handle *handle, bool enable);
int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id,
u16 flow_id, struct flow_keys *fkeys);
int (*dbg_run_cmd)(struct hnae3_handle *handle, const char *cmd_buf);
int (*dbg_read_cmd)(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
char *buf, int len);
pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev);
......
drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
View file @ dc185ae6
......@@ -23,6 +23,15 @@ static struct hns3_dbg_dentry_info hns3_dbg_dentry[] = {
{
.name = "mac_list"
},
{
.name = "reg"
},
{
.name = "queue"
},
{
.name = "fd"
},
/* keep common at the bottom and add new directory above */
{
.name = "common"
......@@ -55,6 +64,55 @@ static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "tm_map",
.cmd = HNAE3_DBG_CMD_TM_MAP,
.dentry = HNS3_DBG_DENTRY_TM,
.buf_len = HNS3_DBG_READ_LEN_1MB,
.init = hns3_dbg_common_file_init,
},
{
.name = "tm_pg",
.cmd = HNAE3_DBG_CMD_TM_PG,
.dentry = HNS3_DBG_DENTRY_TM,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "tm_port",
.cmd = HNAE3_DBG_CMD_TM_PORT,
.dentry = HNS3_DBG_DENTRY_TM,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "tc_sch_info",
.cmd = HNAE3_DBG_CMD_TC_SCH_INFO,
.dentry = HNS3_DBG_DENTRY_TM,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "qos_pause_cfg",
.cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG,
.dentry = HNS3_DBG_DENTRY_TM,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "qos_pri_map",
.cmd = HNAE3_DBG_CMD_QOS_PRI_MAP,
.dentry = HNS3_DBG_DENTRY_TM,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "qos_buf_cfg",
.cmd = HNAE3_DBG_CMD_QOS_BUF_CFG,
.dentry = HNS3_DBG_DENTRY_TM,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "dev_info",
.cmd = HNAE3_DBG_CMD_DEV_INFO,
......@@ -132,6 +190,125 @@ static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
.buf_len = HNS3_DBG_READ_LEN_128KB,
.init = hns3_dbg_common_file_init,
},
{
.name = "mac_tnl_status",
.cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS,
.dentry = HNS3_DBG_DENTRY_COMMON,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "bios_common",
.cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON,
.dentry = HNS3_DBG_DENTRY_REG,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "ssu",
.cmd = HNAE3_DBG_CMD_REG_SSU,
.dentry = HNS3_DBG_DENTRY_REG,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "igu_egu",
.cmd = HNAE3_DBG_CMD_REG_IGU_EGU,
.dentry = HNS3_DBG_DENTRY_REG,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "rpu",
.cmd = HNAE3_DBG_CMD_REG_RPU,
.dentry = HNS3_DBG_DENTRY_REG,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "ncsi",
.cmd = HNAE3_DBG_CMD_REG_NCSI,
.dentry = HNS3_DBG_DENTRY_REG,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "rtc",
.cmd = HNAE3_DBG_CMD_REG_RTC,
.dentry = HNS3_DBG_DENTRY_REG,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "ppp",
.cmd = HNAE3_DBG_CMD_REG_PPP,
.dentry = HNS3_DBG_DENTRY_REG,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "rcb",
.cmd = HNAE3_DBG_CMD_REG_RCB,
.dentry = HNS3_DBG_DENTRY_REG,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "tqp",
.cmd = HNAE3_DBG_CMD_REG_TQP,
.dentry = HNS3_DBG_DENTRY_REG,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "mac",
.cmd = HNAE3_DBG_CMD_REG_MAC,
.dentry = HNS3_DBG_DENTRY_REG,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "dcb",
.cmd = HNAE3_DBG_CMD_REG_DCB,
.dentry = HNS3_DBG_DENTRY_REG,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "queue_map",
.cmd = HNAE3_DBG_CMD_QUEUE_MAP,
.dentry = HNS3_DBG_DENTRY_QUEUE,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "rx_queue_info",
.cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO,
.dentry = HNS3_DBG_DENTRY_QUEUE,
.buf_len = HNS3_DBG_READ_LEN_1MB,
.init = hns3_dbg_common_file_init,
},
{
.name = "tx_queue_info",
.cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO,
.dentry = HNS3_DBG_DENTRY_QUEUE,
.buf_len = HNS3_DBG_READ_LEN_1MB,
.init = hns3_dbg_common_file_init,
},
{
.name = "fd_tcam",
.cmd = HNAE3_DBG_CMD_FD_TCAM,
.dentry = HNS3_DBG_DENTRY_FD,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
{
.name = "service_task_info",
.cmd = HNAE3_DBG_CMD_SERV_INFO,
.dentry = HNS3_DBG_DENTRY_COMMON,
.buf_len = HNS3_DBG_READ_LEN,
.init = hns3_dbg_common_file_init,
},
};
static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
......@@ -192,39 +369,86 @@ static void hns3_dbg_fill_content(char *content, u16 len,
*pos++ = '\0';
}
static int hns3_dbg_queue_info(struct hnae3_handle *h,
const char *cmd_buf)
static const struct hns3_dbg_item rx_queue_info_items[] = {
{ "QUEUE_ID", 2 },
{ "BD_NUM", 2 },
{ "BD_LEN", 2 },
{ "TAIL", 2 },
{ "HEAD", 2 },
{ "FBDNUM", 2 },
{ "PKTNUM", 2 },
{ "RING_EN", 2 },
{ "RX_RING_EN", 2 },
{ "BASE_ADDR", 10 },
};
static void hns3_dump_rx_queue_info(struct hns3_enet_ring *ring,
struct hnae3_ae_dev *ae_dev, char **result,
u32 index)
{
u32 base_add_l, base_add_h;
u32 j = 0;
sprintf(result[j++], "%8u", index);
sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_BD_NUM_REG));
sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_BD_LEN_REG));
sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_TAIL_REG));
sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_HEAD_REG));
sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_FBDNUM_REG));
sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_PKTNUM_RECORD_REG));
sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base +
HNS3_RING_EN_REG) ? "on" : "off");
if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev))
sprintf(result[j++], "%10s", readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_EN_REG) ? "on" : "off");
else
sprintf(result[j++], "%10s", "NA");
base_add_h = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_BASEADDR_H_REG);
base_add_l = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_BASEADDR_L_REG);
sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l);
}
static int hns3_dbg_rx_queue_info(struct hnae3_handle *h,
char *buf, int len)
{
char data_str[ARRAY_SIZE(rx_queue_info_items)][HNS3_DBG_DATA_STR_LEN];
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
char *result[ARRAY_SIZE(rx_queue_info_items)];
struct hns3_nic_priv *priv = h->priv;
char content[HNS3_DBG_INFO_LEN];
struct hns3_enet_ring *ring;
u32 base_add_l, base_add_h;
u32 queue_num, queue_max;
u32 value, i;
int cnt;
int pos = 0;
u32 i;
if (!priv->ring) {
dev_err(&h->pdev->dev, "priv->ring is NULL\n");
return -EFAULT;
}
queue_max = h->kinfo.num_tqps;
cnt = kstrtouint(&cmd_buf[11], 0, &queue_num);
if (cnt)
queue_num = 0;
else
queue_max = queue_num + 1;
dev_info(&h->pdev->dev, "queue info\n");
if (queue_num >= h->kinfo.num_tqps) {
dev_err(&h->pdev->dev,
"Queue number(%u) is out of range(0-%u)\n", queue_num,
h->kinfo.num_tqps - 1);
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(rx_queue_info_items); i++)
result[i] = &data_str[i][0];
for (i = queue_num; i < queue_max; i++) {
hns3_dbg_fill_content(content, sizeof(content), rx_queue_info_items,
NULL, ARRAY_SIZE(rx_queue_info_items));
pos += scnprintf(buf + pos, len - pos, "%s", content);
for (i = 0; i < h->kinfo.num_tqps; i++) {
/* Each cycle needs to determine whether the instance is reset,
* to prevent reference to invalid memory. And need to ensure
* that the following code is executed within 100ms.
......@@ -234,116 +458,159 @@ static int hns3_dbg_queue_info(struct hnae3_handle *h,
return -EPERM;
ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)];
base_add_h = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_BASEADDR_H_REG);
base_add_l = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_BASEADDR_L_REG);
dev_info(&h->pdev->dev, "RX(%u) BASE ADD: 0x%08x%08x\n", i,
base_add_h, base_add_l);
hns3_dump_rx_queue_info(ring, ae_dev, result, i);
hns3_dbg_fill_content(content, sizeof(content),
rx_queue_info_items,
(const char **)result,
ARRAY_SIZE(rx_queue_info_items));
pos += scnprintf(buf + pos, len - pos, "%s", content);
}
return 0;
}
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_BD_NUM_REG);
dev_info(&h->pdev->dev, "RX(%u) RING BD NUM: %u\n", i, value);
static const struct hns3_dbg_item tx_queue_info_items[] = {
{ "QUEUE_ID", 2 },
{ "BD_NUM", 2 },
{ "TC", 2 },
{ "TAIL", 2 },
{ "HEAD", 2 },
{ "FBDNUM", 2 },
{ "OFFSET", 2 },
{ "PKTNUM", 2 },
{ "RING_EN", 2 },
{ "TX_RING_EN", 2 },
{ "BASE_ADDR", 10 },
};
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_BD_LEN_REG);
dev_info(&h->pdev->dev, "RX(%u) RING BD LEN: %u\n", i, value);
static void hns3_dump_tx_queue_info(struct hns3_enet_ring *ring,
struct hnae3_ae_dev *ae_dev, char **result,
u32 index)
{
u32 base_add_l, base_add_h;
u32 j = 0;
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_TAIL_REG);
dev_info(&h->pdev->dev, "RX(%u) RING TAIL: %u\n", i, value);
sprintf(result[j++], "%8u", index);
sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_BD_NUM_REG));
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_HEAD_REG);
dev_info(&h->pdev->dev, "RX(%u) RING HEAD: %u\n", i, value);
sprintf(result[j++], "%2u", readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_TC_REG));
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_FBDNUM_REG);
dev_info(&h->pdev->dev, "RX(%u) RING FBDNUM: %u\n", i, value);
sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_TAIL_REG));
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_PKTNUM_RECORD_REG);
dev_info(&h->pdev->dev, "RX(%u) RING PKTNUM: %u\n", i, value);
sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_HEAD_REG));
sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_FBDNUM_REG));
sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_OFFSET_REG));
sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_PKTNUM_RECORD_REG));
sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base +
HNS3_RING_EN_REG) ? "on" : "off");
if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev))
sprintf(result[j++], "%10s", readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_EN_REG) ? "on" : "off");
else
sprintf(result[j++], "%10s", "NA");
ring = &priv->ring[i];
base_add_h = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_BASEADDR_H_REG);
base_add_l = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_BASEADDR_L_REG);
dev_info(&h->pdev->dev, "TX(%u) BASE ADD: 0x%08x%08x\n", i,
base_add_h, base_add_l);
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_BD_NUM_REG);
dev_info(&h->pdev->dev, "TX(%u) RING BD NUM: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_TC_REG);
dev_info(&h->pdev->dev, "TX(%u) RING TC: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_TAIL_REG);
dev_info(&h->pdev->dev, "TX(%u) RING TAIL: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_HEAD_REG);
dev_info(&h->pdev->dev, "TX(%u) RING HEAD: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_FBDNUM_REG);
dev_info(&h->pdev->dev, "TX(%u) RING FBDNUM: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_OFFSET_REG);
dev_info(&h->pdev->dev, "TX(%u) RING OFFSET: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_PKTNUM_RECORD_REG);
dev_info(&h->pdev->dev, "TX(%u) RING PKTNUM: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base + HNS3_RING_EN_REG);
dev_info(&h->pdev->dev, "TX/RX(%u) RING EN: %s\n", i,
value ? "enable" : "disable");
if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) {
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_EN_REG);
dev_info(&h->pdev->dev, "TX(%u) RING EN: %s\n", i,
value ? "enable" : "disable");
value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_EN_REG);
dev_info(&h->pdev->dev, "RX(%u) RING EN: %s\n", i,
value ? "enable" : "disable");
sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l);
}
static int hns3_dbg_tx_queue_info(struct hnae3_handle *h,
char *buf, int len)
{
char data_str[ARRAY_SIZE(tx_queue_info_items)][HNS3_DBG_DATA_STR_LEN];
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
char *result[ARRAY_SIZE(tx_queue_info_items)];
struct hns3_nic_priv *priv = h->priv;
char content[HNS3_DBG_INFO_LEN];
struct hns3_enet_ring *ring;
int pos = 0;
u32 i;
if (!priv->ring) {
dev_err(&h->pdev->dev, "priv->ring is NULL\n");
return -EFAULT;
}
dev_info(&h->pdev->dev, "\n");
for (i = 0; i < ARRAY_SIZE(tx_queue_info_items); i++)
result[i] = &data_str[i][0];
hns3_dbg_fill_content(content, sizeof(content), tx_queue_info_items,
NULL, ARRAY_SIZE(tx_queue_info_items));
pos += scnprintf(buf + pos, len - pos, "%s", content);
for (i = 0; i < h->kinfo.num_tqps; i++) {
/* Each cycle needs to determine whether the instance is reset,
* to prevent reference to invalid memory. And need to ensure
* that the following code is executed within 100ms.
*/
if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
return -EPERM;
ring = &priv->ring[i];
hns3_dump_tx_queue_info(ring, ae_dev, result, i);
hns3_dbg_fill_content(content, sizeof(content),
tx_queue_info_items,
(const char **)result,
ARRAY_SIZE(tx_queue_info_items));
pos += scnprintf(buf + pos, len - pos, "%s", content);
}
return 0;
}
static int hns3_dbg_queue_map(struct hnae3_handle *h)
static const struct hns3_dbg_item queue_map_items[] = {
{ "local_queue_id", 2 },
{ "global_queue_id", 2 },
{ "vector_id", 2 },
};
static int hns3_dbg_queue_map(struct hnae3_handle *h, char *buf, int len)
{
char data_str[ARRAY_SIZE(queue_map_items)][HNS3_DBG_DATA_STR_LEN];
char *result[ARRAY_SIZE(queue_map_items)];
struct hns3_nic_priv *priv = h->priv;
int i;
char content[HNS3_DBG_INFO_LEN];
int pos = 0;
int j;
u32 i;
if (!h->ae_algo->ops->get_global_queue_id)
return -EOPNOTSUPP;
dev_info(&h->pdev->dev, "map info for queue id and vector id\n");
dev_info(&h->pdev->dev,
"local queue id | global queue id | vector id\n");
for (i = 0; i < h->kinfo.num_tqps; i++) {
u16 global_qid;
for (i = 0; i < ARRAY_SIZE(queue_map_items); i++)
result[i] = &data_str[i][0];
global_qid = h->ae_algo->ops->get_global_queue_id(h, i);
hns3_dbg_fill_content(content, sizeof(content), queue_map_items,
NULL, ARRAY_SIZE(queue_map_items));
pos += scnprintf(buf + pos, len - pos, "%s", content);
for (i = 0; i < h->kinfo.num_tqps; i++) {
if (!priv->ring || !priv->ring[i].tqp_vector)
continue;
dev_info(&h->pdev->dev,
" %4d %4u %4d\n",
i, global_qid, priv->ring[i].tqp_vector->vector_irq);
j = 0;
sprintf(result[j++], "%u", i);
sprintf(result[j++], "%u",
h->ae_algo->ops->get_global_queue_id(h, i));
sprintf(result[j++], "%u",
priv->ring[i].tqp_vector->vector_irq);
hns3_dbg_fill_content(content, sizeof(content), queue_map_items,
(const char **)result,
ARRAY_SIZE(queue_map_items));
pos += scnprintf(buf + pos, len - pos, "%s", content);
}
return 0;
......@@ -506,48 +773,6 @@ static int hns3_dbg_tx_bd_info(struct hns3_dbg_data *d, char *buf, int len)
return 0;
}
static void hns3_dbg_help(struct hnae3_handle *h)
{
#define HNS3_DBG_BUF_LEN 256
char printf_buf[HNS3_DBG_BUF_LEN];
dev_info(&h->pdev->dev, "available commands\n");
dev_info(&h->pdev->dev, "queue info <number>\n");
dev_info(&h->pdev->dev, "queue map\n");
if (!hns3_is_phys_func(h->pdev))
return;
dev_info(&h->pdev->dev, "dump fd tcam\n");
dev_info(&h->pdev->dev, "dump tc\n");
dev_info(&h->pdev->dev, "dump tm map <q_num>\n");
dev_info(&h->pdev->dev, "dump tm\n");
dev_info(&h->pdev->dev, "dump qos pause cfg\n");
dev_info(&h->pdev->dev, "dump qos pri map\n");
dev_info(&h->pdev->dev, "dump qos buf cfg\n");
dev_info(&h->pdev->dev, "dump mac tnl status\n");
dev_info(&h->pdev->dev, "dump qs shaper [qs id]\n");
memset(printf_buf, 0, HNS3_DBG_BUF_LEN);
strncat(printf_buf, "dump reg [[bios common] [ssu <port_id>]",
HNS3_DBG_BUF_LEN - 1);
strncat(printf_buf + strlen(printf_buf),
" [igu egu <port_id>] [rpu <tc_queue_num>]",
HNS3_DBG_BUF_LEN - strlen(printf_buf) - 1);
strncat(printf_buf + strlen(printf_buf),
" [rtc] [ppp] [rcb] [tqp <queue_num>] [mac]]\n",
HNS3_DBG_BUF_LEN - strlen(printf_buf) - 1);
dev_info(&h->pdev->dev, "%s", printf_buf);
memset(printf_buf, 0, HNS3_DBG_BUF_LEN);
strncat(printf_buf, "dump reg dcb <port_id> <pri_id> <pg_id>",
HNS3_DBG_BUF_LEN - 1);
strncat(printf_buf + strlen(printf_buf), " <rq_id> <nq_id> <qset_id>\n",
HNS3_DBG_BUF_LEN - strlen(printf_buf) - 1);
dev_info(&h->pdev->dev, "%s", printf_buf);
}
static void
hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos)
{
......@@ -622,101 +847,6 @@ static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len)
return 0;
}
static ssize_t hns3_dbg_cmd_read(struct file *filp, char __user *buffer,
size_t count, loff_t *ppos)
{
int uncopy_bytes;
char *buf;
int len;
if (*ppos != 0)
return 0;
if (count < HNS3_DBG_READ_LEN)
return -ENOSPC;
buf = kzalloc(HNS3_DBG_READ_LEN, GFP_KERNEL);
if (!buf)
return -ENOMEM;
len = scnprintf(buf, HNS3_DBG_READ_LEN, "%s\n",
"Please echo help to cmd to get help information");
uncopy_bytes = copy_to_user(buffer, buf, len);
kfree(buf);
if (uncopy_bytes)
return -EFAULT;
return (*ppos = len);
}
static int hns3_dbg_check_cmd(struct hnae3_handle *handle, char *cmd_buf)
{
int ret = 0;
if (strncmp(cmd_buf, "help", 4) == 0)
hns3_dbg_help(handle);
else if (strncmp(cmd_buf, "queue info", 10) == 0)
ret = hns3_dbg_queue_info(handle, cmd_buf);
else if (strncmp(cmd_buf, "queue map", 9) == 0)
ret = hns3_dbg_queue_map(handle);
else if (handle->ae_algo->ops->dbg_run_cmd)
ret = handle->ae_algo->ops->dbg_run_cmd(handle, cmd_buf);
else
ret = -EOPNOTSUPP;
return ret;
}
static ssize_t hns3_dbg_cmd_write(struct file *filp, const char __user *buffer,
size_t count, loff_t *ppos)
{
struct hnae3_handle *handle = filp->private_data;
struct hns3_nic_priv *priv = handle->priv;
char *cmd_buf, *cmd_buf_tmp;
int uncopied_bytes;
int ret;
if (*ppos != 0)
return 0;
/* Judge if the instance is being reset. */
if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
return 0;
if (count > HNS3_DBG_WRITE_LEN)
return -ENOSPC;
cmd_buf = kzalloc(count + 1, GFP_KERNEL);
if (!cmd_buf)
return count;
uncopied_bytes = copy_from_user(cmd_buf, buffer, count);
if (uncopied_bytes) {
kfree(cmd_buf);
return -EFAULT;
}
cmd_buf[count] = '\0';
cmd_buf_tmp = strchr(cmd_buf, '\n');
if (cmd_buf_tmp) {
*cmd_buf_tmp = '\0';
count = cmd_buf_tmp - cmd_buf + 1;
}
ret = hns3_dbg_check_cmd(handle, cmd_buf);
if (ret)
hns3_dbg_help(handle);
kfree(cmd_buf);
cmd_buf = NULL;
return count;
}
static int hns3_dbg_get_cmd_index(struct hnae3_handle *handle,
const unsigned char *name, u32 *index)
{
......@@ -735,6 +865,10 @@ static int hns3_dbg_get_cmd_index(struct hnae3_handle *handle,
}
static const struct hns3_dbg_func hns3_dbg_cmd_func[] = {
{
.cmd = HNAE3_DBG_CMD_QUEUE_MAP,
.dbg_dump = hns3_dbg_queue_map,
},
{
.cmd = HNAE3_DBG_CMD_DEV_INFO,
.dbg_dump = hns3_dbg_dev_info,
......@@ -747,6 +881,14 @@ static const struct hns3_dbg_func hns3_dbg_cmd_func[] = {
.cmd = HNAE3_DBG_CMD_RX_BD,
.dbg_dump_bd = hns3_dbg_rx_bd_info,
},
{
.cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO,
.dbg_dump = hns3_dbg_rx_queue_info,
},
{
.cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO,
.dbg_dump = hns3_dbg_tx_queue_info,
},
};
static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data,
......@@ -833,13 +975,6 @@ static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer,
return ret;
}
static const struct file_operations hns3_dbg_cmd_fops = {
.owner = THIS_MODULE,
.open = simple_open,
.read = hns3_dbg_cmd_read,
.write = hns3_dbg_cmd_write,
};
static const struct file_operations hns3_dbg_fops = {
.owner = THIS_MODULE,
.open = simple_open,
......@@ -902,9 +1037,6 @@ int hns3_dbg_init(struct hnae3_handle *handle)
debugfs_create_dir(name, hns3_dbgfs_root);
handle->hnae3_dbgfs = hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry;
debugfs_create_file("cmd", 0600, handle->hnae3_dbgfs, handle,
&hns3_dbg_cmd_fops);
for (i = 0; i < HNS3_DBG_DENTRY_COMMON; i++)
hns3_dbg_dentry[i].dentry =
debugfs_create_dir(hns3_dbg_dentry[i].name,
......
drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h
View file @ dc185ae6
......@@ -6,6 +6,7 @@
#define HNS3_DBG_READ_LEN 65536
#define HNS3_DBG_READ_LEN_128KB 0x20000
#define HNS3_DBG_READ_LEN_1MB 0x100000
#define HNS3_DBG_READ_LEN_4MB 0x400000
#define HNS3_DBG_WRITE_LEN 1024
......@@ -29,6 +30,9 @@ enum hns3_dbg_dentry_type {
HNS3_DBG_DENTRY_TX_BD,
HNS3_DBG_DENTRY_RX_BD,
HNS3_DBG_DENTRY_MAC,
HNS3_DBG_DENTRY_REG,
HNS3_DBG_DENTRY_QUEUE,
HNS3_DBG_DENTRY_FD,
HNS3_DBG_DENTRY_COMMON,
};
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
View file @ dc185ae6
......@@ -15,62 +15,62 @@ static const char * const hclge_mac_state_str[] = {
};
static const struct hclge_dbg_reg_type_info hclge_dbg_reg_info[] = {
{ .reg_type = "bios common",
{ .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON,
.dfx_msg = &hclge_dbg_bios_common_reg[0],
.reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_bios_common_reg),
.offset = HCLGE_DBG_DFX_BIOS_OFFSET,
.cmd = HCLGE_OPC_DFX_BIOS_COMMON_REG } },
{ .reg_type = "ssu",
{ .cmd = HNAE3_DBG_CMD_REG_SSU,
.dfx_msg = &hclge_dbg_ssu_reg_0[0],
.reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_0),
.offset = HCLGE_DBG_DFX_SSU_0_OFFSET,
.cmd = HCLGE_OPC_DFX_SSU_REG_0 } },
{ .reg_type = "ssu",
{ .cmd = HNAE3_DBG_CMD_REG_SSU,
.dfx_msg = &hclge_dbg_ssu_reg_1[0],
.reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_1),
.offset = HCLGE_DBG_DFX_SSU_1_OFFSET,
.cmd = HCLGE_OPC_DFX_SSU_REG_1 } },
{ .reg_type = "ssu",
{ .cmd = HNAE3_DBG_CMD_REG_SSU,
.dfx_msg = &hclge_dbg_ssu_reg_2[0],
.reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_2),
.offset = HCLGE_DBG_DFX_SSU_2_OFFSET,
.cmd = HCLGE_OPC_DFX_SSU_REG_2 } },
{ .reg_type = "igu egu",
{ .cmd = HNAE3_DBG_CMD_REG_IGU_EGU,
.dfx_msg = &hclge_dbg_igu_egu_reg[0],
.reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_igu_egu_reg),
.offset = HCLGE_DBG_DFX_IGU_OFFSET,
.cmd = HCLGE_OPC_DFX_IGU_EGU_REG } },
{ .reg_type = "rpu",
{ .cmd = HNAE3_DBG_CMD_REG_RPU,
.dfx_msg = &hclge_dbg_rpu_reg_0[0],
.reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rpu_reg_0),
.offset = HCLGE_DBG_DFX_RPU_0_OFFSET,
.cmd = HCLGE_OPC_DFX_RPU_REG_0 } },
{ .reg_type = "rpu",
{ .cmd = HNAE3_DBG_CMD_REG_RPU,
.dfx_msg = &hclge_dbg_rpu_reg_1[0],
.reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rpu_reg_1),
.offset = HCLGE_DBG_DFX_RPU_1_OFFSET,
.cmd = HCLGE_OPC_DFX_RPU_REG_1 } },
{ .reg_type = "ncsi",
{ .cmd = HNAE3_DBG_CMD_REG_NCSI,
.dfx_msg = &hclge_dbg_ncsi_reg[0],
.reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ncsi_reg),
.offset = HCLGE_DBG_DFX_NCSI_OFFSET,
.cmd = HCLGE_OPC_DFX_NCSI_REG } },
{ .reg_type = "rtc",
{ .cmd = HNAE3_DBG_CMD_REG_RTC,
.dfx_msg = &hclge_dbg_rtc_reg[0],
.reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rtc_reg),
.offset = HCLGE_DBG_DFX_RTC_OFFSET,
.cmd = HCLGE_OPC_DFX_RTC_REG } },
{ .reg_type = "ppp",
{ .cmd = HNAE3_DBG_CMD_REG_PPP,
.dfx_msg = &hclge_dbg_ppp_reg[0],
.reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ppp_reg),
.offset = HCLGE_DBG_DFX_PPP_OFFSET,
.cmd = HCLGE_OPC_DFX_PPP_REG } },
{ .reg_type = "rcb",
{ .cmd = HNAE3_DBG_CMD_REG_RCB,
.dfx_msg = &hclge_dbg_rcb_reg[0],
.reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rcb_reg),
.offset = HCLGE_DBG_DFX_RCB_OFFSET,
.cmd = HCLGE_OPC_DFX_RCB_REG } },
{ .reg_type = "tqp",
{ .cmd = HNAE3_DBG_CMD_REG_TQP,
.dfx_msg = &hclge_dbg_tqp_reg[0],
.reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_tqp_reg),
.offset = HCLGE_DBG_DFX_TQP_OFFSET,
......@@ -106,7 +106,8 @@ static char *hclge_dbg_get_func_id_str(char *buf, u8 id)
return buf;
}
static int hclge_dbg_get_dfx_bd_num(struct hclge_dev *hdev, int offset)
static int hclge_dbg_get_dfx_bd_num(struct hclge_dev *hdev, int offset,
u32 *bd_num)
{
struct hclge_desc desc[HCLGE_GET_DFX_REG_TYPE_CNT];
int entries_per_desc;
......@@ -116,13 +117,21 @@ static int hclge_dbg_get_dfx_bd_num(struct hclge_dev *hdev, int offset)
ret = hclge_query_bd_num_cmd_send(hdev, desc);
if (ret) {
dev_err(&hdev->pdev->dev,
"get dfx bdnum fail, ret = %d\n", ret);
"failed to get dfx bd_num, offset = %d, ret = %d\n",
offset, ret);
return ret;
}
entries_per_desc = ARRAY_SIZE(desc[0].data);
index = offset % entries_per_desc;
return le32_to_cpu(desc[offset / entries_per_desc].data[index]);
*bd_num = le32_to_cpu(desc[offset / entries_per_desc].data[index]);
if (!(*bd_num)) {
dev_err(&hdev->pdev->dev, "The value of dfx bd_num is 0!\n");
return -EINVAL;
}
return 0;
}
static int hclge_dbg_cmd_send(struct hclge_dev *hdev,
......@@ -149,66 +158,108 @@ static int hclge_dbg_cmd_send(struct hclge_dev *hdev,
return ret;
}
static void hclge_dbg_dump_reg_common(struct hclge_dev *hdev,
static int
hclge_dbg_dump_reg_tqp(struct hclge_dev *hdev,
const struct hclge_dbg_reg_type_info *reg_info,
const char *cmd_buf)
char *buf, int len, int *pos)
{
#define IDX_OFFSET 1
const char *s = &cmd_buf[strlen(reg_info->reg_type) + IDX_OFFSET];
const struct hclge_dbg_dfx_message *dfx_message = reg_info->dfx_msg;
const struct hclge_dbg_reg_common_msg *reg_msg = &reg_info->reg_msg;
struct hclge_desc *desc_src;
u32 index, entry, i, cnt;
int bd_num, min_num, ret;
struct hclge_desc *desc;
int entries_per_desc;
int bd_num, buf_len;
int index = 0;
int min_num;
int ret, i;
if (*s) {
ret = kstrtouint(s, 0, &index);
index = (ret != 0) ? 0 : index;
}
ret = hclge_dbg_get_dfx_bd_num(hdev, reg_msg->offset, &bd_num);
if (ret)
return ret;
bd_num = hclge_dbg_get_dfx_bd_num(hdev, reg_msg->offset);
if (bd_num <= 0) {
dev_err(&hdev->pdev->dev, "get cmd(%d) bd num(%d) failed\n",
reg_msg->offset, bd_num);
return;
desc_src = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL);
if (!desc_src)
return -ENOMEM;
min_num = min_t(int, bd_num * HCLGE_DESC_DATA_LEN, reg_msg->msg_num);
for (i = 0, cnt = 0; i < min_num; i++, dfx_message++)
*pos += scnprintf(buf + *pos, len - *pos, "item%u = %s\n",
cnt++, dfx_message->message);
for (i = 0; i < cnt; i++)
*pos += scnprintf(buf + *pos, len - *pos, "item%u\t", i);
*pos += scnprintf(buf + *pos, len - *pos, "\n");
for (index = 0; index < hdev->vport[0].alloc_tqps; index++) {
dfx_message = reg_info->dfx_msg;
desc = desc_src;
ret = hclge_dbg_cmd_send(hdev, desc, index, bd_num,
reg_msg->cmd);
if (ret)
break;
for (i = 0; i < min_num; i++, dfx_message++) {
entry = i % HCLGE_DESC_DATA_LEN;
if (i > 0 && !entry)
desc++;
*pos += scnprintf(buf + *pos, len - *pos, "%#x\t",
le32_to_cpu(desc->data[entry]));
}
*pos += scnprintf(buf + *pos, len - *pos, "\n");
}
kfree(desc_src);
return ret;
}
buf_len = sizeof(struct hclge_desc) * bd_num;
desc_src = kzalloc(buf_len, GFP_KERNEL);
static int
hclge_dbg_dump_reg_common(struct hclge_dev *hdev,
const struct hclge_dbg_reg_type_info *reg_info,
char *buf, int len, int *pos)
{
const struct hclge_dbg_reg_common_msg *reg_msg = &reg_info->reg_msg;
const struct hclge_dbg_dfx_message *dfx_message = reg_info->dfx_msg;
struct hclge_desc *desc_src;
int bd_num, min_num, ret;
struct hclge_desc *desc;
u32 entry, i;
ret = hclge_dbg_get_dfx_bd_num(hdev, reg_msg->offset, &bd_num);
if (ret)
return ret;
desc_src = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL);
if (!desc_src)
return;
return -ENOMEM;
desc = desc_src;
ret = hclge_dbg_cmd_send(hdev, desc, index, bd_num, reg_msg->cmd);
ret = hclge_dbg_cmd_send(hdev, desc, 0, bd_num, reg_msg->cmd);
if (ret) {
kfree(desc_src);
return;
kfree(desc);
return ret;
}
entries_per_desc = ARRAY_SIZE(desc->data);
min_num = min_t(int, bd_num * entries_per_desc, reg_msg->msg_num);
min_num = min_t(int, bd_num * HCLGE_DESC_DATA_LEN, reg_msg->msg_num);
desc = desc_src;
for (i = 0; i < min_num; i++) {
if (i > 0 && (i % entries_per_desc) == 0)
for (i = 0; i < min_num; i++, dfx_message++) {
entry = i % HCLGE_DESC_DATA_LEN;
if (i > 0 && !entry)
desc++;
if (dfx_message->flag)
dev_info(&hdev->pdev->dev, "%s: 0x%x\n",
dfx_message->message,
le32_to_cpu(desc->data[i % entries_per_desc]));
if (!dfx_message->flag)
continue;
dfx_message++;
*pos += scnprintf(buf + *pos, len - *pos, "%s: %#x\n",
dfx_message->message,
le32_to_cpu(desc->data[entry]));
}
kfree(desc_src);
return 0;
}
static void hclge_dbg_dump_mac_enable_status(struct hclge_dev *hdev)
static int hclge_dbg_dump_mac_enable_status(struct hclge_dev *hdev, char *buf,
int len, int *pos)
{
struct hclge_config_mac_mode_cmd *req;
struct hclge_desc desc;
......@@ -221,43 +272,51 @@ static void hclge_dbg_dump_mac_enable_status(struct hclge_dev *hdev)
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to dump mac enable status, ret = %d\n", ret);
return;
return ret;
}
req = (struct hclge_config_mac_mode_cmd *)desc.data;
loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
dev_info(&hdev->pdev->dev, "config_mac_trans_en: %#x\n",
*pos += scnprintf(buf + *pos, len - *pos, "mac_trans_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_TX_EN_B));
dev_info(&hdev->pdev->dev, "config_mac_rcv_en: %#x\n",
*pos += scnprintf(buf + *pos, len - *pos, "mac_rcv_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_RX_EN_B));
dev_info(&hdev->pdev->dev, "config_pad_trans_en: %#x\n",
*pos += scnprintf(buf + *pos, len - *pos, "pad_trans_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_PAD_TX_B));
dev_info(&hdev->pdev->dev, "config_pad_rcv_en: %#x\n",
*pos += scnprintf(buf + *pos, len - *pos, "pad_rcv_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_PAD_RX_B));
dev_info(&hdev->pdev->dev, "config_1588_trans_en: %#x\n",
*pos += scnprintf(buf + *pos, len - *pos, "1588_trans_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_1588_TX_B));
dev_info(&hdev->pdev->dev, "config_1588_rcv_en: %#x\n",
*pos += scnprintf(buf + *pos, len - *pos, "1588_rcv_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_1588_RX_B));
dev_info(&hdev->pdev->dev, "config_mac_app_loop_en: %#x\n",
*pos += scnprintf(buf + *pos, len - *pos, "mac_app_loop_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_APP_LP_B));
dev_info(&hdev->pdev->dev, "config_mac_line_loop_en: %#x\n",
*pos += scnprintf(buf + *pos, len - *pos, "mac_line_loop_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_LINE_LP_B));
dev_info(&hdev->pdev->dev, "config_mac_fcs_tx_en: %#x\n",
*pos += scnprintf(buf + *pos, len - *pos, "mac_fcs_tx_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_FCS_TX_B));
dev_info(&hdev->pdev->dev, "config_mac_rx_oversize_truncate_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B));
dev_info(&hdev->pdev->dev, "config_mac_rx_fcs_strip_en: %#x\n",
*pos += scnprintf(buf + *pos, len - *pos,
"mac_rx_oversize_truncate_en: %#x\n",
hnae3_get_bit(loop_en,
HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B));
*pos += scnprintf(buf + *pos, len - *pos, "mac_rx_fcs_strip_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B));
dev_info(&hdev->pdev->dev, "config_mac_rx_fcs_en: %#x\n",
*pos += scnprintf(buf + *pos, len - *pos, "mac_rx_fcs_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_RX_FCS_B));
dev_info(&hdev->pdev->dev, "config_mac_tx_under_min_err_en: %#x\n",
*pos += scnprintf(buf + *pos, len - *pos,
"mac_tx_under_min_err_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B));
dev_info(&hdev->pdev->dev, "config_mac_tx_oversize_truncate_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B));
*pos += scnprintf(buf + *pos, len - *pos,
"mac_tx_oversize_truncate_en: %#x\n",
hnae3_get_bit(loop_en,
HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B));
return 0;
}
static void hclge_dbg_dump_mac_frame_size(struct hclge_dev *hdev)
static int hclge_dbg_dump_mac_frame_size(struct hclge_dev *hdev, char *buf,
int len, int *pos)
{
struct hclge_config_max_frm_size_cmd *req;
struct hclge_desc desc;
......@@ -269,17 +328,21 @@ static void hclge_dbg_dump_mac_frame_size(struct hclge_dev *hdev)
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to dump mac frame size, ret = %d\n", ret);
return;
return ret;
}
req = (struct hclge_config_max_frm_size_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "max_frame_size: %u\n",
*pos += scnprintf(buf + *pos, len - *pos, "max_frame_size: %u\n",
le16_to_cpu(req->max_frm_size));
dev_info(&hdev->pdev->dev, "min_frame_size: %u\n", req->min_frm_size);
*pos += scnprintf(buf + *pos, len - *pos, "min_frame_size: %u\n",
req->min_frm_size);
return 0;
}
static void hclge_dbg_dump_mac_speed_duplex(struct hclge_dev *hdev)
static int hclge_dbg_dump_mac_speed_duplex(struct hclge_dev *hdev, char *buf,
int len, int *pos)
{
#define HCLGE_MAC_SPEED_SHIFT 0
#define HCLGE_MAC_SPEED_MASK GENMASK(5, 0)
......@@ -295,543 +358,540 @@ static void hclge_dbg_dump_mac_speed_duplex(struct hclge_dev *hdev)
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to dump mac speed duplex, ret = %d\n", ret);
return;
return ret;
}
req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "speed: %#lx\n",
*pos += scnprintf(buf + *pos, len - *pos, "speed: %#lx\n",
hnae3_get_field(req->speed_dup, HCLGE_MAC_SPEED_MASK,
HCLGE_MAC_SPEED_SHIFT));
dev_info(&hdev->pdev->dev, "duplex: %#x\n",
hnae3_get_bit(req->speed_dup, HCLGE_MAC_DUPLEX_SHIFT));
*pos += scnprintf(buf + *pos, len - *pos, "duplex: %#x\n",
hnae3_get_bit(req->speed_dup,
HCLGE_MAC_DUPLEX_SHIFT));
return 0;
}
static void hclge_dbg_dump_mac(struct hclge_dev *hdev)
static int hclge_dbg_dump_mac(struct hclge_dev *hdev, char *buf, int len)
{
hclge_dbg_dump_mac_enable_status(hdev);
int pos = 0;
int ret;
hclge_dbg_dump_mac_frame_size(hdev);
ret = hclge_dbg_dump_mac_enable_status(hdev, buf, len, &pos);
if (ret)
return ret;
hclge_dbg_dump_mac_speed_duplex(hdev);
ret = hclge_dbg_dump_mac_frame_size(hdev, buf, len, &pos);
if (ret)
return ret;
return hclge_dbg_dump_mac_speed_duplex(hdev, buf, len, &pos);
}
static void hclge_dbg_dump_dcb(struct hclge_dev *hdev, const char *cmd_buf)
static int hclge_dbg_dump_dcb_qset(struct hclge_dev *hdev, char *buf, int len,
int *pos)
{
struct device *dev = &hdev->pdev->dev;
struct hclge_dbg_bitmap_cmd *bitmap;
enum hclge_opcode_type cmd;
int rq_id, pri_id, qset_id;
int port_id, nq_id, pg_id;
struct hclge_desc desc[2];
struct hclge_desc desc;
u16 qset_id, qset_num;
int ret;
int cnt, ret;
ret = hclge_tm_get_qset_num(hdev, &qset_num);
if (ret)
return ret;
cnt = sscanf(cmd_buf, "%i %i %i %i %i %i",
&port_id, &pri_id, &pg_id, &rq_id, &nq_id, &qset_id);
if (cnt != 6) {
dev_err(&hdev->pdev->dev,
"dump dcb: bad command parameter, cnt=%d\n", cnt);
return;
*pos += scnprintf(buf + *pos, len - *pos,
"qset_id roce_qset_mask nic_qset_mask qset_shaping_pass qset_bp_status\n");
for (qset_id = 0; qset_id < qset_num; qset_id++) {
ret = hclge_dbg_cmd_send(hdev, &desc, qset_id, 1,
HCLGE_OPC_QSET_DFX_STS);
if (ret)
return ret;
bitmap = (struct hclge_dbg_bitmap_cmd *)&desc.data[1];
*pos += scnprintf(buf + *pos, len - *pos,
"%04u %#x %#x %#x %#x\n",
qset_id, bitmap->bit0, bitmap->bit1,
bitmap->bit2, bitmap->bit3);
}
cmd = HCLGE_OPC_QSET_DFX_STS;
ret = hclge_dbg_cmd_send(hdev, desc, qset_id, 1, cmd);
return 0;
}
static int hclge_dbg_dump_dcb_pri(struct hclge_dev *hdev, char *buf, int len,
int *pos)
{
struct hclge_dbg_bitmap_cmd *bitmap;
struct hclge_desc desc;
u8 pri_id, pri_num;
int ret;
ret = hclge_tm_get_pri_num(hdev, &pri_num);
if (ret)
return ret;
*pos += scnprintf(buf + *pos, len - *pos,
"pri_id pri_mask pri_cshaping_pass pri_pshaping_pass\n");
for (pri_id = 0; pri_id < pri_num; pri_id++) {
ret = hclge_dbg_cmd_send(hdev, &desc, pri_id, 1,
HCLGE_OPC_PRI_DFX_STS);
if (ret)
goto err_dcb_cmd_send;
return ret;
bitmap = (struct hclge_dbg_bitmap_cmd *)&desc.data[1];
*pos += scnprintf(buf + *pos, len - *pos,
"%03u %#x %#x %#x\n",
pri_id, bitmap->bit0, bitmap->bit1,
bitmap->bit2);
}
bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1];
dev_info(dev, "roce_qset_mask: 0x%x\n", bitmap->bit0);
dev_info(dev, "nic_qs_mask: 0x%x\n", bitmap->bit1);
dev_info(dev, "qs_shaping_pass: 0x%x\n", bitmap->bit2);
dev_info(dev, "qs_bp_sts: 0x%x\n", bitmap->bit3);
return 0;
}
cmd = HCLGE_OPC_PRI_DFX_STS;
ret = hclge_dbg_cmd_send(hdev, desc, pri_id, 1, cmd);
static int hclge_dbg_dump_dcb_pg(struct hclge_dev *hdev, char *buf, int len,
int *pos)
{
struct hclge_dbg_bitmap_cmd *bitmap;
struct hclge_desc desc;
u8 pg_id;
int ret;
*pos += scnprintf(buf + *pos, len - *pos,
"pg_id pg_mask pg_cshaping_pass pg_pshaping_pass\n");
for (pg_id = 0; pg_id < hdev->tm_info.num_pg; pg_id++) {
ret = hclge_dbg_cmd_send(hdev, &desc, pg_id, 1,
HCLGE_OPC_PG_DFX_STS);
if (ret)
goto err_dcb_cmd_send;
return ret;
bitmap = (struct hclge_dbg_bitmap_cmd *)&desc.data[1];
bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1];
dev_info(dev, "pri_mask: 0x%x\n", bitmap->bit0);
dev_info(dev, "pri_cshaping_pass: 0x%x\n", bitmap->bit1);
dev_info(dev, "pri_pshaping_pass: 0x%x\n", bitmap->bit2);
*pos += scnprintf(buf + *pos, len - *pos,
"%03u %#x %#x %#x\n",
pg_id, bitmap->bit0, bitmap->bit1,
bitmap->bit2);
}
cmd = HCLGE_OPC_PG_DFX_STS;
ret = hclge_dbg_cmd_send(hdev, desc, pg_id, 1, cmd);
return 0;
}
static int hclge_dbg_dump_dcb_queue(struct hclge_dev *hdev, char *buf, int len,
int *pos)
{
struct hclge_desc desc;
u16 nq_id;
int ret;
*pos += scnprintf(buf + *pos, len - *pos,
"nq_id sch_nic_queue_cnt sch_roce_queue_cnt\n");
for (nq_id = 0; nq_id < hdev->num_tqps; nq_id++) {
ret = hclge_dbg_cmd_send(hdev, &desc, nq_id, 1,
HCLGE_OPC_SCH_NQ_CNT);
if (ret)
goto err_dcb_cmd_send;
return ret;
bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1];
dev_info(dev, "pg_mask: 0x%x\n", bitmap->bit0);
dev_info(dev, "pg_cshaping_pass: 0x%x\n", bitmap->bit1);
dev_info(dev, "pg_pshaping_pass: 0x%x\n", bitmap->bit2);
*pos += scnprintf(buf + *pos, len - *pos, "%04u %#x",
nq_id, le32_to_cpu(desc.data[1]));
cmd = HCLGE_OPC_PORT_DFX_STS;
ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, cmd);
ret = hclge_dbg_cmd_send(hdev, &desc, nq_id, 1,
HCLGE_OPC_SCH_RQ_CNT);
if (ret)
goto err_dcb_cmd_send;
return ret;
*pos += scnprintf(buf + *pos, len - *pos,
" %#x\n",
le32_to_cpu(desc.data[1]));
}
bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1];
dev_info(dev, "port_mask: 0x%x\n", bitmap->bit0);
dev_info(dev, "port_shaping_pass: 0x%x\n", bitmap->bit1);
return 0;
}
static int hclge_dbg_dump_dcb_port(struct hclge_dev *hdev, char *buf, int len,
int *pos)
{
struct hclge_dbg_bitmap_cmd *bitmap;
struct hclge_desc desc;
u8 port_id = 0;
int ret;
cmd = HCLGE_OPC_SCH_NQ_CNT;
ret = hclge_dbg_cmd_send(hdev, desc, nq_id, 1, cmd);
ret = hclge_dbg_cmd_send(hdev, &desc, port_id, 1,
HCLGE_OPC_PORT_DFX_STS);
if (ret)
goto err_dcb_cmd_send;
return ret;
bitmap = (struct hclge_dbg_bitmap_cmd *)&desc.data[1];
dev_info(dev, "sch_nq_cnt: 0x%x\n", le32_to_cpu(desc[0].data[1]));
*pos += scnprintf(buf + *pos, len - *pos, "port_mask: %#x\n",
bitmap->bit0);
*pos += scnprintf(buf + *pos, len - *pos, "port_shaping_pass: %#x\n",
bitmap->bit1);
return 0;
}
static int hclge_dbg_dump_dcb_tm(struct hclge_dev *hdev, char *buf, int len,
int *pos)
{
struct hclge_desc desc[2];
u8 port_id = 0;
int ret;
cmd = HCLGE_OPC_SCH_RQ_CNT;
ret = hclge_dbg_cmd_send(hdev, desc, nq_id, 1, cmd);
ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1,
HCLGE_OPC_TM_INTERNAL_CNT);
if (ret)
goto err_dcb_cmd_send;
return ret;
dev_info(dev, "sch_rq_cnt: 0x%x\n", le32_to_cpu(desc[0].data[1]));
*pos += scnprintf(buf + *pos, len - *pos, "SCH_NIC_NUM: %#x\n",
le32_to_cpu(desc[0].data[1]));
*pos += scnprintf(buf + *pos, len - *pos, "SCH_ROCE_NUM: %#x\n",
le32_to_cpu(desc[0].data[2]));
cmd = HCLGE_OPC_TM_INTERNAL_STS;
ret = hclge_dbg_cmd_send(hdev, desc, 0, 2, cmd);
ret = hclge_dbg_cmd_send(hdev, desc, port_id, 2,
HCLGE_OPC_TM_INTERNAL_STS);
if (ret)
goto err_dcb_cmd_send;
return ret;
dev_info(dev, "pri_bp: 0x%x\n", le32_to_cpu(desc[0].data[1]));
dev_info(dev, "fifo_dfx_info: 0x%x\n", le32_to_cpu(desc[0].data[2]));
dev_info(dev, "sch_roce_fifo_afull_gap: 0x%x\n",
*pos += scnprintf(buf + *pos, len - *pos, "pri_bp: %#x\n",
le32_to_cpu(desc[0].data[1]));
*pos += scnprintf(buf + *pos, len - *pos, "fifo_dfx_info: %#x\n",
le32_to_cpu(desc[0].data[2]));
*pos += scnprintf(buf + *pos, len - *pos,
"sch_roce_fifo_afull_gap: %#x\n",
le32_to_cpu(desc[0].data[3]));
dev_info(dev, "tx_private_waterline: 0x%x\n",
*pos += scnprintf(buf + *pos, len - *pos,
"tx_private_waterline: %#x\n",
le32_to_cpu(desc[0].data[4]));
dev_info(dev, "tm_bypass_en: 0x%x\n", le32_to_cpu(desc[0].data[5]));
dev_info(dev, "SSU_TM_BYPASS_EN: 0x%x\n", le32_to_cpu(desc[1].data[0]));
dev_info(dev, "SSU_RESERVE_CFG: 0x%x\n", le32_to_cpu(desc[1].data[1]));
cmd = HCLGE_OPC_TM_INTERNAL_CNT;
ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, cmd);
if (ret)
goto err_dcb_cmd_send;
*pos += scnprintf(buf + *pos, len - *pos, "tm_bypass_en: %#x\n",
le32_to_cpu(desc[0].data[5]));
*pos += scnprintf(buf + *pos, len - *pos, "SSU_TM_BYPASS_EN: %#x\n",
le32_to_cpu(desc[1].data[0]));
*pos += scnprintf(buf + *pos, len - *pos, "SSU_RESERVE_CFG: %#x\n",
le32_to_cpu(desc[1].data[1]));
dev_info(dev, "SCH_NIC_NUM: 0x%x\n", le32_to_cpu(desc[0].data[1]));
dev_info(dev, "SCH_ROCE_NUM: 0x%x\n", le32_to_cpu(desc[0].data[2]));
if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER)
return 0;
cmd = HCLGE_OPC_TM_INTERNAL_STS_1;
ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, cmd);
ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1,
HCLGE_OPC_TM_INTERNAL_STS_1);
if (ret)
goto err_dcb_cmd_send;
return ret;
dev_info(dev, "TC_MAP_SEL: 0x%x\n", le32_to_cpu(desc[0].data[1]));
dev_info(dev, "IGU_PFC_PRI_EN: 0x%x\n", le32_to_cpu(desc[0].data[2]));
dev_info(dev, "MAC_PFC_PRI_EN: 0x%x\n", le32_to_cpu(desc[0].data[3]));
dev_info(dev, "IGU_PRI_MAP_TC_CFG: 0x%x\n",
*pos += scnprintf(buf + *pos, len - *pos, "TC_MAP_SEL: %#x\n",
le32_to_cpu(desc[0].data[1]));
*pos += scnprintf(buf + *pos, len - *pos, "IGU_PFC_PRI_EN: %#x\n",
le32_to_cpu(desc[0].data[2]));
*pos += scnprintf(buf + *pos, len - *pos, "MAC_PFC_PRI_EN: %#x\n",
le32_to_cpu(desc[0].data[3]));
*pos += scnprintf(buf + *pos, len - *pos, "IGU_PRI_MAP_TC_CFG: %#x\n",
le32_to_cpu(desc[0].data[4]));
dev_info(dev, "IGU_TX_PRI_MAP_TC_CFG: 0x%x\n",
*pos += scnprintf(buf + *pos, len - *pos,
"IGU_TX_PRI_MAP_TC_CFG: %#x\n",
le32_to_cpu(desc[0].data[5]));
return;
err_dcb_cmd_send:
dev_err(&hdev->pdev->dev,
"failed to dump dcb dfx, cmd = %#x, ret = %d\n",
cmd, ret);
return 0;
}
static void hclge_dbg_dump_reg_cmd(struct hclge_dev *hdev, const char *cmd_buf)
static int hclge_dbg_dump_dcb(struct hclge_dev *hdev, char *buf, int len)
{
int pos = 0;
int ret;
ret = hclge_dbg_dump_dcb_qset(hdev, buf, len, &pos);
if (ret)
return ret;
ret = hclge_dbg_dump_dcb_pri(hdev, buf, len, &pos);
if (ret)
return ret;
ret = hclge_dbg_dump_dcb_pg(hdev, buf, len, &pos);
if (ret)
return ret;
ret = hclge_dbg_dump_dcb_queue(hdev, buf, len, &pos);
if (ret)
return ret;
ret = hclge_dbg_dump_dcb_port(hdev, buf, len, &pos);
if (ret)
return ret;
return hclge_dbg_dump_dcb_tm(hdev, buf, len, &pos);
}
static int hclge_dbg_dump_reg_cmd(struct hclge_dev *hdev,
enum hnae3_dbg_cmd cmd, char *buf, int len)
{
const struct hclge_dbg_reg_type_info *reg_info;
bool has_dump = false;
int pos = 0, ret = 0;
int i;
for (i = 0; i < ARRAY_SIZE(hclge_dbg_reg_info); i++) {
reg_info = &hclge_dbg_reg_info[i];
if (!strncmp(cmd_buf, reg_info->reg_type,
strlen(reg_info->reg_type))) {
hclge_dbg_dump_reg_common(hdev, reg_info, cmd_buf);
has_dump = true;
}
}
if (strncmp(cmd_buf, "mac", strlen("mac")) == 0) {
hclge_dbg_dump_mac(hdev);
has_dump = true;
}
if (cmd == reg_info->cmd) {
if (cmd == HNAE3_DBG_CMD_REG_TQP)
return hclge_dbg_dump_reg_tqp(hdev, reg_info,
buf, len, &pos);
if (strncmp(cmd_buf, "dcb", 3) == 0) {
hclge_dbg_dump_dcb(hdev, &cmd_buf[sizeof("dcb")]);
has_dump = true;
ret = hclge_dbg_dump_reg_common(hdev, reg_info, buf,
len, &pos);
if (ret)
break;
}
if (!has_dump) {
dev_info(&hdev->pdev->dev, "unknown command\n");
return;
}
}
static void hclge_print_tc_info(struct hclge_dev *hdev, bool flag, int index)
{
if (flag)
dev_info(&hdev->pdev->dev, "tc(%d): no sp mode weight: %u\n",
index, hdev->tm_info.pg_info[0].tc_dwrr[index]);
else
dev_info(&hdev->pdev->dev, "tc(%d): sp mode\n", index);
return ret;
}
static void hclge_dbg_dump_tc(struct hclge_dev *hdev)
static int hclge_dbg_dump_tc(struct hclge_dev *hdev, char *buf, int len)
{
struct hclge_ets_tc_weight_cmd *ets_weight;
struct hclge_desc desc;
int i, ret;
char *sch_mode_str;
int pos = 0;
int ret;
u8 i;
if (!hnae3_dev_dcb_supported(hdev)) {
dev_info(&hdev->pdev->dev,
dev_err(&hdev->pdev->dev,
"Only DCB-supported dev supports tc\n");
return;
return -EOPNOTSUPP;
}
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev, "dump tc fail, ret = %d\n", ret);
return;
dev_err(&hdev->pdev->dev, "failed to get tc weight, ret = %d\n",
ret);
return ret;
}
ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "dump tc: %u tc enabled\n",
pos += scnprintf(buf + pos, len - pos, "enabled tc number: %u\n",
hdev->tm_info.num_tc);
dev_info(&hdev->pdev->dev, "weight_offset: %u\n",
pos += scnprintf(buf + pos, len - pos, "weight_offset: %u\n",
ets_weight->weight_offset);
for (i = 0; i < HNAE3_MAX_TC; i++)
hclge_print_tc_info(hdev, ets_weight->tc_weight[i], i);
pos += scnprintf(buf + pos, len - pos, "TC MODE WEIGHT\n");
for (i = 0; i < HNAE3_MAX_TC; i++) {
sch_mode_str = ets_weight->tc_weight[i] ? "dwrr" : "sp";
pos += scnprintf(buf + pos, len - pos, "%u %4s %3u\n",
i, sch_mode_str,
hdev->tm_info.pg_info[0].tc_dwrr[i]);
}
return 0;
}
static void hclge_dbg_dump_tm_pg(struct hclge_dev *hdev)
static const struct hclge_dbg_item tm_pg_items[] = {
{ "ID", 2 },
{ "PRI_MAP", 2 },
{ "MODE", 2 },
{ "DWRR", 2 },
{ "C_IR_B", 2 },
{ "C_IR_U", 2 },
{ "C_IR_S", 2 },
{ "C_BS_B", 2 },
{ "C_BS_S", 2 },
{ "C_FLAG", 2 },
{ "C_RATE(Mbps)", 2 },
{ "P_IR_B", 2 },
{ "P_IR_U", 2 },
{ "P_IR_S", 2 },
{ "P_BS_B", 2 },
{ "P_BS_S", 2 },
{ "P_FLAG", 2 },
{ "P_RATE(Mbps)", 0 }
};
static void hclge_dbg_fill_shaper_content(struct hclge_tm_shaper_para *para,
char **result, u8 *index)
{
struct hclge_port_shapping_cmd *port_shap_cfg_cmd;
struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
struct hclge_pg_shapping_cmd *pg_shap_cfg_cmd;
enum hclge_opcode_type cmd;
struct hclge_desc desc;
sprintf(result[(*index)++], "%3u", para->ir_b);
sprintf(result[(*index)++], "%3u", para->ir_u);
sprintf(result[(*index)++], "%3u", para->ir_s);
sprintf(result[(*index)++], "%3u", para->bs_b);
sprintf(result[(*index)++], "%3u", para->bs_s);
sprintf(result[(*index)++], "%3u", para->flag);
sprintf(result[(*index)++], "%6u", para->rate);
}
static int hclge_dbg_dump_tm_pg(struct hclge_dev *hdev, char *buf, int len)
{
char data_str[ARRAY_SIZE(tm_pg_items)][HCLGE_DBG_DATA_STR_LEN];
struct hclge_tm_shaper_para c_shaper_para, p_shaper_para;
char *result[ARRAY_SIZE(tm_pg_items)], *sch_mode_str;
u8 pg_id, sch_mode, weight, pri_bit_map, i, j;
char content[HCLGE_DBG_TM_INFO_LEN];
int pos = 0;
int ret;
cmd = HCLGE_OPC_TM_PG_C_SHAPPING;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
goto err_tm_pg_cmd_send;
for (i = 0; i < ARRAY_SIZE(tm_pg_items); i++)
result[i] = &data_str[i][0];
pg_shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "PG_C pg_id: %u\n", pg_shap_cfg_cmd->pg_id);
dev_info(&hdev->pdev->dev, "PG_C pg_shapping: 0x%x\n",
le32_to_cpu(pg_shap_cfg_cmd->pg_shapping_para));
hclge_dbg_fill_content(content, sizeof(content), tm_pg_items,
NULL, ARRAY_SIZE(tm_pg_items));
pos += scnprintf(buf + pos, len - pos, "%s", content);
cmd = HCLGE_OPC_TM_PG_P_SHAPPING;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
goto err_tm_pg_cmd_send;
pg_shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "PG_P pg_id: %u\n", pg_shap_cfg_cmd->pg_id);
dev_info(&hdev->pdev->dev, "PG_P pg_shapping: 0x%x\n",
le32_to_cpu(pg_shap_cfg_cmd->pg_shapping_para));
dev_info(&hdev->pdev->dev, "PG_P flag: %#x\n", pg_shap_cfg_cmd->flag);
dev_info(&hdev->pdev->dev, "PG_P pg_rate: %u(Mbps)\n",
le32_to_cpu(pg_shap_cfg_cmd->pg_rate));
cmd = HCLGE_OPC_TM_PORT_SHAPPING;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
for (pg_id = 0; pg_id < hdev->tm_info.num_pg; pg_id++) {
ret = hclge_tm_get_pg_to_pri_map(hdev, pg_id, &pri_bit_map);
if (ret)
goto err_tm_pg_cmd_send;
port_shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "PORT port_shapping: 0x%x\n",
le32_to_cpu(port_shap_cfg_cmd->port_shapping_para));
dev_info(&hdev->pdev->dev, "PORT flag: %#x\n", port_shap_cfg_cmd->flag);
dev_info(&hdev->pdev->dev, "PORT port_rate: %u(Mbps)\n",
le32_to_cpu(port_shap_cfg_cmd->port_rate));
return ret;
cmd = HCLGE_OPC_TM_PG_SCH_MODE_CFG;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
ret = hclge_tm_get_pg_sch_mode(hdev, pg_id, &sch_mode);
if (ret)
goto err_tm_pg_cmd_send;
dev_info(&hdev->pdev->dev, "PG_SCH pg_id: %u\n",
le32_to_cpu(desc.data[0]));
return ret;
cmd = HCLGE_OPC_TM_PRI_SCH_MODE_CFG;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
ret = hclge_tm_get_pg_weight(hdev, pg_id, &weight);
if (ret)
goto err_tm_pg_cmd_send;
return ret;
dev_info(&hdev->pdev->dev, "PRI_SCH pri_id: %u\n",
le32_to_cpu(desc.data[0]));
ret = hclge_tm_get_pg_shaper(hdev, pg_id,
HCLGE_OPC_TM_PG_C_SHAPPING,
&c_shaper_para);
if (ret)
return ret;
cmd = HCLGE_OPC_TM_QS_SCH_MODE_CFG;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
ret = hclge_tm_get_pg_shaper(hdev, pg_id,
HCLGE_OPC_TM_PG_P_SHAPPING,
&p_shaper_para);
if (ret)
goto err_tm_pg_cmd_send;
return ret;
dev_info(&hdev->pdev->dev, "QS_SCH qs_id: %u\n",
le32_to_cpu(desc.data[0]));
sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" :
"sp";
if (!hnae3_dev_dcb_supported(hdev)) {
dev_info(&hdev->pdev->dev,
"Only DCB-supported dev supports tm mapping\n");
return;
j = 0;
sprintf(result[j++], "%02u", pg_id);
sprintf(result[j++], "0x%02x", pri_bit_map);
sprintf(result[j++], "%4s", sch_mode_str);
sprintf(result[j++], "%3u", weight);
hclge_dbg_fill_shaper_content(&c_shaper_para, result, &j);
hclge_dbg_fill_shaper_content(&p_shaper_para, result, &j);
hclge_dbg_fill_content(content, sizeof(content), tm_pg_items,
(const char **)result,
ARRAY_SIZE(tm_pg_items));
pos += scnprintf(buf + pos, len - pos, "%s", content);
}
cmd = HCLGE_OPC_TM_BP_TO_QSET_MAPPING;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
goto err_tm_pg_cmd_send;
bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "BP_TO_QSET tc_id: %u\n",
bp_to_qs_map_cmd->tc_id);
dev_info(&hdev->pdev->dev, "BP_TO_QSET qs_group_id: 0x%x\n",
bp_to_qs_map_cmd->qs_group_id);
dev_info(&hdev->pdev->dev, "BP_TO_QSET qs_bit_map: 0x%x\n",
le32_to_cpu(bp_to_qs_map_cmd->qs_bit_map));
return;
err_tm_pg_cmd_send:
dev_err(&hdev->pdev->dev, "dump tm_pg fail(0x%x), ret = %d\n",
cmd, ret);
return 0;
}
static void hclge_dbg_dump_tm(struct hclge_dev *hdev)
static int hclge_dbg_dump_tm_port(struct hclge_dev *hdev, char *buf, int len)
{
struct hclge_priority_weight_cmd *priority_weight;
struct hclge_pg_to_pri_link_cmd *pg_to_pri_map;
struct hclge_qs_to_pri_link_cmd *qs_to_pri_map;
struct hclge_nq_to_qs_link_cmd *nq_to_qs_map;
struct hclge_pri_shapping_cmd *shap_cfg_cmd;
struct hclge_pg_weight_cmd *pg_weight;
struct hclge_qs_weight_cmd *qs_weight;
enum hclge_opcode_type cmd;
struct hclge_desc desc;
struct hclge_tm_shaper_para shaper_para;
int pos = 0;
int ret;
cmd = HCLGE_OPC_TM_PG_TO_PRI_LINK;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
goto err_tm_cmd_send;
pg_to_pri_map = (struct hclge_pg_to_pri_link_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "dump tm\n");
dev_info(&hdev->pdev->dev, "PG_TO_PRI gp_id: %u\n",
pg_to_pri_map->pg_id);
dev_info(&hdev->pdev->dev, "PG_TO_PRI map: 0x%x\n",
pg_to_pri_map->pri_bit_map);
cmd = HCLGE_OPC_TM_QS_TO_PRI_LINK;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
goto err_tm_cmd_send;
qs_to_pri_map = (struct hclge_qs_to_pri_link_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "QS_TO_PRI qs_id: %u\n",
le16_to_cpu(qs_to_pri_map->qs_id));
dev_info(&hdev->pdev->dev, "QS_TO_PRI priority: %u\n",
qs_to_pri_map->priority);
dev_info(&hdev->pdev->dev, "QS_TO_PRI link_vld: %u\n",
qs_to_pri_map->link_vld);
cmd = HCLGE_OPC_TM_NQ_TO_QS_LINK;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
goto err_tm_cmd_send;
nq_to_qs_map = (struct hclge_nq_to_qs_link_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "NQ_TO_QS nq_id: %u\n",
le16_to_cpu(nq_to_qs_map->nq_id));
dev_info(&hdev->pdev->dev, "NQ_TO_QS qset_id: 0x%x\n",
le16_to_cpu(nq_to_qs_map->qset_id));
cmd = HCLGE_OPC_TM_PG_WEIGHT;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
goto err_tm_cmd_send;
pg_weight = (struct hclge_pg_weight_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "PG pg_id: %u\n", pg_weight->pg_id);
dev_info(&hdev->pdev->dev, "PG dwrr: %u\n", pg_weight->dwrr);
cmd = HCLGE_OPC_TM_QS_WEIGHT;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
ret = hclge_tm_get_port_shaper(hdev, &shaper_para);
if (ret)
goto err_tm_cmd_send;
return ret;
qs_weight = (struct hclge_qs_weight_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "QS qs_id: %u\n",
le16_to_cpu(qs_weight->qs_id));
dev_info(&hdev->pdev->dev, "QS dwrr: %u\n", qs_weight->dwrr);
pos += scnprintf(buf + pos, len - pos,
"IR_B IR_U IR_S BS_B BS_S FLAG RATE(Mbps)\n");
pos += scnprintf(buf + pos, len - pos,
"%3u %3u %3u %3u %3u %1u %6u\n",
shaper_para.ir_b, shaper_para.ir_u, shaper_para.ir_s,
shaper_para.bs_b, shaper_para.bs_s, shaper_para.flag,
shaper_para.rate);
cmd = HCLGE_OPC_TM_PRI_WEIGHT;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
goto err_tm_cmd_send;
return 0;
}
priority_weight = (struct hclge_priority_weight_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "PRI pri_id: %u\n", priority_weight->pri_id);
dev_info(&hdev->pdev->dev, "PRI dwrr: %u\n", priority_weight->dwrr);
static int hclge_dbg_dump_tm_bp_qset_map(struct hclge_dev *hdev, u8 tc_id,
char *buf, int len)
{
u32 qset_mapping[HCLGE_BP_EXT_GRP_NUM];
struct hclge_bp_to_qs_map_cmd *map;
struct hclge_desc desc;
int pos = 0;
u8 group_id;
u8 grp_num;
u16 i = 0;
int ret;
cmd = HCLGE_OPC_TM_PRI_C_SHAPPING;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
goto err_tm_cmd_send;
shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "PRI_C pri_id: %u\n", shap_cfg_cmd->pri_id);
dev_info(&hdev->pdev->dev, "PRI_C pri_shapping: 0x%x\n",
le32_to_cpu(shap_cfg_cmd->pri_shapping_para));
dev_info(&hdev->pdev->dev, "PRI_C flag: %#x\n", shap_cfg_cmd->flag);
dev_info(&hdev->pdev->dev, "PRI_C pri_rate: %u(Mbps)\n",
le32_to_cpu(shap_cfg_cmd->pri_rate));
cmd = HCLGE_OPC_TM_PRI_P_SHAPPING;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
grp_num = hdev->num_tqps <= HCLGE_TQP_MAX_SIZE_DEV_V2 ?
HCLGE_BP_GRP_NUM : HCLGE_BP_EXT_GRP_NUM;
map = (struct hclge_bp_to_qs_map_cmd *)desc.data;
for (group_id = 0; group_id < grp_num; group_id++) {
hclge_cmd_setup_basic_desc(&desc,
HCLGE_OPC_TM_BP_TO_QSET_MAPPING,
true);
map->tc_id = tc_id;
map->qs_group_id = group_id;
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
goto err_tm_cmd_send;
shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "PRI_P pri_id: %u\n", shap_cfg_cmd->pri_id);
dev_info(&hdev->pdev->dev, "PRI_P pri_shapping: 0x%x\n",
le32_to_cpu(shap_cfg_cmd->pri_shapping_para));
dev_info(&hdev->pdev->dev, "PRI_P flag: %#x\n", shap_cfg_cmd->flag);
dev_info(&hdev->pdev->dev, "PRI_P pri_rate: %u(Mbps)\n",
le32_to_cpu(shap_cfg_cmd->pri_rate));
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to get bp to qset map, ret = %d\n",
ret);
return ret;
}
hclge_dbg_dump_tm_pg(hdev);
qset_mapping[group_id] = le32_to_cpu(map->qs_bit_map);
}
return;
pos += scnprintf(buf + pos, len - pos, "INDEX | TM BP QSET MAPPING:\n");
for (group_id = 0; group_id < grp_num / 8; group_id++) {
pos += scnprintf(buf + pos, len - pos,
"%04d | %08x:%08x:%08x:%08x:%08x:%08x:%08x:%08x\n",
group_id * 256, qset_mapping[i + 7],
qset_mapping[i + 6], qset_mapping[i + 5],
qset_mapping[i + 4], qset_mapping[i + 3],
qset_mapping[i + 2], qset_mapping[i + 1],
qset_mapping[i]);
i += 8;
}
err_tm_cmd_send:
dev_err(&hdev->pdev->dev, "dump tm fail(0x%x), ret = %d\n",
cmd, ret);
return pos;
}
static void hclge_dbg_dump_tm_map(struct hclge_dev *hdev,
const char *cmd_buf)
static int hclge_dbg_dump_tm_map(struct hclge_dev *hdev, char *buf, int len)
{
struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
struct hclge_nq_to_qs_link_cmd *nq_to_qs_map;
u32 qset_mapping[HCLGE_BP_EXT_GRP_NUM];
struct hclge_qs_to_pri_link_cmd *map;
struct hclge_tqp_tx_queue_tc_cmd *tc;
u16 group_id, queue_id, qset_id;
enum hclge_opcode_type cmd;
u8 grp_num, pri_id, tc_id;
struct hclge_desc desc;
u16 qs_id_l;
u16 qs_id_h;
int ret;
u32 i;
ret = kstrtou16(cmd_buf, 0, &queue_id);
queue_id = (ret != 0) ? 0 : queue_id;
u16 queue_id;
u16 qset_id;
u8 link_vld;
int pos = 0;
u8 pri_id;
u8 tc_id;
int ret;
cmd = HCLGE_OPC_TM_NQ_TO_QS_LINK;
nq_to_qs_map = (struct hclge_nq_to_qs_link_cmd *)desc.data;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
nq_to_qs_map->nq_id = cpu_to_le16(queue_id);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
for (queue_id = 0; queue_id < hdev->num_tqps; queue_id++) {
ret = hclge_tm_get_q_to_qs_map(hdev, queue_id, &qset_id);
if (ret)
goto err_tm_map_cmd_send;
qset_id = le16_to_cpu(nq_to_qs_map->qset_id);
/* convert qset_id to the following format, drop the vld bit
* | qs_id_h | vld | qs_id_l |
* qset_id: | 15 ~ 11 | 10 | 9 ~ 0 |
* \ \ / /
* \ \ / /
* qset_id: | 15 | 14 ~ 10 | 9 ~ 0 |
*/
qs_id_l = hnae3_get_field(qset_id, HCLGE_TM_QS_ID_L_MSK,
HCLGE_TM_QS_ID_L_S);
qs_id_h = hnae3_get_field(qset_id, HCLGE_TM_QS_ID_H_EXT_MSK,
HCLGE_TM_QS_ID_H_EXT_S);
qset_id = 0;
hnae3_set_field(qset_id, HCLGE_TM_QS_ID_L_MSK, HCLGE_TM_QS_ID_L_S,
qs_id_l);
hnae3_set_field(qset_id, HCLGE_TM_QS_ID_H_MSK, HCLGE_TM_QS_ID_H_S,
qs_id_h);
cmd = HCLGE_OPC_TM_QS_TO_PRI_LINK;
map = (struct hclge_qs_to_pri_link_cmd *)desc.data;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
map->qs_id = cpu_to_le16(qset_id);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
return ret;
ret = hclge_tm_get_qset_map_pri(hdev, qset_id, &pri_id,
&link_vld);
if (ret)
goto err_tm_map_cmd_send;
pri_id = map->priority;
return ret;
cmd = HCLGE_OPC_TQP_TX_QUEUE_TC;
tc = (struct hclge_tqp_tx_queue_tc_cmd *)desc.data;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
tc->queue_id = cpu_to_le16(queue_id);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
ret = hclge_tm_get_q_to_tc(hdev, queue_id, &tc_id);
if (ret)
goto err_tm_map_cmd_send;
tc_id = tc->tc_id & 0x7;
return ret;
dev_info(&hdev->pdev->dev, "queue_id | qset_id | pri_id | tc_id\n");
dev_info(&hdev->pdev->dev, "%04u | %04u | %02u | %02u\n",
pos += scnprintf(buf + pos, len - pos,
"QUEUE_ID QSET_ID PRI_ID TC_ID\n");
pos += scnprintf(buf + pos, len - pos,
"%04u %4u %3u %2u\n",
queue_id, qset_id, pri_id, tc_id);
if (!hnae3_dev_dcb_supported(hdev)) {
dev_info(&hdev->pdev->dev,
"Only DCB-supported dev supports tm mapping\n");
return;
}
grp_num = hdev->num_tqps <= HCLGE_TQP_MAX_SIZE_DEV_V2 ?
HCLGE_BP_GRP_NUM : HCLGE_BP_EXT_GRP_NUM;
cmd = HCLGE_OPC_TM_BP_TO_QSET_MAPPING;
bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data;
for (group_id = 0; group_id < grp_num; group_id++) {
hclge_cmd_setup_basic_desc(&desc, cmd, true);
bp_to_qs_map_cmd->tc_id = tc_id;
bp_to_qs_map_cmd->qs_group_id = group_id;
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
goto err_tm_map_cmd_send;
qset_mapping[group_id] =
le32_to_cpu(bp_to_qs_map_cmd->qs_bit_map);
}
if (!hnae3_dev_dcb_supported(hdev))
continue;
dev_info(&hdev->pdev->dev, "index | tm bp qset maping:\n");
ret = hclge_dbg_dump_tm_bp_qset_map(hdev, tc_id, buf + pos,
len - pos);
if (ret < 0)
return ret;
pos += ret;
i = 0;
for (group_id = 0; group_id < grp_num / 8; group_id++) {
dev_info(&hdev->pdev->dev,
"%04d | %08x:%08x:%08x:%08x:%08x:%08x:%08x:%08x\n",
group_id * 256, qset_mapping[(u32)(i + 7)],
qset_mapping[(u32)(i + 6)], qset_mapping[(u32)(i + 5)],
qset_mapping[(u32)(i + 4)], qset_mapping[(u32)(i + 3)],
qset_mapping[(u32)(i + 2)], qset_mapping[(u32)(i + 1)],
qset_mapping[i]);
i += 8;
pos += scnprintf(buf + pos, len - pos, "\n");
}
return;
err_tm_map_cmd_send:
dev_err(&hdev->pdev->dev, "dump tqp map fail(0x%x), ret = %d\n",
cmd, ret);
return 0;
}
static int hclge_dbg_dump_tm_nodes(struct hclge_dev *hdev, char *buf, int len)
......@@ -868,8 +928,8 @@ static int hclge_dbg_dump_tm_nodes(struct hclge_dev *hdev, char *buf, int len)
static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len)
{
struct hclge_pri_shaper_para c_shaper_para;
struct hclge_pri_shaper_para p_shaper_para;
struct hclge_tm_shaper_para c_shaper_para;
struct hclge_tm_shaper_para p_shaper_para;
u8 pri_num, sch_mode, weight;
char *sch_mode_str;
int pos = 0;
......@@ -931,19 +991,42 @@ static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len)
return 0;
}
static const struct hclge_dbg_item tm_qset_items[] = {
{ "ID", 4 },
{ "MAP_PRI", 2 },
{ "LINK_VLD", 2 },
{ "MODE", 2 },
{ "DWRR", 2 },
{ "IR_B", 2 },
{ "IR_U", 2 },
{ "IR_S", 2 },
{ "BS_B", 2 },
{ "BS_S", 2 },
{ "FLAG", 2 },
{ "RATE(Mbps)", 0 }
};
static int hclge_dbg_dump_tm_qset(struct hclge_dev *hdev, char *buf, int len)
{
char data_str[ARRAY_SIZE(tm_qset_items)][HCLGE_DBG_DATA_STR_LEN];
char *result[ARRAY_SIZE(tm_qset_items)], *sch_mode_str;
u8 priority, link_vld, sch_mode, weight;
char *sch_mode_str;
struct hclge_tm_shaper_para shaper_para;
char content[HCLGE_DBG_TM_INFO_LEN];
u16 qset_num, i;
int ret, pos;
u16 qset_num;
u16 i;
u8 j;
ret = hclge_tm_get_qset_num(hdev, &qset_num);
if (ret)
return ret;
pos = scnprintf(buf, len, "ID MAP_PRI LINK_VLD MODE DWRR\n");
for (i = 0; i < ARRAY_SIZE(tm_qset_items); i++)
result[i] = &data_str[i][0];
hclge_dbg_fill_content(content, sizeof(content), tm_qset_items,
NULL, ARRAY_SIZE(tm_qset_items));
pos = scnprintf(buf, len, "%s", content);
for (i = 0; i < qset_num; i++) {
ret = hclge_tm_get_qset_map_pri(hdev, i, &priority, &link_vld);
......@@ -958,260 +1041,311 @@ static int hclge_dbg_dump_tm_qset(struct hclge_dev *hdev, char *buf, int len)
if (ret)
return ret;
ret = hclge_tm_get_qset_shaper(hdev, i, &shaper_para);
if (ret)
return ret;
sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" :
"sp";
pos += scnprintf(buf + pos, len - pos,
"%04u %4u %1u %4s %3u\n",
i, priority, link_vld, sch_mode_str, weight);
j = 0;
sprintf(result[j++], "%04u", i);
sprintf(result[j++], "%4u", priority);
sprintf(result[j++], "%4u", link_vld);
sprintf(result[j++], "%4s", sch_mode_str);
sprintf(result[j++], "%3u", weight);
hclge_dbg_fill_shaper_content(&shaper_para, result, &j);
hclge_dbg_fill_content(content, sizeof(content), tm_qset_items,
(const char **)result,
ARRAY_SIZE(tm_qset_items));
pos += scnprintf(buf + pos, len - pos, "%s", content);
}
return 0;
}
static void hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev)
static int hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev, char *buf,
int len)
{
struct hclge_cfg_pause_param_cmd *pause_param;
struct hclge_desc desc;
int pos = 0;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev, "dump checksum fail, ret = %d\n",
ret);
return;
dev_err(&hdev->pdev->dev,
"failed to dump qos pause, ret = %d\n", ret);
return ret;
}
pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "dump qos pause cfg\n");
dev_info(&hdev->pdev->dev, "pause_trans_gap: 0x%x\n",
pos += scnprintf(buf + pos, len - pos, "pause_trans_gap: 0x%x\n",
pause_param->pause_trans_gap);
dev_info(&hdev->pdev->dev, "pause_trans_time: 0x%x\n",
pos += scnprintf(buf + pos, len - pos, "pause_trans_time: 0x%x\n",
le16_to_cpu(pause_param->pause_trans_time));
return 0;
}
static void hclge_dbg_dump_qos_pri_map(struct hclge_dev *hdev)
static int hclge_dbg_dump_qos_pri_map(struct hclge_dev *hdev, char *buf,
int len)
{
#define HCLGE_DBG_TC_MASK 0x0F
#define HCLGE_DBG_TC_BIT_WIDTH 4
struct hclge_qos_pri_map_cmd *pri_map;
struct hclge_desc desc;
int pos = 0;
u8 *pri_tc;
u8 tc, i;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"dump qos pri map fail, ret = %d\n", ret);
return;
"failed to dump qos pri map, ret = %d\n", ret);
return ret;
}
pri_map = (struct hclge_qos_pri_map_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "dump qos pri map\n");
dev_info(&hdev->pdev->dev, "vlan_to_pri: 0x%x\n", pri_map->vlan_pri);
dev_info(&hdev->pdev->dev, "pri_0_to_tc: 0x%x\n", pri_map->pri0_tc);
dev_info(&hdev->pdev->dev, "pri_1_to_tc: 0x%x\n", pri_map->pri1_tc);
dev_info(&hdev->pdev->dev, "pri_2_to_tc: 0x%x\n", pri_map->pri2_tc);
dev_info(&hdev->pdev->dev, "pri_3_to_tc: 0x%x\n", pri_map->pri3_tc);
dev_info(&hdev->pdev->dev, "pri_4_to_tc: 0x%x\n", pri_map->pri4_tc);
dev_info(&hdev->pdev->dev, "pri_5_to_tc: 0x%x\n", pri_map->pri5_tc);
dev_info(&hdev->pdev->dev, "pri_6_to_tc: 0x%x\n", pri_map->pri6_tc);
dev_info(&hdev->pdev->dev, "pri_7_to_tc: 0x%x\n", pri_map->pri7_tc);
pos += scnprintf(buf + pos, len - pos, "vlan_to_pri: 0x%x\n",
pri_map->vlan_pri);
pos += scnprintf(buf + pos, len - pos, "PRI TC\n");
pri_tc = (u8 *)pri_map;
for (i = 0; i < HNAE3_MAX_TC; i++) {
tc = pri_tc[i >> 1] >> ((i & 1) * HCLGE_DBG_TC_BIT_WIDTH);
tc &= HCLGE_DBG_TC_MASK;
pos += scnprintf(buf + pos, len - pos, "%u %u\n", i, tc);
}
return 0;
}
static int hclge_dbg_dump_tx_buf_cfg(struct hclge_dev *hdev)
static int hclge_dbg_dump_tx_buf_cfg(struct hclge_dev *hdev, char *buf, int len)
{
struct hclge_tx_buff_alloc_cmd *tx_buf_cmd;
struct hclge_desc desc;
int pos = 0;
int i, ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to dump tx buf, ret = %d\n", ret);
return ret;
}
dev_info(&hdev->pdev->dev, "dump qos buf cfg\n");
tx_buf_cmd = (struct hclge_tx_buff_alloc_cmd *)desc.data;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
dev_info(&hdev->pdev->dev, "tx_packet_buf_tc_%d: 0x%x\n", i,
pos += scnprintf(buf + pos, len - pos,
"tx_packet_buf_tc_%d: 0x%x\n", i,
le16_to_cpu(tx_buf_cmd->tx_pkt_buff[i]));
return 0;
return pos;
}
static int hclge_dbg_dump_rx_priv_buf_cfg(struct hclge_dev *hdev)
static int hclge_dbg_dump_rx_priv_buf_cfg(struct hclge_dev *hdev, char *buf,
int len)
{
struct hclge_rx_priv_buff_cmd *rx_buf_cmd;
struct hclge_desc desc;
int pos = 0;
int i, ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to dump rx priv buf, ret = %d\n", ret);
return ret;
}
pos += scnprintf(buf + pos, len - pos, "\n");
dev_info(&hdev->pdev->dev, "\n");
rx_buf_cmd = (struct hclge_rx_priv_buff_cmd *)desc.data;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
dev_info(&hdev->pdev->dev, "rx_packet_buf_tc_%d: 0x%x\n", i,
pos += scnprintf(buf + pos, len - pos,
"rx_packet_buf_tc_%d: 0x%x\n", i,
le16_to_cpu(rx_buf_cmd->buf_num[i]));
dev_info(&hdev->pdev->dev, "rx_share_buf: 0x%x\n",
pos += scnprintf(buf + pos, len - pos, "rx_share_buf: 0x%x\n",
le16_to_cpu(rx_buf_cmd->shared_buf));
return 0;
return pos;
}
static int hclge_dbg_dump_rx_common_wl_cfg(struct hclge_dev *hdev)
static int hclge_dbg_dump_rx_common_wl_cfg(struct hclge_dev *hdev, char *buf,
int len)
{
struct hclge_rx_com_wl *rx_com_wl;
struct hclge_desc desc;
int pos = 0;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to dump rx common wl, ret = %d\n", ret);
return ret;
}
rx_com_wl = (struct hclge_rx_com_wl *)desc.data;
dev_info(&hdev->pdev->dev, "\n");
dev_info(&hdev->pdev->dev, "rx_com_wl: high: 0x%x, low: 0x%x\n",
pos += scnprintf(buf + pos, len - pos, "\n");
pos += scnprintf(buf + pos, len - pos,
"rx_com_wl: high: 0x%x, low: 0x%x\n",
le16_to_cpu(rx_com_wl->com_wl.high),
le16_to_cpu(rx_com_wl->com_wl.low));
return 0;
return pos;
}
static int hclge_dbg_dump_rx_global_pkt_cnt(struct hclge_dev *hdev)
static int hclge_dbg_dump_rx_global_pkt_cnt(struct hclge_dev *hdev, char *buf,
int len)
{
struct hclge_rx_com_wl *rx_packet_cnt;
struct hclge_desc desc;
int pos = 0;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_GBL_PKT_CNT, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to dump rx global pkt cnt, ret = %d\n", ret);
return ret;
}
rx_packet_cnt = (struct hclge_rx_com_wl *)desc.data;
dev_info(&hdev->pdev->dev,
pos += scnprintf(buf + pos, len - pos,
"rx_global_packet_cnt: high: 0x%x, low: 0x%x\n",
le16_to_cpu(rx_packet_cnt->com_wl.high),
le16_to_cpu(rx_packet_cnt->com_wl.low));
return 0;
return pos;
}
static int hclge_dbg_dump_rx_priv_wl_buf_cfg(struct hclge_dev *hdev)
static int hclge_dbg_dump_rx_priv_wl_buf_cfg(struct hclge_dev *hdev, char *buf,
int len)
{
struct hclge_rx_priv_wl_buf *rx_priv_wl;
struct hclge_desc desc[2];
int pos = 0;
int i, ret;
hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_RX_PRIV_WL_ALLOC, true);
desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_RX_PRIV_WL_ALLOC, true);
ret = hclge_cmd_send(&hdev->hw, desc, 2);
if (ret)
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to dump rx priv wl buf, ret = %d\n", ret);
return ret;
}
rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[0].data;
for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
dev_info(&hdev->pdev->dev,
pos += scnprintf(buf + pos, len - pos,
"rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i,
le16_to_cpu(rx_priv_wl->tc_wl[i].high),
le16_to_cpu(rx_priv_wl->tc_wl[i].low));
rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[1].data;
for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
dev_info(&hdev->pdev->dev,
pos += scnprintf(buf + pos, len - pos,
"rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n",
i + HCLGE_TC_NUM_ONE_DESC,
le16_to_cpu(rx_priv_wl->tc_wl[i].high),
le16_to_cpu(rx_priv_wl->tc_wl[i].low));
return 0;
return pos;
}
static int hclge_dbg_dump_rx_common_threshold_cfg(struct hclge_dev *hdev)
static int hclge_dbg_dump_rx_common_threshold_cfg(struct hclge_dev *hdev,
char *buf, int len)
{
struct hclge_rx_com_thrd *rx_com_thrd;
struct hclge_desc desc[2];
int pos = 0;
int i, ret;
hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_RX_COM_THRD_ALLOC, true);
desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_RX_COM_THRD_ALLOC, true);
ret = hclge_cmd_send(&hdev->hw, desc, 2);
if (ret)
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to dump rx common threshold, ret = %d\n", ret);
return ret;
}
dev_info(&hdev->pdev->dev, "\n");
pos += scnprintf(buf + pos, len - pos, "\n");
rx_com_thrd = (struct hclge_rx_com_thrd *)desc[0].data;
for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
dev_info(&hdev->pdev->dev,
pos += scnprintf(buf + pos, len - pos,
"rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i,
le16_to_cpu(rx_com_thrd->com_thrd[i].high),
le16_to_cpu(rx_com_thrd->com_thrd[i].low));
rx_com_thrd = (struct hclge_rx_com_thrd *)desc[1].data;
for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
dev_info(&hdev->pdev->dev,
pos += scnprintf(buf + pos, len - pos,
"rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n",
i + HCLGE_TC_NUM_ONE_DESC,
le16_to_cpu(rx_com_thrd->com_thrd[i].high),
le16_to_cpu(rx_com_thrd->com_thrd[i].low));
return 0;
return pos;
}
static void hclge_dbg_dump_qos_buf_cfg(struct hclge_dev *hdev)
static int hclge_dbg_dump_qos_buf_cfg(struct hclge_dev *hdev, char *buf,
int len)
{
enum hclge_opcode_type cmd;
int pos = 0;
int ret;
cmd = HCLGE_OPC_TX_BUFF_ALLOC;
ret = hclge_dbg_dump_tx_buf_cfg(hdev);
if (ret)
goto err_qos_cmd_send;
cmd = HCLGE_OPC_RX_PRIV_BUFF_ALLOC;
ret = hclge_dbg_dump_rx_priv_buf_cfg(hdev);
if (ret)
goto err_qos_cmd_send;
ret = hclge_dbg_dump_tx_buf_cfg(hdev, buf + pos, len - pos);
if (ret < 0)
return ret;
pos += ret;
cmd = HCLGE_OPC_RX_COM_WL_ALLOC;
ret = hclge_dbg_dump_rx_common_wl_cfg(hdev);
if (ret)
goto err_qos_cmd_send;
ret = hclge_dbg_dump_rx_priv_buf_cfg(hdev, buf + pos, len - pos);
if (ret < 0)
return ret;
pos += ret;
cmd = HCLGE_OPC_RX_GBL_PKT_CNT;
ret = hclge_dbg_dump_rx_global_pkt_cnt(hdev);
if (ret)
goto err_qos_cmd_send;
ret = hclge_dbg_dump_rx_common_wl_cfg(hdev, buf + pos, len - pos);
if (ret < 0)
return ret;
pos += ret;
dev_info(&hdev->pdev->dev, "\n");
if (!hnae3_dev_dcb_supported(hdev)) {
dev_info(&hdev->pdev->dev,
"Only DCB-supported dev supports rx priv wl\n");
return;
}
ret = hclge_dbg_dump_rx_global_pkt_cnt(hdev, buf + pos, len - pos);
if (ret < 0)
return ret;
pos += ret;
cmd = HCLGE_OPC_RX_PRIV_WL_ALLOC;
ret = hclge_dbg_dump_rx_priv_wl_buf_cfg(hdev);
if (ret)
goto err_qos_cmd_send;
pos += scnprintf(buf + pos, len - pos, "\n");
if (!hnae3_dev_dcb_supported(hdev))
return 0;
cmd = HCLGE_OPC_RX_COM_THRD_ALLOC;
ret = hclge_dbg_dump_rx_common_threshold_cfg(hdev);
if (ret)
goto err_qos_cmd_send;
ret = hclge_dbg_dump_rx_priv_wl_buf_cfg(hdev, buf + pos, len - pos);
if (ret < 0)
return ret;
pos += ret;
return;
ret = hclge_dbg_dump_rx_common_threshold_cfg(hdev, buf + pos,
len - pos);
if (ret < 0)
return ret;
err_qos_cmd_send:
dev_err(&hdev->pdev->dev,
"dump qos buf cfg fail(0x%x), ret = %d\n", cmd, ret);
return 0;
}
static int hclge_dbg_dump_mng_table(struct hclge_dev *hdev, char *buf, int len)
......@@ -1273,13 +1407,17 @@ static int hclge_dbg_dump_mng_table(struct hclge_dev *hdev, char *buf, int len)
return 0;
}
static int hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, u8 stage,
bool sel_x, u32 loc)
#define HCLGE_DBG_TCAM_BUF_SIZE 256
static int hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, bool sel_x,
char *tcam_buf,
struct hclge_dbg_tcam_msg tcam_msg)
{
struct hclge_fd_tcam_config_1_cmd *req1;
struct hclge_fd_tcam_config_2_cmd *req2;
struct hclge_fd_tcam_config_3_cmd *req3;
struct hclge_desc desc[3];
int pos = 0;
int ret, i;
u32 *req;
......@@ -1293,31 +1431,35 @@ static int hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, u8 stage,
req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
req1->stage = stage;
req1->stage = tcam_msg.stage;
req1->xy_sel = sel_x ? 1 : 0;
req1->index = cpu_to_le32(loc);
req1->index = cpu_to_le32(tcam_msg.loc);
ret = hclge_cmd_send(&hdev->hw, desc, 3);
if (ret)
return ret;
dev_info(&hdev->pdev->dev, " read result tcam key %s(%u):\n",
sel_x ? "x" : "y", loc);
pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos,
"read result tcam key %s(%u):\n", sel_x ? "x" : "y",
tcam_msg.loc);
/* tcam_data0 ~ tcam_data1 */
req = (u32 *)req1->tcam_data;
for (i = 0; i < 2; i++)
dev_info(&hdev->pdev->dev, "%08x\n", *req++);
pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos,
"%08x\n", *req++);
/* tcam_data2 ~ tcam_data7 */
req = (u32 *)req2->tcam_data;
for (i = 0; i < 6; i++)
dev_info(&hdev->pdev->dev, "%08x\n", *req++);
pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos,
"%08x\n", *req++);
/* tcam_data8 ~ tcam_data12 */
req = (u32 *)req3->tcam_data;
for (i = 0; i < 5; i++)
dev_info(&hdev->pdev->dev, "%08x\n", *req++);
pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos,
"%08x\n", *req++);
return ret;
}
......@@ -1335,59 +1477,75 @@ static int hclge_dbg_get_rules_location(struct hclge_dev *hdev, u16 *rule_locs)
}
spin_unlock_bh(&hdev->fd_rule_lock);
if (cnt != hdev->hclge_fd_rule_num)
if (cnt != hdev->hclge_fd_rule_num || cnt == 0)
return -EINVAL;
return cnt;
}
static void hclge_dbg_fd_tcam(struct hclge_dev *hdev)
static int hclge_dbg_dump_fd_tcam(struct hclge_dev *hdev, char *buf, int len)
{
u32 rule_num = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
struct hclge_dbg_tcam_msg tcam_msg;
int i, ret, rule_cnt;
u16 *rule_locs;
char *tcam_buf;
int pos = 0;
if (!hnae3_dev_fd_supported(hdev)) {
dev_err(&hdev->pdev->dev,
"Only FD-supported dev supports dump fd tcam\n");
return;
return -EOPNOTSUPP;
}
if (!hdev->hclge_fd_rule_num ||
!hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
return;
if (!hdev->hclge_fd_rule_num || !rule_num)
return 0;
rule_locs = kcalloc(hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
sizeof(u16), GFP_KERNEL);
rule_locs = kcalloc(rule_num, sizeof(u16), GFP_KERNEL);
if (!rule_locs)
return;
return -ENOMEM;
tcam_buf = kzalloc(HCLGE_DBG_TCAM_BUF_SIZE, GFP_KERNEL);
if (!tcam_buf) {
kfree(rule_locs);
return -ENOMEM;
}
rule_cnt = hclge_dbg_get_rules_location(hdev, rule_locs);
if (rule_cnt <= 0) {
if (rule_cnt < 0) {
ret = rule_cnt;
dev_err(&hdev->pdev->dev,
"failed to get rule number, ret = %d\n", rule_cnt);
kfree(rule_locs);
return;
"failed to get rule number, ret = %d\n", ret);
goto out;
}
for (i = 0; i < rule_cnt; i++) {
ret = hclge_dbg_fd_tcam_read(hdev, 0, true, rule_locs[i]);
tcam_msg.stage = HCLGE_FD_STAGE_1;
tcam_msg.loc = rule_locs[i];
ret = hclge_dbg_fd_tcam_read(hdev, true, tcam_buf, tcam_msg);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to get fd tcam key x, ret = %d\n", ret);
kfree(rule_locs);
return;
goto out;
}
ret = hclge_dbg_fd_tcam_read(hdev, 0, false, rule_locs[i]);
pos += scnprintf(buf + pos, len - pos, "%s", tcam_buf);
ret = hclge_dbg_fd_tcam_read(hdev, false, tcam_buf, tcam_msg);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to get fd tcam key y, ret = %d\n", ret);
kfree(rule_locs);
return;
goto out;
}
pos += scnprintf(buf + pos, len - pos, "%s", tcam_buf);
}
out:
kfree(tcam_buf);
kfree(rule_locs);
return ret;
}
int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len)
......@@ -1432,12 +1590,26 @@ int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len)
return 0;
}
static void hclge_dbg_dump_serv_info(struct hclge_dev *hdev)
static int hclge_dbg_dump_serv_info(struct hclge_dev *hdev, char *buf, int len)
{
dev_info(&hdev->pdev->dev, "last_serv_processed: %lu\n",
unsigned long rem_nsec;
int pos = 0;
u64 lc;
lc = local_clock();
rem_nsec = do_div(lc, HCLGE_BILLION_NANO_SECONDS);
pos += scnprintf(buf + pos, len - pos, "local_clock: [%5lu.%06lu]\n",
(unsigned long)lc, rem_nsec / 1000);
pos += scnprintf(buf + pos, len - pos, "delta: %u(ms)\n",
jiffies_to_msecs(jiffies - hdev->last_serv_processed));
pos += scnprintf(buf + pos, len - pos,
"last_service_task_processed: %lu(jiffies)\n",
hdev->last_serv_processed);
dev_info(&hdev->pdev->dev, "last_serv_cnt: %lu\n",
pos += scnprintf(buf + pos, len - pos, "last_service_task_cnt: %lu\n",
hdev->serv_processed_cnt);
return 0;
}
static int hclge_dbg_dump_interrupt(struct hclge_dev *hdev, char *buf, int len)
......@@ -1649,98 +1821,28 @@ static int hclge_dbg_dump_loopback(struct hclge_dev *hdev, char *buf, int len)
/* hclge_dbg_dump_mac_tnl_status: print message about mac tnl interrupt
* @hdev: pointer to struct hclge_dev
*/
static void hclge_dbg_dump_mac_tnl_status(struct hclge_dev *hdev)
static int
hclge_dbg_dump_mac_tnl_status(struct hclge_dev *hdev, char *buf, int len)
{
#define HCLGE_BILLION_NANO_SECONDS 1000000000
struct hclge_mac_tnl_stats stats;
unsigned long rem_nsec;
int pos = 0;
dev_info(&hdev->pdev->dev, "Recently generated mac tnl interruption:\n");
pos += scnprintf(buf + pos, len - pos,
"Recently generated mac tnl interruption:\n");
while (kfifo_get(&hdev->mac_tnl_log, &stats)) {
rem_nsec = do_div(stats.time, HCLGE_BILLION_NANO_SECONDS);
dev_info(&hdev->pdev->dev, "[%07lu.%03lu] status = 0x%x\n",
pos += scnprintf(buf + pos, len - pos,
"[%07lu.%03lu] status = 0x%x\n",
(unsigned long)stats.time, rem_nsec / 1000,
stats.status);
}
}
static void hclge_dbg_dump_qs_shaper_single(struct hclge_dev *hdev, u16 qsid)
{
struct hclge_qs_shapping_cmd *shap_cfg_cmd;
u8 ir_u, ir_b, ir_s, bs_b, bs_s;
struct hclge_desc desc;
u32 shapping_para;
u32 rate;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QCN_SHAPPING_CFG, true);
shap_cfg_cmd = (struct hclge_qs_shapping_cmd *)desc.data;
shap_cfg_cmd->qs_id = cpu_to_le16(qsid);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"qs%u failed to get tx_rate, ret=%d\n",
qsid, ret);
return;
}
shapping_para = le32_to_cpu(shap_cfg_cmd->qs_shapping_para);
ir_b = hclge_tm_get_field(shapping_para, IR_B);
ir_u = hclge_tm_get_field(shapping_para, IR_U);
ir_s = hclge_tm_get_field(shapping_para, IR_S);
bs_b = hclge_tm_get_field(shapping_para, BS_B);
bs_s = hclge_tm_get_field(shapping_para, BS_S);
rate = le32_to_cpu(shap_cfg_cmd->qs_rate);
dev_info(&hdev->pdev->dev,
"qs%u ir_b:%u, ir_u:%u, ir_s:%u, bs_b:%u, bs_s:%u, flag:%#x, rate:%u(Mbps)\n",
qsid, ir_b, ir_u, ir_s, bs_b, bs_s, shap_cfg_cmd->flag, rate);
}
static void hclge_dbg_dump_qs_shaper_all(struct hclge_dev *hdev)
{
struct hnae3_knic_private_info *kinfo;
struct hclge_vport *vport;
int vport_id, i;
for (vport_id = 0; vport_id <= pci_num_vf(hdev->pdev); vport_id++) {
vport = &hdev->vport[vport_id];
kinfo = &vport->nic.kinfo;
dev_info(&hdev->pdev->dev, "qs cfg of vport%d:\n", vport_id);
for (i = 0; i < kinfo->tc_info.num_tc; i++) {
u16 qsid = vport->qs_offset + i;
hclge_dbg_dump_qs_shaper_single(hdev, qsid);
}
}
return 0;
}
static void hclge_dbg_dump_qs_shaper(struct hclge_dev *hdev,
const char *cmd_buf)
{
u16 qsid;
int ret;
ret = kstrtou16(cmd_buf, 0, &qsid);
if (ret) {
hclge_dbg_dump_qs_shaper_all(hdev);
return;
}
if (qsid >= hdev->ae_dev->dev_specs.max_qset_num) {
dev_err(&hdev->pdev->dev, "qsid(%u) out of range[0-%u]\n",
qsid, hdev->ae_dev->dev_specs.max_qset_num - 1);
return;
}
hclge_dbg_dump_qs_shaper_single(hdev, qsid);
}
static const struct hclge_dbg_item mac_list_items[] = {
{ "FUNC_ID", 2 },
......@@ -1805,45 +1907,6 @@ static int hclge_dbg_dump_mac_mc(struct hclge_dev *hdev, char *buf, int len)
return 0;
}
int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf)
{
#define DUMP_REG "dump reg"
#define DUMP_TM_MAP "dump tm map"
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
if (strncmp(cmd_buf, "dump fd tcam", 12) == 0) {
hclge_dbg_fd_tcam(hdev);
} else if (strncmp(cmd_buf, "dump tc", 7) == 0) {
hclge_dbg_dump_tc(hdev);
} else if (strncmp(cmd_buf, DUMP_TM_MAP, strlen(DUMP_TM_MAP)) == 0) {
hclge_dbg_dump_tm_map(hdev, &cmd_buf[sizeof(DUMP_TM_MAP)]);
} else if (strncmp(cmd_buf, "dump tm", 7) == 0) {
hclge_dbg_dump_tm(hdev);
} else if (strncmp(cmd_buf, "dump qos pause cfg", 18) == 0) {
hclge_dbg_dump_qos_pause_cfg(hdev);
} else if (strncmp(cmd_buf, "dump qos pri map", 16) == 0) {
hclge_dbg_dump_qos_pri_map(hdev);
} else if (strncmp(cmd_buf, "dump qos buf cfg", 16) == 0) {
hclge_dbg_dump_qos_buf_cfg(hdev);
} else if (strncmp(cmd_buf, DUMP_REG, strlen(DUMP_REG)) == 0) {
hclge_dbg_dump_reg_cmd(hdev, &cmd_buf[sizeof(DUMP_REG)]);
} else if (strncmp(cmd_buf, "dump serv info", 14) == 0) {
hclge_dbg_dump_serv_info(hdev);
} else if (strncmp(cmd_buf, "dump mac tnl status", 19) == 0) {
hclge_dbg_dump_mac_tnl_status(hdev);
} else if (strncmp(cmd_buf, "dump qs shaper", 14) == 0) {
hclge_dbg_dump_qs_shaper(hdev,
&cmd_buf[sizeof("dump qs shaper")]);
} else {
dev_info(&hdev->pdev->dev, "unknown command\n");
return -EINVAL;
}
return 0;
}
static const struct hclge_dbg_func hclge_dbg_cmd_func[] = {
{
.cmd = HNAE3_DBG_CMD_TM_NODES,
......@@ -1857,6 +1920,34 @@ static const struct hclge_dbg_func hclge_dbg_cmd_func[] = {
.cmd = HNAE3_DBG_CMD_TM_QSET,
.dbg_dump = hclge_dbg_dump_tm_qset,
},
{
.cmd = HNAE3_DBG_CMD_TM_MAP,
.dbg_dump = hclge_dbg_dump_tm_map,
},
{
.cmd = HNAE3_DBG_CMD_TM_PG,
.dbg_dump = hclge_dbg_dump_tm_pg,
},
{
.cmd = HNAE3_DBG_CMD_TM_PORT,
.dbg_dump = hclge_dbg_dump_tm_port,
},
{
.cmd = HNAE3_DBG_CMD_TC_SCH_INFO,
.dbg_dump = hclge_dbg_dump_tc,
},
{
.cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG,
.dbg_dump = hclge_dbg_dump_qos_pause_cfg,
},
{
.cmd = HNAE3_DBG_CMD_QOS_PRI_MAP,
.dbg_dump = hclge_dbg_dump_qos_pri_map,
},
{
.cmd = HNAE3_DBG_CMD_QOS_BUF_CFG,
.dbg_dump = hclge_dbg_dump_qos_buf_cfg,
},
{
.cmd = HNAE3_DBG_CMD_MAC_UC,
.dbg_dump = hclge_dbg_dump_mac_uc,
......@@ -1889,18 +1980,81 @@ static const struct hclge_dbg_func hclge_dbg_cmd_func[] = {
.cmd = HNAE3_DBG_CMD_NCL_CONFIG,
.dbg_dump = hclge_dbg_dump_ncl_config,
},
{
.cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON,
.dbg_dump_reg = hclge_dbg_dump_reg_cmd,
},
{
.cmd = HNAE3_DBG_CMD_REG_SSU,
.dbg_dump_reg = hclge_dbg_dump_reg_cmd,
},
{
.cmd = HNAE3_DBG_CMD_REG_IGU_EGU,
.dbg_dump_reg = hclge_dbg_dump_reg_cmd,
},
{
.cmd = HNAE3_DBG_CMD_REG_RPU,
.dbg_dump_reg = hclge_dbg_dump_reg_cmd,
},
{
.cmd = HNAE3_DBG_CMD_REG_NCSI,
.dbg_dump_reg = hclge_dbg_dump_reg_cmd,
},
{
.cmd = HNAE3_DBG_CMD_REG_RTC,
.dbg_dump_reg = hclge_dbg_dump_reg_cmd,
},
{
.cmd = HNAE3_DBG_CMD_REG_PPP,
.dbg_dump_reg = hclge_dbg_dump_reg_cmd,
},
{
.cmd = HNAE3_DBG_CMD_REG_RCB,
.dbg_dump_reg = hclge_dbg_dump_reg_cmd,
},
{
.cmd = HNAE3_DBG_CMD_REG_TQP,
.dbg_dump_reg = hclge_dbg_dump_reg_cmd,
},
{
.cmd = HNAE3_DBG_CMD_REG_MAC,
.dbg_dump = hclge_dbg_dump_mac,
},
{
.cmd = HNAE3_DBG_CMD_REG_DCB,
.dbg_dump = hclge_dbg_dump_dcb,
},
{
.cmd = HNAE3_DBG_CMD_FD_TCAM,
.dbg_dump = hclge_dbg_dump_fd_tcam,
},
{
.cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS,
.dbg_dump = hclge_dbg_dump_mac_tnl_status,
},
{
.cmd = HNAE3_DBG_CMD_SERV_INFO,
.dbg_dump = hclge_dbg_dump_serv_info,
},
};
int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
char *buf, int len)
{
struct hclge_vport *vport = hclge_get_vport(handle);
const struct hclge_dbg_func *cmd_func;
struct hclge_dev *hdev = vport->back;
u32 i;
for (i = 0; i < ARRAY_SIZE(hclge_dbg_cmd_func); i++) {
if (cmd == hclge_dbg_cmd_func[i].cmd)
return hclge_dbg_cmd_func[i].dbg_dump(hdev, buf, len);
if (cmd == hclge_dbg_cmd_func[i].cmd) {
cmd_func = &hclge_dbg_cmd_func[i];
if (cmd_func->dbg_dump)
return cmd_func->dbg_dump(hdev, buf, len);
else
return cmd_func->dbg_dump_reg(hdev, cmd, buf,
len);
}
}
dev_err(&hdev->pdev->dev, "invalid command(%d)\n", cmd);
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h
View file @ dc185ae6
......@@ -69,6 +69,11 @@ struct hclge_dbg_reg_common_msg {
enum hclge_opcode_type cmd;
};
struct hclge_dbg_tcam_msg {
u8 stage;
u32 loc;
};
#define HCLGE_DBG_MAX_DFX_MSG_LEN 60
struct hclge_dbg_dfx_message {
int flag;
......@@ -77,7 +82,7 @@ struct hclge_dbg_dfx_message {
#define HCLGE_DBG_MAC_REG_TYPE_LEN 32
struct hclge_dbg_reg_type_info {
const char *reg_type;
enum hnae3_dbg_cmd cmd;
const struct hclge_dbg_dfx_message *dfx_msg;
struct hclge_dbg_reg_common_msg reg_msg;
};
......@@ -85,6 +90,8 @@ struct hclge_dbg_reg_type_info {
struct hclge_dbg_func {
enum hnae3_dbg_cmd cmd;
int (*dbg_dump)(struct hclge_dev *hdev, char *buf, int len);
int (*dbg_dump_reg)(struct hclge_dev *hdev, enum hnae3_dbg_cmd cmd,
char *buf, int len);
};
static const struct hclge_dbg_dfx_message hclge_dbg_bios_common_reg[] = {
......@@ -731,6 +738,10 @@ static const struct hclge_dbg_dfx_message hclge_dbg_tqp_reg[] = {
#define HCLGE_DBG_ID_LEN 16
#define HCLGE_DBG_ITEM_NAME_LEN 32
#define HCLGE_DBG_DATA_STR_LEN 32
#define HCLGE_DBG_TM_INFO_LEN 256
#define HCLGE_BILLION_NANO_SECONDS 1000000000
struct hclge_dbg_item {
char name[HCLGE_DBG_ITEM_NAME_LEN];
u16 interval; /* blank numbers after the item */
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
View file @ dc185ae6
......@@ -12610,7 +12610,6 @@ static const struct hnae3_ae_ops hclge_ops = {
.get_fd_all_rules = hclge_get_all_rules,
.enable_fd = hclge_enable_fd,
.add_arfs_entry = hclge_add_fd_entry_by_arfs,
.dbg_run_cmd = hclge_dbg_run_cmd,
.dbg_read_cmd = hclge_dbg_read_cmd,
.handle_hw_ras_error = hclge_handle_hw_ras_error,
.get_hw_reset_stat = hclge_get_hw_reset_stat,
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
View file @ dc185ae6
......@@ -1062,7 +1062,6 @@ int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);
int hclge_vport_start(struct hclge_vport *vport);
void hclge_vport_stop(struct hclge_vport *vport);
int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu);
int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf);
int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
char *buf, int len);
u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id);
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
View file @ dc185ae6
......@@ -1733,6 +1733,36 @@ int hclge_tm_get_qset_weight(struct hclge_dev *hdev, u16 qset_id, u8 *weight)
return 0;
}
int hclge_tm_get_qset_shaper(struct hclge_dev *hdev, u16 qset_id,
struct hclge_tm_shaper_para *para)
{
struct hclge_qs_shapping_cmd *shap_cfg_cmd;
struct hclge_desc desc;
u32 shapping_para;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QCN_SHAPPING_CFG, true);
shap_cfg_cmd = (struct hclge_qs_shapping_cmd *)desc.data;
shap_cfg_cmd->qs_id = cpu_to_le16(qset_id);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to get qset %u shaper, ret = %d\n", qset_id,
ret);
return ret;
}
shapping_para = le32_to_cpu(shap_cfg_cmd->qs_shapping_para);
para->ir_b = hclge_tm_get_field(shapping_para, IR_B);
para->ir_u = hclge_tm_get_field(shapping_para, IR_U);
para->ir_s = hclge_tm_get_field(shapping_para, IR_S);
para->bs_b = hclge_tm_get_field(shapping_para, BS_B);
para->bs_s = hclge_tm_get_field(shapping_para, BS_S);
para->flag = shap_cfg_cmd->flag;
para->rate = le32_to_cpu(shap_cfg_cmd->qs_rate);
return 0;
}
int hclge_tm_get_pri_sch_mode(struct hclge_dev *hdev, u8 pri_id, u8 *mode)
{
struct hclge_pri_sch_mode_cfg_cmd *pri_sch_mode;
......@@ -1775,7 +1805,7 @@ int hclge_tm_get_pri_weight(struct hclge_dev *hdev, u8 pri_id, u8 *weight)
int hclge_tm_get_pri_shaper(struct hclge_dev *hdev, u8 pri_id,
enum hclge_opcode_type cmd,
struct hclge_pri_shaper_para *para)
struct hclge_tm_shaper_para *para)
{
struct hclge_pri_shapping_cmd *shap_cfg_cmd;
struct hclge_desc desc;
......@@ -1807,3 +1837,186 @@ int hclge_tm_get_pri_shaper(struct hclge_dev *hdev, u8 pri_id,
para->rate = le32_to_cpu(shap_cfg_cmd->pri_rate);
return 0;
}
int hclge_tm_get_q_to_qs_map(struct hclge_dev *hdev, u16 q_id, u16 *qset_id)
{
struct hclge_nq_to_qs_link_cmd *map;
struct hclge_desc desc;
u16 qs_id_l;
u16 qs_id_h;
int ret;
map = (struct hclge_nq_to_qs_link_cmd *)desc.data;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NQ_TO_QS_LINK, true);
map->nq_id = cpu_to_le16(q_id);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to get queue to qset map, ret = %d\n", ret);
return ret;
}
*qset_id = le16_to_cpu(map->qset_id);
/* convert qset_id to the following format, drop the vld bit
* | qs_id_h | vld | qs_id_l |
* qset_id: | 15 ~ 11 | 10 | 9 ~ 0 |
* \ \ / /
* \ \ / /
* qset_id: | 15 | 14 ~ 10 | 9 ~ 0 |
*/
qs_id_l = hnae3_get_field(*qset_id, HCLGE_TM_QS_ID_L_MSK,
HCLGE_TM_QS_ID_L_S);
qs_id_h = hnae3_get_field(*qset_id, HCLGE_TM_QS_ID_H_EXT_MSK,
HCLGE_TM_QS_ID_H_EXT_S);
*qset_id = 0;
hnae3_set_field(*qset_id, HCLGE_TM_QS_ID_L_MSK, HCLGE_TM_QS_ID_L_S,
qs_id_l);
hnae3_set_field(*qset_id, HCLGE_TM_QS_ID_H_MSK, HCLGE_TM_QS_ID_H_S,
qs_id_h);
return 0;
}
int hclge_tm_get_q_to_tc(struct hclge_dev *hdev, u16 q_id, u8 *tc_id)
{
#define HCLGE_TM_TC_MASK 0x7
struct hclge_tqp_tx_queue_tc_cmd *tc;
struct hclge_desc desc;
int ret;
tc = (struct hclge_tqp_tx_queue_tc_cmd *)desc.data;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TQP_TX_QUEUE_TC, true);
tc->queue_id = cpu_to_le16(q_id);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to get queue to tc map, ret = %d\n", ret);
return ret;
}
*tc_id = tc->tc_id & HCLGE_TM_TC_MASK;
return 0;
}
int hclge_tm_get_pg_to_pri_map(struct hclge_dev *hdev, u8 pg_id,
u8 *pri_bit_map)
{
struct hclge_pg_to_pri_link_cmd *map;
struct hclge_desc desc;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_TO_PRI_LINK, true);
map = (struct hclge_pg_to_pri_link_cmd *)desc.data;
map->pg_id = pg_id;
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to get pg to pri map, ret = %d\n", ret);
return ret;
}
*pri_bit_map = map->pri_bit_map;
return 0;
}
int hclge_tm_get_pg_weight(struct hclge_dev *hdev, u8 pg_id, u8 *weight)
{
struct hclge_pg_weight_cmd *pg_weight_cmd;
struct hclge_desc desc;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_WEIGHT, true);
pg_weight_cmd = (struct hclge_pg_weight_cmd *)desc.data;
pg_weight_cmd->pg_id = pg_id;
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to get pg weight, ret = %d\n", ret);
return ret;
}
*weight = pg_weight_cmd->dwrr;
return 0;
}
int hclge_tm_get_pg_sch_mode(struct hclge_dev *hdev, u8 pg_id, u8 *mode)
{
struct hclge_desc desc;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_SCH_MODE_CFG, true);
desc.data[0] = cpu_to_le32(pg_id);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to get pg sch mode, ret = %d\n", ret);
return ret;
}
*mode = (u8)le32_to_cpu(desc.data[1]);
return 0;
}
int hclge_tm_get_pg_shaper(struct hclge_dev *hdev, u8 pg_id,
enum hclge_opcode_type cmd,
struct hclge_tm_shaper_para *para)
{
struct hclge_pg_shapping_cmd *shap_cfg_cmd;
struct hclge_desc desc;
u32 shapping_para;
int ret;
if (cmd != HCLGE_OPC_TM_PG_C_SHAPPING &&
cmd != HCLGE_OPC_TM_PG_P_SHAPPING)
return -EINVAL;
hclge_cmd_setup_basic_desc(&desc, cmd, true);
shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
shap_cfg_cmd->pg_id = pg_id;
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to get pg shaper(%#x), ret = %d\n",
cmd, ret);
return ret;
}
shapping_para = le32_to_cpu(shap_cfg_cmd->pg_shapping_para);
para->ir_b = hclge_tm_get_field(shapping_para, IR_B);
para->ir_u = hclge_tm_get_field(shapping_para, IR_U);
para->ir_s = hclge_tm_get_field(shapping_para, IR_S);
para->bs_b = hclge_tm_get_field(shapping_para, BS_B);
para->bs_s = hclge_tm_get_field(shapping_para, BS_S);
para->flag = shap_cfg_cmd->flag;
para->rate = le32_to_cpu(shap_cfg_cmd->pg_rate);
return 0;
}
int hclge_tm_get_port_shaper(struct hclge_dev *hdev,
struct hclge_tm_shaper_para *para)
{
struct hclge_port_shapping_cmd *port_shap_cfg_cmd;
struct hclge_desc desc;
u32 shapping_para;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to get port shaper, ret = %d\n", ret);
return ret;
}
port_shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data;
shapping_para = le32_to_cpu(port_shap_cfg_cmd->port_shapping_para);
para->ir_b = hclge_tm_get_field(shapping_para, IR_B);
para->ir_u = hclge_tm_get_field(shapping_para, IR_U);
para->ir_s = hclge_tm_get_field(shapping_para, IR_S);
para->bs_b = hclge_tm_get_field(shapping_para, BS_B);
para->bs_s = hclge_tm_get_field(shapping_para, BS_S);
para->flag = port_shap_cfg_cmd->flag;
para->rate = le32_to_cpu(port_shap_cfg_cmd->port_rate);
return 0;
}
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
View file @ dc185ae6
......@@ -199,14 +199,14 @@ struct hclge_tm_nodes_cmd {
__le16 queue_num;
};
struct hclge_pri_shaper_para {
struct hclge_tm_shaper_para {
u32 rate;
u8 ir_b;
u8 ir_u;
u8 ir_s;
u8 bs_b;
u8 bs_s;
u8 flag;
u32 rate;
};
#define hclge_tm_set_field(dest, string, val) \
......@@ -237,9 +237,22 @@ int hclge_tm_get_qset_map_pri(struct hclge_dev *hdev, u16 qset_id, u8 *priority,
u8 *link_vld);
int hclge_tm_get_qset_sch_mode(struct hclge_dev *hdev, u16 qset_id, u8 *mode);
int hclge_tm_get_qset_weight(struct hclge_dev *hdev, u16 qset_id, u8 *weight);
int hclge_tm_get_qset_shaper(struct hclge_dev *hdev, u16 qset_id,
struct hclge_tm_shaper_para *para);
int hclge_tm_get_pri_sch_mode(struct hclge_dev *hdev, u8 pri_id, u8 *mode);
int hclge_tm_get_pri_weight(struct hclge_dev *hdev, u8 pri_id, u8 *weight);
int hclge_tm_get_pri_shaper(struct hclge_dev *hdev, u8 pri_id,
enum hclge_opcode_type cmd,
struct hclge_pri_shaper_para *para);
struct hclge_tm_shaper_para *para);
int hclge_tm_get_q_to_qs_map(struct hclge_dev *hdev, u16 q_id, u16 *qset_id);
int hclge_tm_get_q_to_tc(struct hclge_dev *hdev, u16 q_id, u8 *tc_id);
int hclge_tm_get_pg_to_pri_map(struct hclge_dev *hdev, u8 pg_id,
u8 *pri_bit_map);
int hclge_tm_get_pg_weight(struct hclge_dev *hdev, u8 pg_id, u8 *weight);
int hclge_tm_get_pg_sch_mode(struct hclge_dev *hdev, u8 pg_id, u8 *mode);
int hclge_tm_get_pg_shaper(struct hclge_dev *hdev, u8 pg_id,
enum hclge_opcode_type cmd,
struct hclge_tm_shaper_para *para);
int hclge_tm_get_port_shaper(struct hclge_dev *hdev,
struct hclge_tm_shaper_para *para);
#endif
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