Commit dc2fc9f0 authored by Marek Behún's avatar Marek Behún Committed by Jakub Kicinski

net: dsa: mv88e6xxx: Don't support >1G speeds on 6191X on ports other than 10

Model 88E6191X only supports >1G speeds on port 10. Port 0 and 9 are
only 1G.

Fixes: de776d0d ("net: dsa: mv88e6xxx: add support for mv88e6393x family")
Signed-off-by: default avatarMarek Behún <kabel@kernel.org>
Cc: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20211104171747.10509-1-kabel@kernel.orgSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent fceb0795
...@@ -640,7 +640,10 @@ static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, ...@@ -640,7 +640,10 @@ static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
unsigned long *mask, unsigned long *mask,
struct phylink_link_state *state) struct phylink_link_state *state)
{ {
if (port == 0 || port == 9 || port == 10) { bool is_6191x =
chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
if (((port == 0 || port == 9) && !is_6191x) || port == 10) {
phylink_set(mask, 10000baseT_Full); phylink_set(mask, 10000baseT_Full);
phylink_set(mask, 10000baseKR_Full); phylink_set(mask, 10000baseKR_Full);
phylink_set(mask, 10000baseCR_Full); phylink_set(mask, 10000baseCR_Full);
......
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