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Commit dc3988f4 authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab Committed by Heiko Carstens
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docs: Debugging390.txt: convert table to ascii artwork 

The first bit/value table inside the document is very
hard to read and won't fit ReST format. Also, some columns aren't
properly aligned.

Convert it to a nice ascii artwork table with makes it easier to
read as plain text and is compatible with ReST format parser
on Sphinx.
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
Signed-off-by: default avatarHeiko Carstens <heiko.carstens@de.ibm.com>
parent 04310324
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Showing with 120 additions and 90 deletions
Documentation/s390/Debugging390.txt
View file @ dc3988f4
...@@ -78,96 +78,126 @@ e.g. switching address translation off requires that you ...@@ -78,96 +78,126 @@ e.g. switching address translation off requires that you
have a logical=physical mapping for the address you are have a logical=physical mapping for the address you are
currently running at. currently running at.
Bit Value +-------------------------+-------------------------------------------------+
s/390 z/Architecture | Bit | |
0 0 Reserved ( must be 0 ) otherwise specification exception occurs. +--------+----------------+ Value |
| s/390 | z/Architecture | |
1 1 Program Event Recording 1 PER enabled, +========+================+=================================================+
PER is used to facilitate debugging e.g. single stepping. | 0 | 0 | Reserved (must be 0) otherwise specification |
| | | exception occurs. |
2-4 2-4 Reserved ( must be 0 ). +--------+----------------+-------------------------------------------------+
| 1 | 1 | Program Event Recording 1 PER enabled, |
5 5 Dynamic address translation 1=DAT on. | | | PER is used to facilitate debugging e.g. |
| | | single stepping. |
6 6 Input/Output interrupt Mask +--------+----------------+-------------------------------------------------+
| 2-4 | 2-4 | Reserved (must be 0). |
7 7 External interrupt Mask used primarily for interprocessor +--------+----------------+-------------------------------------------------+
signalling and clock interrupts. | 5 | 5 | Dynamic address translation 1=DAT on. |
+--------+----------------+-------------------------------------------------+
8-11 8-11 PSW Key used for complex memory protection mechanism | 6 | 6 | Input/Output interrupt Mask |
(not used under linux) +--------+----------------+-------------------------------------------------+
| 7 | 7 | External interrupt Mask used primarily for |
12 12 1 on s/390 0 on z/Architecture | | | interprocessor signalling and clock interrupts. |
+--------+----------------+-------------------------------------------------+
13 13 Machine Check Mask 1=enable machine check interrupts | 8-11 | 8-11 | PSW Key used for complex memory protection |
| | | mechanism (not used under linux) |
14 14 Wait State. Set this to 1 to stop the processor except for +--------+----------------+-------------------------------------------------+
interrupts and give time to other LPARS. Used in CPU idle in | 12 | 12 | 1 on s/390 0 on z/Architecture |
the kernel to increase overall usage of processor resources. +--------+----------------+-------------------------------------------------+
| 13 | 13 | Machine Check Mask 1=enable machine check |
15 15 Problem state ( if set to 1 certain instructions are disabled ) | | | interrupts |
all linux user programs run with this bit 1 +--------+----------------+-------------------------------------------------+
( useful info for debugging under VM ). | 14 | 14 | Wait State. Set this to 1 to stop the processor |
| | | except for interrupts and give time to other |
16-17 16-17 Address Space Control | | | LPARS. Used in CPU idle in the kernel to |
| | | increase overall usage of processor resources. |
00 Primary Space Mode: +--------+----------------+-------------------------------------------------+
The register CR1 contains the primary address-space control ele- | 15 | 15 | Problem state (if set to 1 certain instructions |
ment (PASCE), which points to the primary space region/segment | | | are disabled). All linux user programs run with |
table origin. | | | this bit 1 (useful info for debugging under VM).|
+--------+----------------+-------------------------------------------------+
01 Access register mode | 16-17 | 16-17 | Address Space Control |
| | | |
10 Secondary Space Mode: | | | 00 Primary Space Mode: |
The register CR7 contains the secondary address-space control | | | |
element (SASCE), which points to the secondary space region or | | | The register CR1 contains the primary |
segment table origin. | | | address-space control element (PASCE), which |
| | | points to the primary space region/segment |
11 Home Space Mode: | | | table origin. |
The register CR13 contains the home space address-space control | | | |
element (HASCE), which points to the home space region/segment | | | 01 Access register mode |
table origin. | | | |
| | | 10 Secondary Space Mode: |
See "Address Spaces on Linux for s/390 & z/Architecture" below | | | |
for more information about address space usage in Linux. | | | The register CR7 contains the secondary |
| | | address-space control element (SASCE), which |
18-19 18-19 Condition codes (CC) | | | points to the secondary space region or |
| | | segment table origin. |
20 20 Fixed point overflow mask if 1=FPU exceptions for this event | | | |
occur ( normally 0 ) | | | 11 Home Space Mode: |
| | | |
21 21 Decimal overflow mask if 1=FPU exceptions for this event occur | | | The register CR13 contains the home space |
( normally 0 ) | | | address-space control element (HASCE), which |
| | | points to the home space region/segment |
22 22 Exponent underflow mask if 1=FPU exceptions for this event occur | | | table origin. |
( normally 0 ) | | | |
| | | See "Address Spaces on Linux for s/390 & |
23 23 Significance Mask if 1=FPU exceptions for this event occur | | | z/Architecture" below for more information |
( normally 0 ) | | | about address space usage in Linux. |
+--------+----------------+-------------------------------------------------+
24-31 24-30 Reserved Must be 0. | 18-19 | 18-19 | Condition codes (CC) |
+--------+----------------+-------------------------------------------------+
31 Extended Addressing Mode | 20 | 20 | Fixed point overflow mask if 1=FPU exceptions |
32 Basic Addressing Mode | | | for this event occur (normally 0) |
Used to set addressing mode +--------+----------------+-------------------------------------------------+
PSW 31 PSW 32 | 21 | 21 | Decimal overflow mask if 1=FPU exceptions for |
0 0 24 bit | | | this event occur (normally 0) |
0 1 31 bit +--------+----------------+-------------------------------------------------+
1 1 64 bit | 22 | 22 | Exponent underflow mask if 1=FPU exceptions |
| | | for this event occur (normally 0) |
32 1=31 bit addressing mode 0=24 bit addressing mode (for backward +--------+----------------+-------------------------------------------------+
compatibility), linux always runs with this bit set to 1 | 23 | 23 | Significance Mask if 1=FPU exceptions for this |
| | | event occur (normally 0) |
33-64 Instruction address. +--------+----------------+-------------------------------------------------+
33-63 Reserved must be 0 | 24-31 | 24-30 | Reserved Must be 0. |
64-127 Address | +----------------+-------------------------------------------------+
In 24 bits mode bits 64-103=0 bits 104-127 Address | | 31 | Extended Addressing Mode |
In 31 bits mode bits 64-96=0 bits 97-127 Address | +----------------+-------------------------------------------------+
Note: unlike 31 bit mode on s/390 bit 96 must be zero | | 32 | Basic Addressing Mode |
when loading the address with LPSWE otherwise a | | | |
specification exception occurs, LPSW is fully backward | | | Used to set addressing mode |
compatible. | | | |
| | | +---------+----------+----------+ |
| | | | PSW 31 | PSW 32 | | |
| | | +---------+----------+----------+ |
| | | | 0 | 0 | 24 bit | |
| | | +---------+----------+----------+ |
| | | | 0 | 1 | 31 bit | |
| | | +---------+----------+----------+ |
| | | | 1 | 1 | 64 bit | |
| | | +---------+----------+----------+ |
+--------+----------------+-------------------------------------------------+
| 32 | | 1=31 bit addressing mode 0=24 bit addressing |
| | | mode (for backward compatibility), linux |
| | | always runs with this bit set to 1 |
+--------+----------------+-------------------------------------------------+
| 33-64 | | Instruction address. |
| +----------------+-------------------------------------------------+
| | 33-63 | Reserved must be 0 |
| +----------------+-------------------------------------------------+
| | 64-127 | Address |
| | | |
| | | - In 24 bits mode bits 64-103=0 bits 104-127 |
| | | Address |
| | | - In 31 bits mode bits 64-96=0 bits 97-127 |
| | | Address |
| | | |
| | | Note: |
| | | unlike 31 bit mode on s/390 bit 96 must be |
| | | zero when loading the address with LPSWE |
| | | otherwise a specification exception occurs, |
| | | LPSW is fully backward compatible. |
+--------+----------------+-------------------------------------------------+
Prefix Page(s) Prefix Page(s)
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