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Commit dc745ece authored by Russell King's avatar Russell King Committed by David S. Miller
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net: dsa: mv88e6xxx: remove port_link_state functions 

The port_link_state method is only used by mv88e6xxx_port_setup_mac(),
which is now only called during port setup, rather than also being
called via phylink's mac_config method.

Remove this now unnecessary optimisation, which allows us to remove the
port_link_state methods as well.
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent f365c6f7
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drivers/net/dsa/mv88e6xxx/chip.c
View file @ dc745ece
This diff is collapsed.
drivers/net/dsa/mv88e6xxx/chip.h
View file @ dc745ece
......@@ -458,9 +458,6 @@ struct mv88e6xxx_ops {
*/
int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
int upstream_port);
/* Return the port link state, as required by phylink */
int (*port_link_state)(struct mv88e6xxx_chip *chip, int port,
struct phylink_link_state *state);
/* Snapshot the statistics for a port. The statistics can then
* be read back a leisure but still with a consistent view.
......
drivers/net/dsa/mv88e6xxx/port.c
View file @ dc745ece
......@@ -584,183 +584,6 @@ int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
return 0;
}
int mv88e6250_port_link_state(struct mv88e6xxx_chip *chip, int port,
struct phylink_link_state *state)
{
int err;
u16 reg;
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
if (err)
return err;
if (port < 5) {
switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
case MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF:
state->speed = SPEED_10;
state->duplex = DUPLEX_HALF;
break;
case MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF:
state->speed = SPEED_100;
state->duplex = DUPLEX_HALF;
break;
case MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL:
state->speed = SPEED_10;
state->duplex = DUPLEX_FULL;
break;
case MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL:
state->speed = SPEED_100;
state->duplex = DUPLEX_FULL;
break;
default:
state->speed = SPEED_UNKNOWN;
state->duplex = DUPLEX_UNKNOWN;
break;
}
} else {
switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF:
state->speed = SPEED_10;
state->duplex = DUPLEX_HALF;
break;
case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF:
state->speed = SPEED_100;
state->duplex = DUPLEX_HALF;
break;
case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL:
state->speed = SPEED_10;
state->duplex = DUPLEX_FULL;
break;
case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL:
state->speed = SPEED_100;
state->duplex = DUPLEX_FULL;
break;
default:
state->speed = SPEED_UNKNOWN;
state->duplex = DUPLEX_UNKNOWN;
break;
}
}
state->link = !!(reg & MV88E6250_PORT_STS_LINK);
state->an_enabled = 1;
state->an_complete = state->link;
state->interface = PHY_INTERFACE_MODE_NA;
return 0;
}
int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,
struct phylink_link_state *state)
{
int err;
u16 reg;
switch (chip->ports[port].cmode) {
case MV88E6XXX_PORT_STS_CMODE_RGMII:
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL,
&reg);
if (err)
return err;
if ((reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK) &&
(reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK))
state->interface = PHY_INTERFACE_MODE_RGMII_ID;
else if (reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK)
state->interface = PHY_INTERFACE_MODE_RGMII_RXID;
else if (reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK)
state->interface = PHY_INTERFACE_MODE_RGMII_TXID;
else
state->interface = PHY_INTERFACE_MODE_RGMII;
break;
case MV88E6XXX_PORT_STS_CMODE_1000BASEX:
state->interface = PHY_INTERFACE_MODE_1000BASEX;
break;
case MV88E6XXX_PORT_STS_CMODE_SGMII:
state->interface = PHY_INTERFACE_MODE_SGMII;
break;
case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
state->interface = PHY_INTERFACE_MODE_2500BASEX;
break;
case MV88E6XXX_PORT_STS_CMODE_XAUI:
state->interface = PHY_INTERFACE_MODE_XAUI;
break;
case MV88E6XXX_PORT_STS_CMODE_RXAUI:
state->interface = PHY_INTERFACE_MODE_RXAUI;
break;
default:
/* we do not support other cmode values here */
state->interface = PHY_INTERFACE_MODE_NA;
}
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
if (err)
return err;
switch (reg & MV88E6XXX_PORT_STS_SPEED_MASK) {
case MV88E6XXX_PORT_STS_SPEED_10:
state->speed = SPEED_10;
break;
case MV88E6XXX_PORT_STS_SPEED_100:
state->speed = SPEED_100;
break;
case MV88E6XXX_PORT_STS_SPEED_1000:
state->speed = SPEED_1000;
break;
case MV88E6XXX_PORT_STS_SPEED_10000:
if ((reg & MV88E6XXX_PORT_STS_CMODE_MASK) ==
MV88E6XXX_PORT_STS_CMODE_2500BASEX)
state->speed = SPEED_2500;
else
state->speed = SPEED_10000;
break;
}
state->duplex = reg & MV88E6XXX_PORT_STS_DUPLEX ?
DUPLEX_FULL : DUPLEX_HALF;
state->link = !!(reg & MV88E6XXX_PORT_STS_LINK);
state->an_enabled = 1;
state->an_complete = state->link;
return 0;
}
int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
struct phylink_link_state *state)
{
if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
u8 cmode = chip->ports[port].cmode;
/* When a port is in "Cross-chip serdes" mode, it uses
* 1000Base-X full duplex mode, but there is no automatic
* link detection. Use the sync OK status for link (as it
* would do for 1000Base-X mode.)
*/
if (cmode == MV88E6185_PORT_STS_CMODE_SERDES) {
u16 mac;
int err;
err = mv88e6xxx_port_read(chip, port,
MV88E6XXX_PORT_MAC_CTL, &mac);
if (err)
return err;
state->link = !!(mac & MV88E6185_PORT_MAC_CTL_SYNC_OK);
state->an_enabled = 1;
state->an_complete =
!!(mac & MV88E6185_PORT_MAC_CTL_AN_DONE);
state->duplex =
state->link ? DUPLEX_FULL : DUPLEX_UNKNOWN;
state->speed =
state->link ? SPEED_1000 : SPEED_UNKNOWN;
return 0;
}
}
return mv88e6352_port_link_state(chip, port, state);
}
/* Offset 0x02: Jamming Control
*
* Do not limit the period of time that this port can be paused for by
......
drivers/net/dsa/mv88e6xxx/port.h
View file @ dc745ece
......@@ -364,12 +364,6 @@ int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
phy_interface_t mode);
int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
struct phylink_link_state *state);
int mv88e6250_port_link_state(struct mv88e6xxx_chip *chip, int port,
struct phylink_link_state *state);
int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,
struct phylink_link_state *state);
int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port);
int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
int upstream_port);
......
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