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Commit dcd68326 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'devicetree-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull devicetree updates from Rob Herring:

 - Convert /reserved-memory bindings to schemas

 - Convert a bunch of NFC bindings to schemas

 - Convert bindings to schema: Xilinx USB, Freescale DDR controller, Arm
   CCI-400, UBlox Neo-6M, 1-Wire GPIO, MSI controller, ASpeed LPC, OMAP
   and Inside-Secure HWRNG, register-bit-led, OV5640, Silead GSL1680,
   Elan ekth3000, Marvell bluetooth, TI wlcore, TI bluetooth, ESP
   ESP8089, tlm,trusted-foundations, Microchip cap11xx, Ralink SoCs and
   boards, and TI sysc

 - New binding schemas for: msi-ranges, Aspeed UART routing controller,
   palmbus, Xylon LogiCVC display controller, Mediatek's MT7621 SDRAM
   memory controller, and Apple M1 PCIe host

 - Run schema checks for %.dtb targets

 - Improve build time when using DT_SCHEMA_FILES

 - Improve error message when dtschema is not found

 - Various doc reference fixes in MAINTAINERS

 - Convert architectures to common CPU h/w ID parsing function
   of_get_cpu_hwid().

 - Allow for empty NUMA node IDs which may be hotplugged

 - Cleanup of __fdt_scan_reserved_mem()

 - Constify device_node parameters

 - Update dtc to upstream v1.6.1-19-g0a3a9d3449c8. Adds new checks
   'node_name_vs_property_name' and 'interrupt_map'.

 - Enable dtc 'unit_address_format' warning by default

 - Fix unittest EXPECT text for gpio hog errors

* tag 'devicetree-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (97 commits)
  dt-bindings: net: ti,bluetooth: Document default max-speed
  dt-bindings: pci: rcar-pci-ep: Document r8a7795
  dt-bindings: net: qcom,ipa: IPA does support up to two iommus
  of/fdt: Remove of_scan_flat_dt() usage for __fdt_scan_reserved_mem()
  of: unittest: document intentional interrupt-map provider build warning
  of: unittest: fix EXPECT text for gpio hog errors
  of/unittest: Disable new dtc node_name_vs_property_name and interrupt_map warnings
  scripts/dtc: Update to upstream version v1.6.1-19-g0a3a9d3449c8
  dt-bindings: arm: firmware: tlm,trusted-foundations: Convert txt bindings to yaml
  dt-bindings: display: tilcd: Fix endpoint addressing in example
  dt-bindings: input: microchip,cap11xx: Convert txt bindings to yaml
  dt-bindings: ufs: exynos-ufs: add exynosautov9 compatible
  dt-bindings: ufs: exynos-ufs: add io-coherency property
  dt-bindings: mips: convert Ralink SoCs and boards to schema
  dt-bindings: display: xilinx: Fix example with psgtr
  dt-bindings: net: nfc: nxp,pn544: Convert txt bindings to yaml
  dt-bindings: Add a help message when dtschema tools are missing
  dt-bindings: bus: ti-sysc: Update to use yaml binding
  dt-bindings: sram: Allow numbers in sram region node name
  dt-bindings: display: Document the Xylon LogiCVC display controller
  ...
parents 624ad333 4c7a7d50
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Showing with 4301 additions and 2251 deletions
Documentation/admin-guide/ramoops.rst
View file @ dcd68326
......@@ -69,7 +69,7 @@ Setting the ramoops parameters can be done in several different manners:
mem=128M ramoops.mem_address=0x8000000 ramoops.ecc=1
B. Use Device Tree bindings, as described in
``Documentation/devicetree/bindings/reserved-memory/ramoops.txt``.
``Documentation/devicetree/bindings/reserved-memory/ramoops.yaml``.
For example::
reserved-memory {
......
Documentation/devicetree/bindings/Makefile
View file @ dcd68326
......@@ -9,6 +9,11 @@ DT_SCHEMA_MIN_VERSION = 2021.2.1
PHONY += check_dtschema_version
check_dtschema_version:
@which $(DT_DOC_CHECKER) >/dev/null || \
{ echo "Error: '$(DT_DOC_CHECKER)' not found!" >&2; \
echo "Ensure dtschema python package is installed and in your PATH." >&2; \
echo "Current PATH is:" >&2; \
echo "$$PATH" >&2; false; }
@{ echo $(DT_SCHEMA_MIN_VERSION); \
$(DT_DOC_CHECKER) --version 2>/dev/null || echo 0; } | sort -Vc >/dev/null || \
{ echo "ERROR: dtschema minimum version is v$(DT_SCHEMA_MIN_VERSION)" >&2; false; }
......@@ -22,13 +27,20 @@ $(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
# Use full schemas when checking %.example.dts
DT_TMP_SCHEMA := $(obj)/processed-schema-examples.json
find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
-name 'processed-schema*' ! \
-name '*.example.dt.yaml' \)
ifeq ($(DT_SCHEMA_FILES),)
find_cmd = $(find_all_cmd)
else
find_cmd = echo $(addprefix $(srctree)/, $(DT_SCHEMA_FILES))
endif
quiet_cmd_yamllint = LINT $(src)
cmd_yamllint = ($(find_cmd) | \
xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true
xargs -n200 -P$$(nproc) \
$(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true
quiet_cmd_chk_bindings = CHKDT $@
cmd_chk_bindings = ($(find_cmd) | \
......@@ -38,7 +50,7 @@ quiet_cmd_mk_schema = SCHEMA $@
cmd_mk_schema = f=$$(mktemp) ; \
$(if $(DT_MK_SCHEMA_FLAGS), \
printf '%s\n' $(real-prereqs), \
$(find_cmd)) > $$f ; \
$(find_all_cmd)) > $$f ; \
$(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \
rm -f $$f
......@@ -48,7 +60,7 @@ define rule_chkdt
$(call cmd,mk_schema)
endef
DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_cmd)))
DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd)))
override DTC_FLAGS := \
-Wno-avoid_unnecessary_addr_size \
......
Documentation/devicetree/bindings/arm/arm,cci-400.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM CCI Cache Coherent Interconnect Device Tree Binding
maintainers:
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
description: >
ARM multi-cluster systems maintain intra-cluster coherency through a cache
coherent interconnect (CCI) that is capable of monitoring bus transactions
and manage coherency, TLB invalidations and memory barriers.
It allows snooping and distributed virtual memory message broadcast across
clusters, through memory mapped interface, with a global control register
space and multiple sets of interface control registers, one per slave
interface.
properties:
$nodename:
pattern: "^cci(@[0-9a-f]+)?$"
compatible:
enum:
- arm,cci-400
- arm,cci-500
- arm,cci-550
reg:
maxItems: 1
description: >
Specifies base physical address of CCI control registers common to all
interfaces.
"#address-cells": true
"#size-cells": true
ranges: true
patternProperties:
"^slave-if@[0-9a-f]+$":
type: object
properties:
compatible:
const: arm,cci-400-ctrl-if
interface-type:
enum:
- ace
- ace-lite
reg:
maxItems: 1
required:
- compatible
- interface-type
- reg
additionalProperties: false
"^pmu@[0-9a-f]+$":
type: object
properties:
compatible:
oneOf:
- const: arm,cci-400-pmu,r0
- const: arm,cci-400-pmu,r1
- const: arm,cci-400-pmu
deprecated: true
description: >
Permitted only where OS has secure access to CCI registers
- const: arm,cci-500-pmu,r0
- const: arm,cci-550-pmu,r0
interrupts:
minItems: 1
maxItems: 8
description: >
List of counter overflow interrupts, one per counter. The interrupts
must be specified starting with the cycle counter overflow interrupt,
followed by counter0 overflow interrupt, counter1 overflow
interrupt,... ,counterN overflow interrupt.
The CCI PMU has an interrupt signal for each counter. The number of
interrupts must be equal to the number of counters.
reg:
maxItems: 1
required:
- compatible
- interrupts
- reg
additionalProperties: false
required:
- "#address-cells"
- "#size-cells"
- compatible
- ranges
- reg
additionalProperties: false
examples:
- |
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
model = "V2P-CA15_CA7";
arm,hbi = <0x249>;
interrupt-parent = <&gic>;
/*
* This CCI node corresponds to a CCI component whose control
* registers sits at address 0x000000002c090000.
*
* CCI slave interface @0x000000002c091000 is connected to dma
* controller dma0.
*
* CCI slave interface @0x000000002c094000 is connected to CPUs
* {CPU0, CPU1};
*
* CCI slave interface @0x000000002c095000 is connected to CPUs
* {CPU2, CPU3};
*/
cpus {
#size-cells = <0>;
#address-cells = <1>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
cci-control-port = <&cci_control1>;
reg = <0x0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
cci-control-port = <&cci_control1>;
reg = <0x1>;
};
CPU2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
cci-control-port = <&cci_control2>;
reg = <0x100>;
};
CPU3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
cci-control-port = <&cci_control2>;
reg = <0x101>;
};
};
dma0: dma@3000000 {
/* compatible = "arm,pl330", "arm,primecell"; */
cci-control-port = <&cci_control0>;
reg = <0x0 0x3000000 0x0 0x1000>;
interrupts = <10>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
cci@2c090000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x2c090000 0 0x1000>;
ranges = <0x0 0x0 0x2c090000 0x10000>;
cci_control0: slave-if@1000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace-lite";
reg = <0x1000 0x1000>;
};
cci_control1: slave-if@4000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x4000 0x1000>;
};
cci_control2: slave-if@5000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x5000 0x1000>;
};
pmu@9000 {
compatible = "arm,cci-400-pmu";
reg = <0x9000 0x5000>;
interrupts = <0 101 4>,
<0 102 4>,
<0 103 4>,
<0 104 4>,
<0 105 4>;
};
};
};
...
Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
View file @ dcd68326
......@@ -119,22 +119,6 @@ properties:
- const: arm,foundation-aarch64
- const: arm,vexpress
arm,hbi:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: This indicates the ARM HBI (Hardware Board ID), this is
ARM's unique board model ID, visible on the PCB's silkscreen.
arm,vexpress,site:
description: As Versatile Express can be configured in number of physically
different setups, the device tree should describe platform topology.
For this reason the root node and main motherboard node must define this
property, describing the physical location of the children nodes.
0 means motherboard site, while 1 and 2 are daughterboard sites, and
0xf means "sisterboard" which is the site containing the main CPU tile.
$ref: '/schemas/types.yaml#/definitions/uint32'
minimum: 0
maximum: 15
arm,vexpress,position:
description: When daughterboards are stacked on one site, their position
in the stack be be described this attribute.
......@@ -154,9 +138,9 @@ patternProperties:
description: Static Memory Bus (SMB) node, if this exists it describes
the connection between the motherboard and any tiles. Sometimes the
compatible is placed directly under this node, sometimes it is placed
in a subnode named "motherboard". Sometimes the compatible includes
in a subnode named "motherboard-bus". Sometimes the compatible includes
"arm,vexpress,v2?-p1" sometimes (on software models) is is just
"simple-bus". If the compatible is placed in the "motherboard" node,
"simple-bus". If the compatible is placed in the "motherboard-bus" node,
it is stricter and always has two compatibles.
type: object
$ref: '/schemas/simple-bus.yaml'
......@@ -170,7 +154,9 @@ patternProperties:
- arm,vexpress,v2p-p1
- const: simple-bus
- const: simple-bus
motherboard:
patternProperties:
'^motherboard-bus@':
type: object
description: The motherboard description provides a single "motherboard"
node using 2 address cells corresponding to the Static Memory Bus
......@@ -183,6 +169,8 @@ patternProperties:
const: 2
"#size-cells":
const: 1
ranges: true
compatible:
items:
- enum:
......@@ -196,8 +184,28 @@ patternProperties:
- rs1
- rs2
arm,hbi:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: This indicates the ARM HBI (Hardware Board ID), this is
ARM's unique board model ID, visible on the PCB's silkscreen.
arm,vexpress,site:
description: As Versatile Express can be configured in number of physically
different setups, the device tree should describe platform topology.
For this reason the root node and main motherboard node must define this
property, describing the physical location of the children nodes.
0 means motherboard site, while 1 and 2 are daughterboard sites, and
0xf means "sisterboard" which is the site containing the main CPU tile.
$ref: '/schemas/types.yaml#/definitions/uint32'
minimum: 0
maximum: 15
required:
- compatible
additionalProperties:
type: object
required:
- compatible
......
Documentation/devicetree/bindings/arm/cci-control-port.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CCI Interconnect Bus Masters binding
maintainers:
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
description: |
Masters in the device tree connected to a CCI port (inclusive of CPUs
and their cpu nodes).
select: true
properties:
cci-control-port:
$ref: /schemas/types.yaml#/definitions/phandle
additionalProperties: true
examples:
- |
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a15";
device_type = "cpu";
cci-control-port = <&cci_control1>;
reg = <0>;
};
};
...
Documentation/devicetree/bindings/arm/cci.txt deleted 100644 → 0
View file @ 624ad333
=======================================================
ARM CCI cache coherent interconnect binding description
=======================================================
ARM multi-cluster systems maintain intra-cluster coherency through a
cache coherent interconnect (CCI) that is capable of monitoring bus
transactions and manage coherency, TLB invalidations and memory barriers.
It allows snooping and distributed virtual memory message broadcast across
clusters, through memory mapped interface, with a global control register
space and multiple sets of interface control registers, one per slave
interface.
* CCI interconnect node
Description: Describes a CCI cache coherent Interconnect component
Node name must be "cci".
Node's parent must be the root node /, and the address space visible
through the CCI interconnect is the same as the one seen from the
root node (ie from CPUs perspective as per DT standard).
Every CCI node has to define the following properties:
- compatible
Usage: required
Value type: <string>
Definition: must contain one of the following:
"arm,cci-400"
"arm,cci-500"
"arm,cci-550"
- reg
Usage: required
Value type: Integer cells. A register entry, expressed as a pair
of cells, containing base and size.
Definition: A standard property. Specifies base physical
address of CCI control registers common to all
interfaces.
- ranges:
Usage: required
Value type: Integer cells. An array of range entries, expressed
as a tuple of cells, containing child address,
parent address and the size of the region in the
child address space.
Definition: A standard property. Follow rules in the Devicetree
Specification for hierarchical bus addressing. CCI
interfaces addresses refer to the parent node
addressing scheme to declare their register bases.
CCI interconnect node can define the following child nodes:
- CCI control interface nodes
Node name must be "slave-if".
Parent node must be CCI interconnect node.
A CCI control interface node must contain the following
properties:
- compatible
Usage: required
Value type: <string>
Definition: must be set to
"arm,cci-400-ctrl-if"
- interface-type:
Usage: required
Value type: <string>
Definition: must be set to one of {"ace", "ace-lite"}
depending on the interface type the node
represents.
- reg:
Usage: required
Value type: Integer cells. A register entry, expressed
as a pair of cells, containing base and
size.
Definition: the base address and size of the
corresponding interface programming
registers.
- CCI PMU node
Parent node must be CCI interconnect node.
A CCI pmu node must contain the following properties:
- compatible
Usage: required
Value type: <string>
Definition: Must contain one of:
"arm,cci-400-pmu,r0"
"arm,cci-400-pmu,r1"
"arm,cci-400-pmu" - DEPRECATED, permitted only where OS has
secure access to CCI registers
"arm,cci-500-pmu,r0"
"arm,cci-550-pmu,r0"
- reg:
Usage: required
Value type: Integer cells. A register entry, expressed
as a pair of cells, containing base and
size.
Definition: the base address and size of the
corresponding interface programming
registers.
- interrupts:
Usage: required
Value type: Integer cells. Array of interrupt specifier
entries, as defined in
../interrupt-controller/interrupts.txt.
Definition: list of counter overflow interrupts, one per
counter. The interrupts must be specified
starting with the cycle counter overflow
interrupt, followed by counter0 overflow
interrupt, counter1 overflow interrupt,...
,counterN overflow interrupt.
The CCI PMU has an interrupt signal for each
counter. The number of interrupts must be
equal to the number of counters.
* CCI interconnect bus masters
Description: masters in the device tree connected to a CCI port
(inclusive of CPUs and their cpu nodes).
A CCI interconnect bus master node must contain the following
properties:
- cci-control-port:
Usage: required
Value type: <phandle>
Definition: a phandle containing the CCI control interface node
the master is connected to.
Example:
cpus {
#size-cells = <0>;
#address-cells = <1>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
cci-control-port = <&cci_control1>;
reg = <0x0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
cci-control-port = <&cci_control1>;
reg = <0x1>;
};
CPU2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
cci-control-port = <&cci_control2>;
reg = <0x100>;
};
CPU3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
cci-control-port = <&cci_control2>;
reg = <0x101>;
};
};
dma0: dma@3000000 {
compatible = "arm,pl330", "arm,primecell";
cci-control-port = <&cci_control0>;
reg = <0x0 0x3000000 0x0 0x1000>;
interrupts = <10>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
cci@2c090000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x2c090000 0 0x1000>;
ranges = <0x0 0x0 0x2c090000 0x10000>;
cci_control0: slave-if@1000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace-lite";
reg = <0x1000 0x1000>;
};
cci_control1: slave-if@4000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x4000 0x1000>;
};
cci_control2: slave-if@5000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x5000 0x1000>;
};
pmu@9000 {
compatible = "arm,cci-400-pmu";
reg = <0x9000 0x5000>;
interrupts = <0 101 4>,
<0 102 4>,
<0 103 4>,
<0 104 4>,
<0 105 4>;
};
};
This CCI node corresponds to a CCI component whose control registers sits
at address 0x000000002c090000.
CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
Documentation/devicetree/bindings/arm/cpus.yaml
View file @ dcd68326
......@@ -240,6 +240,8 @@ properties:
DMIPS/MHz, relative to highest capacity-dmips-mhz
in the system.
cci-control-port: true
dynamic-power-coefficient:
$ref: '/schemas/types.yaml#/definitions/uint32'
description:
......
Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt deleted 100644 → 0
View file @ 624ad333
Trusted Foundations
-------------------
Boards that use the Trusted Foundations secure monitor can signal its
presence by declaring a node compatible with "tlm,trusted-foundations"
under the /firmware/ node
Required properties:
- compatible: "tlm,trusted-foundations"
- tlm,version-major: major version number of Trusted Foundations firmware
- tlm,version-minor: minor version number of Trusted Foundations firmware
Example:
firmware {
trusted-foundations {
compatible = "tlm,trusted-foundations";
tlm,version-major = <2>;
tlm,version-minor = <8>;
};
};
Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/firmware/tlm,trusted-foundations.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Trusted Foundations
description: |
Boards that use the Trusted Foundations secure monitor can signal its
presence by declaring a node compatible under the /firmware/ node
maintainers:
- Stephen Warren <swarren@nvidia.com>
properties:
$nodename:
const: trusted-foundations
compatible:
const: tlm,trusted-foundations
tlm,version-major:
$ref: /schemas/types.yaml#/definitions/uint32
description: major version number of Trusted Foundations firmware
tlm,version-minor:
$ref: /schemas/types.yaml#/definitions/uint32
description: minor version number of Trusted Foundations firmware
required:
- compatible
- tlm,version-major
- tlm,version-minor
additionalProperties: false
examples:
- |
firmware {
trusted-foundations {
compatible = "tlm,trusted-foundations";
tlm,version-major = <2>;
tlm,version-minor = <8>;
};
};
Documentation/devicetree/bindings/bus/palmbus.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/palmbus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ralink PalmBus Device Tree Bindings
maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description: |
The ralink palmbus controller can be found in all ralink MIPS
SoCs. It provides an external bus for connecting multiple
external devices to the SoC.
properties:
$nodename:
pattern: "^palmbus(@[0-9a-f]+)?$"
"#address-cells":
const: 1
"#size-cells":
const: 1
compatible:
const: palmbus
reg:
maxItems: 1
ranges: true
patternProperties:
# All other properties should be child nodes with unit-address and 'reg'
"@[0-9a-f]+$":
type: object
properties:
reg:
maxItems: 1
required:
- reg
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
palmbus@1e000000 {
compatible = "palmbus";
reg = <0x1e000000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e000000 0x0fffff>;
gpio@600 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "mediatek,mt7621-gpio";
gpio-controller;
gpio-ranges = <&pinctrl 0 0 95>;
interrupt-controller;
reg = <0x600 0x100>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
};
};
...
Documentation/devicetree/bindings/bus/ti-sysc.txt deleted 100644 → 0
View file @ 624ad333
Texas Instruments sysc interconnect target module wrapper binding
Texas Instruments SoCs can have a generic interconnect target module
hardware for devices connected to various interconnects such as L3
interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc
is mostly used for interaction between module and PRCM. It participates
in the OCP Disconnect Protocol but other than that is mostly independent
of the interconnect.
Each interconnect target module can have one or more devices connected to
it. There is a set of control registers for managing interconnect target
module clocks, idle modes and interconnect level resets for the module.
These control registers are sprinkled into the unused register address
space of the first child device IP block managed by the interconnect
target module and typically are named REVISION, SYSCONFIG and SYSSTATUS.
Required standard properties:
- compatible shall be one of the following generic types:
"ti,sysc"
"ti,sysc-omap2"
"ti,sysc-omap4"
"ti,sysc-omap4-simple"
or one of the following derivative types for hardware
needing special workarounds:
"ti,sysc-omap2-timer"
"ti,sysc-omap4-timer"
"ti,sysc-omap3430-sr"
"ti,sysc-omap3630-sr"
"ti,sysc-omap4-sr"
"ti,sysc-omap3-sham"
"ti,sysc-omap-aes"
"ti,sysc-mcasp"
"ti,sysc-dra7-mcasp"
"ti,sysc-usb-host-fs"
"ti,sysc-dra7-mcan"
"ti,sysc-pruss"
- reg shall have register areas implemented for the interconnect
target module in question such as revision, sysc and syss
- reg-names shall contain the register names implemented for the
interconnect target module in question such as
"rev, "sysc", and "syss"
- ranges shall contain the interconnect target module IO range
available for one or more child device IP blocks managed
by the interconnect target module, the ranges may include
multiple ranges such as device L4 range for control and
parent L3 range for DMA access
Optional properties:
- ti,sysc-mask shall contain mask of supported register bits for the
SYSCONFIG register as documented in the Technical Reference
Manual (TRM) for the interconnect target module
- ti,sysc-midle list of master idle modes supported by the interconnect
target module as documented in the TRM for SYSCONFIG
register MIDLEMODE bits
- ti,sysc-sidle list of slave idle modes supported by the interconnect
target module as documented in the TRM for SYSCONFIG
register SIDLEMODE bits
- ti,sysc-delay-us delay needed after OCP softreset before accssing
SYSCONFIG register again
- ti,syss-mask optional mask of reset done status bits as described in the
TRM for SYSSTATUS registers, typically 1 with some devices
having separate reset done bits for children like OHCI and
EHCI
- clocks clock specifier for each name in the clock-names as
specified in the binding documentation for ti-clkctrl,
typically available for all interconnect targets on TI SoCs
based on omap4 except if it's read-only register in hwauto
mode as for example omap4 L4_CFG_CLKCTRL
- clock-names should contain at least "fck", and optionally also "ick"
depending on the SoC and the interconnect target module,
some interconnect target modules also need additional
optional clocks that can be specified as listed in TRM
for the related CLKCTRL register bits 8 to 15 such as
"dbclk" or "clk32k" depending on their role
- ti,hwmods optional TI interconnect module name to use legacy
hwmod platform data
- ti,no-reset-on-init interconnect target module should not be reset at init
- ti,no-idle-on-init interconnect target module should not be idled at init
- ti,no-idle interconnect target module should not be idled
Example: Single instance of MUSB controller on omap4 using interconnect ranges
using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
compatible = "ti,sysc-omap2";
ti,hwmods = "usb_otg_hs";
reg = <0x2b400 0x4>,
<0x2b404 0x4>,
<0x2b408 0x4>;
reg-names = "rev", "sysc", "syss";
clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
clock-names = "fck";
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2b000 0x1000>;
usb_otg_hs: otg@0 {
compatible = "ti,omap4-musb";
reg = <0x0 0x7ff>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb2_phy>;
...
};
};
Note that other SoCs, such as am335x can have multiple child devices. On am335x
there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA
instance as children of a single interconnect target module.
Documentation/devicetree/bindings/bus/ti-sysc.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/ti-sysc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments interconnect target module binding
maintainers:
- Tony Lindgren <tony@atomide.com>
description:
Texas Instruments SoCs can have a generic interconnect target module
for devices connected to various interconnects such as L3 interconnect
using Arteris NoC, and L4 interconnect using Sonics s3220. This module
is mostly used for interaction between module and Power, Reset and Clock
Manager PRCM. It participates in the OCP Disconnect Protocol, but other
than that it is mostly independent of the interconnect.
Each interconnect target module can have one or more devices connected to
it. There is a set of control registers for managing the interconnect target
module clocks, idle modes and interconnect level resets.
The interconnect target module control registers are sprinkled into the
unused register address space of the first child device IP block managed by
the interconnect target module. Typically the register names are REVISION,
SYSCONFIG and SYSSTATUS.
properties:
$nodename:
pattern: "^target-module(@[0-9a-f]+)?$"
compatible:
oneOf:
- items:
- enum:
- ti,sysc-omap2
- ti,sysc-omap2
- ti,sysc-omap4
- ti,sysc-omap4-simple
- ti,sysc-omap2-timer
- ti,sysc-omap4-timer
- ti,sysc-omap3430-sr
- ti,sysc-omap3630-sr
- ti,sysc-omap4-sr
- ti,sysc-omap3-sham
- ti,sysc-omap-aes
- ti,sysc-mcasp
- ti,sysc-dra7-mcasp
- ti,sysc-usb-host-fs
- ti,sysc-dra7-mcan
- ti,sysc-pruss
- const: ti,sysc
- items:
- const: ti,sysc
reg:
description:
Interconnect target module control registers consisting of
REVISION, SYSCONFIG and SYSSTATUS registers as defined in the
Technical Reference Manual for the SoC.
minItems: 1
maxItems: 3
reg-names:
description:
Interconnect target module control register names consisting
of "rev", "sysc" and "syss".
oneOf:
- minItems: 1
items:
- const: rev
- const: sysc
- const: syss
- items:
- const: rev
- const: syss
- enum: [ sysc, syss ]
power-domains:
description: Target module power domain if available.
maxItems: 1
clocks:
description:
Target module clocks consisting of one functional clock, one
interface clock, and up to 8 module specific optional clocks.
Some modules may have only the functional clock, and some have
no configurable clocks.
minItems: 1
maxItems: 4
clock-names:
description:
Target module clock names like "fck", "ick", "optck1", "optck2"
if the clocks are configurable.
oneOf:
- enum: [ ick, fck, sys_clk ]
- items:
- const: fck
- enum: [ ick. dbclk, osc, sys_clk, dss_clk, ahclkx ]
- items:
- const: fck
- const: phy-clk
- const: phy-clk-div
- items:
- const: fck
- const: hdmi_clk
- const: sys_clk
- const: tv_clk
- items:
- const: fck
- const: ahclkx
- const: ahclkr
resets:
description:
Target module reset bit in the RSTCTRL register if wired for the module.
Note that the other reset bits should be mapped for the child device
driver to use.
maxItems: 1
reset-names:
description:
Target module reset names in the RSTCTRL register, typically named
"rstctrl" if only one reset bit is wired for the module.
items:
- const: rstctrl
'#address-cells':
enum: [ 1, 2 ]
'#size-cells':
enum: [ 1, 2 ]
ranges: true
dma-ranges: true
ti,sysc-mask:
description: Mask of supported register bits for the SYSCONFIG register
$ref: /schemas/types.yaml#/definitions/uint32
ti,sysc-midle:
description: List of hardware supported idle modes
$ref: /schemas/types.yaml#/definitions/uint32-array
ti,sysc-sidle:
description: List of hardware supported idle modes
$ref: /schemas/types.yaml#/definitions/uint32-array
ti,syss-mask:
description: Mask of supported register bits for the SYSSTATUS register
$ref: /schemas/types.yaml#/definitions/uint32
ti,sysc-delay-us:
description: Delay needed after OCP softreset before accessing SYCONFIG
default: 0
minimum: 0
maximum: 2
ti,no-reset-on-init:
description: Interconnect target module shall not be reset at init
type: boolean
ti,no-idle-on-init:
description: Interconnect target module shall not be idled at init
type: boolean
ti,no-idle:
description: Interconnect target module shall not be idled
type: boolean
ti,hwmods:
description: Interconnect module name to use with legacy hwmod data
$ref: /schemas/types.yaml#/definitions/string
deprecated: true
required:
- compatible
- '#address-cells'
- '#size-cells'
- ranges
additionalProperties:
type: object
examples:
- |
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/omap4.h>
target-module@2b000 {
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "usb_otg_hs";
reg = <0x2b400 0x4>,
<0x2b404 0x4>,
<0x2b408 0x4>;
reg-names = "rev", "sysc", "syss";
clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
clock-names = "fck";
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2b000 0x1000>;
};
Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
View file @ dcd68326
......@@ -174,7 +174,7 @@ Example:
compatible = "rockchip,rk3399-dmc";
devfreq-events = <&dfi>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_DDRCLK>;
clocks = <&cru SCLK_DDRC>;
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
center-supply = <&ppvar_centerlogic>;
......
Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt
View file @ dcd68326
......@@ -60,7 +60,7 @@ Example:
blue-and-red-wiring = "crossed";
port {
lcdc_0: endpoint@0 {
lcdc_0: endpoint {
remote-endpoint = <&hdmi_0>;
};
};
......@@ -75,7 +75,7 @@ Example:
pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
port {
hdmi_0: endpoint@0 {
hdmi_0: endpoint {
remote-endpoint = <&lcdc_0>;
};
};
......
Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
View file @ dcd68326
......@@ -160,8 +160,8 @@ examples:
<&xlnx_dpdma 2>,
<&xlnx_dpdma 3>;
phys = <&psgtr 1 PHY_TYPE_DP 0 3 27000000>,
<&psgtr 0 PHY_TYPE_DP 1 3 27000000>;
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
phy-names = "dp-phy0", "dp-phy1";
};
......
Documentation/devicetree/bindings/display/xylon,logicvc-display.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Bootlin
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Xylon LogiCVC display controller
maintainers:
- Paul Kocialkowski <paul.kocialkowski@bootlin.com>
description: |
The Xylon LogiCVC is a display controller that supports multiple layers.
It is usually implemented as programmable logic and was optimized for use
with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
Because the controller is intended for use in a FPGA, most of the
configuration of the controller takes place at logic configuration bitstream
synthesis time. As a result, many of the device-tree bindings are meant to
reflect the synthesis configuration and must not be configured differently.
Matching synthesis parameters are provided when applicable.
Layers are declared in the "layers" sub-node and have dedicated configuration.
In version 3 of the controller, each layer has fixed memory offset and address
starting from the video memory base address for its framebuffer. In version 4,
framebuffers are configured with a direct memory address instead.
properties:
compatible:
enum:
- xylon,logicvc-3.02.a-display
- xylon,logicvc-4.01.a-display
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
items:
# vclk is required and must be provided as first item.
- const: vclk
# Other clocks are optional and can be provided in any order.
- enum:
- vclk2
- lvdsclk
- lvdsclkn
- enum:
- vclk2
- lvdsclk
- lvdsclkn
- enum:
- vclk2
- lvdsclk
- lvdsclkn
interrupts:
maxItems: 1
memory-region:
maxItems: 1
xylon,display-interface:
enum:
# Parallel RGB interface (C_DISPLAY_INTERFACE == 0)
- parallel-rgb
# ITU-T BR656 interface (C_DISPLAY_INTERFACE == 1)
- bt656
# 4-bit LVDS interface (C_DISPLAY_INTERFACE == 2)
- lvds-4bits
# 3-bit LVDS interface (C_DISPLAY_INTERFACE == 4)
- lvds-3bits
# DVI interface (C_DISPLAY_INTERFACE == 5)
- dvi
description: Display output interface (C_DISPLAY_INTERFACE).
xylon,display-colorspace:
enum:
# RGB colorspace (C_DISPLAY_COLOR_SPACE == 0)
- rgb
# YUV 4:2:2 colorspace (C_DISPLAY_COLOR_SPACE == 1)
- yuv422
# YUV 4:4:4 colorspace (C_DISPLAY_COLOR_SPACE == 2)
- yuv444
description: Display output colorspace (C_DISPLAY_COLOR_SPACE).
xylon,display-depth:
$ref: "/schemas/types.yaml#/definitions/uint32"
description: Display output depth (C_PIXEL_DATA_WIDTH).
xylon,row-stride:
$ref: "/schemas/types.yaml#/definitions/uint32"
description: Fixed number of pixels in a framebuffer row (C_ROW_STRIDE).
xylon,dithering:
$ref: "/schemas/types.yaml#/definitions/flag"
description: Dithering module is enabled (C_XCOLOR)
xylon,background-layer:
$ref: "/schemas/types.yaml#/definitions/flag"
description: |
The last layer is used to display a black background (C_USE_BACKGROUND).
The layer must still be registered.
xylon,layers-configurable:
$ref: "/schemas/types.yaml#/definitions/flag"
description: |
Configuration of layers' size, position and offset is enabled
(C_USE_SIZE_POSITION).
layers:
type: object
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^layer@[0-9]+$":
type: object
properties:
reg:
maxItems: 1
xylon,layer-depth:
$ref: "/schemas/types.yaml#/definitions/uint32"
description: Layer depth (C_LAYER_X_DATA_WIDTH).
xylon,layer-colorspace:
enum:
# RGB colorspace (C_LAYER_X_TYPE == 0)
- rgb
# YUV packed colorspace (C_LAYER_X_TYPE == 0)
- yuv
description: Layer colorspace (C_LAYER_X_TYPE).
xylon,layer-alpha-mode:
enum:
# Alpha is configured layer-wide (C_LAYER_X_ALPHA_MODE == 0)
- layer
# Alpha is configured per-pixel (C_LAYER_X_ALPHA_MODE == 1)
- pixel
description: Alpha mode for the layer (C_LAYER_X_ALPHA_MODE).
xylon,layer-base-offset:
$ref: "/schemas/types.yaml#/definitions/uint32"
description: |
Offset in number of lines (C_LAYER_X_OFFSET) starting from the
video RAM base (C_VMEM_BASEADDR), only for version 3.
xylon,layer-buffer-offset:
$ref: "/schemas/types.yaml#/definitions/uint32"
description: |
Offset in number of lines (C_BUFFER_*_OFFSET) starting from the
layer base offset for the second buffer used in double-buffering.
xylon,layer-primary:
$ref: "/schemas/types.yaml#/definitions/flag"
description: |
Layer should be registered as a primary plane (exactly one is
required).
additionalProperties: false
required:
- reg
- xylon,layer-depth
- xylon,layer-colorspace
- xylon,layer-alpha-mode
required:
- "#address-cells"
- "#size-cells"
- layer@0
additionalProperties: false
description: |
The description of the display controller layers, containing layer
sub-nodes that each describe a registered layer.
port:
$ref: /schemas/graph.yaml#/properties/port
description: |
Video output port, typically connected to a panel or bridge.
additionalProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- xylon,display-interface
- xylon,display-colorspace
- xylon,display-depth
- xylon,row-stride
- layers
- port
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
logicvc: logicvc@43c00000 {
compatible = "xylon,logicvc-3.02.a", "syscon", "simple-mfd";
reg = <0x43c00000 0x6000>;
#address-cells = <1>;
#size-cells = <1>;
logicvc_display: display@0 {
compatible = "xylon,logicvc-3.02.a-display";
reg = <0x0 0x6000>;
memory-region = <&logicvc_cma>;
clocks = <&logicvc_vclk 0>, <&logicvc_lvdsclk 0>;
clock-names = "vclk", "lvdsclk";
interrupt-parent = <&intc>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
xylon,display-interface = "lvds-4bits";
xylon,display-colorspace = "rgb";
xylon,display-depth = <16>;
xylon,row-stride = <1024>;
xylon,layers-configurable;
layers {
#address-cells = <1>;
#size-cells = <0>;
layer@0 {
reg = <0>;
xylon,layer-depth = <16>;
xylon,layer-colorspace = "rgb";
xylon,layer-alpha-mode = "layer";
xylon,layer-base-offset = <0>;
xylon,layer-buffer-offset = <480>;
xylon,layer-primary;
};
layer@1 {
reg = <1>;
xylon,layer-depth = <16>;
xylon,layer-colorspace = "rgb";
xylon,layer-alpha-mode = "layer";
xylon,layer-base-offset = <2400>;
xylon,layer-buffer-offset = <480>;
};
layer@2 {
reg = <2>;
xylon,layer-depth = <16>;
xylon,layer-colorspace = "rgb";
xylon,layer-alpha-mode = "layer";
xylon,layer-base-offset = <960>;
xylon,layer-buffer-offset = <480>;
};
layer@3 {
reg = <3>;
xylon,layer-depth = <16>;
xylon,layer-colorspace = "rgb";
xylon,layer-alpha-mode = "layer";
xylon,layer-base-offset = <480>;
xylon,layer-buffer-offset = <480>;
};
layer@4 {
reg = <4>;
xylon,layer-depth = <16>;
xylon,layer-colorspace = "rgb";
xylon,layer-alpha-mode = "layer";
xylon,layer-base-offset = <8192>;
xylon,layer-buffer-offset = <480>;
};
};
port {
#address-cells = <1>;
#size-cells = <0>;
logicvc_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
};
};
Documentation/devicetree/bindings/example-schema.yaml
View file @ dcd68326
......@@ -119,7 +119,7 @@ properties:
# valid for this binding.
clock-frequency:
# The type is set in the core schema. Per device schema only need to set
# The type is set in the core schema. Per-device schema only need to set
# constraints on the possible values.
minimum: 100
maximum: 400000
......@@ -133,24 +133,24 @@ properties:
# *-supply is always a single phandle, so nothing more to define.
foo-supply: true
# Vendor specific properties
# Vendor-specific properties
#
# Vendor specific properties have slightly different schema requirements than
# Vendor-specific properties have slightly different schema requirements than
# common properties. They must have at least a type definition and
# 'description'.
vendor,int-property:
description: Vendor specific properties must have a description
description: Vendor-specific properties must have a description
$ref: /schemas/types.yaml#/definitions/uint32
enum: [2, 4, 6, 8, 10]
vendor,bool-property:
description: Vendor specific properties must have a description. Boolean
description: Vendor-specific properties must have a description. Boolean
properties are one case where the json-schema 'type' keyword can be used
directly.
type: boolean
vendor,string-array-property:
description: Vendor specific properties should reference a type in the
description: Vendor-specific properties should reference a type in the
core schema.
$ref: /schemas/types.yaml#/definitions/string-array
items:
......@@ -158,7 +158,7 @@ properties:
- enum: [baz, boo]
vendor,property-in-standard-units-microvolt:
description: Vendor specific properties having a standard unit suffix
description: Vendor-specific properties having a standard unit suffix
don't need a type.
enum: [ 100, 200, 300 ]
......
Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gnss/u-blox,neo-6m.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: U-blox GNSS Receiver Device Tree Bindings
maintainers:
- Johan Hovold <johan@kernel.org>
description: >
The U-blox GNSS receivers can use UART, DDC (I2C), SPI and USB interfaces.
properties:
compatible:
enum:
- u-blox,neo-6m
- u-blox,neo-8
- u-blox,neo-m8
reg:
description: >
The DDC Slave Address, SPI chip select address, the number of the USB hub
port or the USB host-controller port to which this device is attached,
depending on the bus used. Required for the DDC, SPI or USB busses.
vcc-supply:
description: >
Main voltage regulator
timepulse-gpios:
maxItems: 1
description: >
Time pulse GPIO
u-blox,extint-gpios:
maxItems: 1
description: >
GPIO connected to the "external interrupt" input pin
v-bckp-supply:
description: >
Backup voltage regulator
current-speed: true
required:
- compatible
- vcc-supply
additionalProperties: false
examples:
- |
serial {
gnss {
compatible = "u-blox,neo-8";
v-bckp-supply = <&gnss_v_bckp_reg>;
vcc-supply = <&gnss_vcc_reg>;
};
};
Documentation/devicetree/bindings/gnss/u-blox.txt deleted 100644 → 0
View file @ 624ad333
u-blox GNSS Receiver DT binding
The u-blox GNSS receivers can use UART, DDC (I2C), SPI and USB interfaces.
Please see Documentation/devicetree/bindings/gnss/gnss.txt for generic
properties.
Required properties:
- compatible : Must be one of
"u-blox,neo-6m"
"u-blox,neo-8"
"u-blox,neo-m8"
- vcc-supply : Main voltage regulator
Required properties (DDC):
- reg : DDC (I2C) slave address
Required properties (SPI):
- reg : SPI chip select address
Required properties (USB):
- reg : Number of the USB hub port or the USB host-controller port
to which this device is attached
Optional properties:
- timepulse-gpios : Time pulse GPIO
- u-blox,extint-gpios : GPIO connected to the "external interrupt" input pin
- v-bckp-supply : Backup voltage regulator
Example:
serial@1234 {
compatible = "ns16550a";
gnss {
compatible = "u-blox,neo-8";
v-bckp-supply = <&gnss_v_bckp_reg>;
vcc-supply = <&gnss_vcc_reg>;
};
};
Documentation/devicetree/bindings/input/cap11xx.txt deleted 100644 → 0
View file @ 624ad333
Device tree bindings for Microchip CAP11xx based capacitive touch sensors
The node for this device must be a child of a I2C controller node, as the
device communication via I2C only.
Required properties:
compatible: Must contain one of:
"microchip,cap1106"
"microchip,cap1126"
"microchip,cap1188"
reg: The I2C slave address of the device.
interrupts: Property describing the interrupt line the
device's ALERT#/CM_IRQ# pin is connected to.
The device only has one interrupt source.
Optional properties:
autorepeat: Enables the Linux input system's autorepeat
feature on the input device.
microchip,sensor-gain: Defines the gain of the sensor circuitry. This
effectively controls the sensitivity, as a
smaller delta capacitance is required to
generate the same delta count values.
Valid values are 1, 2, 4, and 8.
By default, a gain of 1 is set.
microchip,irq-active-high: By default the interrupt pin is active low
open drain. This property allows using the active
high push-pull output.
linux,keycodes: Specifies an array of numeric keycode values to
be used for the channels. If this property is
omitted, KEY_A, KEY_B, etc are used as
defaults. The array must have exactly six
entries.
Example:
i2c_controller {
cap1106@28 {
compatible = "microchip,cap1106";
interrupt-parent = <&gpio1>;
interrupts = <0 0>;
reg = <0x28>;
autorepeat;
microchip,sensor-gain = <2>;
linux,keycodes = <103>, /* KEY_UP */
<106>, /* KEY_RIGHT */
<108>, /* KEY_DOWN */
<105>, /* KEY_LEFT */
<109>, /* KEY_PAGEDOWN */
<104>; /* KEY_PAGEUP */
#address-cells = <1>;
#size-cells = <0>;
usr@0 {
label = "cap11xx:green:usr0";
reg = <0>;
};
usr@1 {
label = "cap11xx:green:usr1";
reg = <1>;
};
alive@2 {
label = "cap11xx:green:alive";
reg = <2>;
linux,default_trigger = "heartbeat";
};
};
}
Documentation/devicetree/bindings/input/elan,ekth3000.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/elan,ekth3000.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Elantech I2C Touchpad
maintainers:
- Dmitry Torokhov <dmitry.torokhov@gmail.com>
allOf:
- $ref: touchscreen/touchscreen.yaml#
properties:
compatible:
const: elan,ekth3000
reg:
maxItems: 1
interrupts:
maxItems: 1
wakeup-source:
type: boolean
description: touchpad can be used as a wakeup source
vcc-supply:
description: a phandle for the regulator supplying 3.3V power
elan,trackpoint:
type: boolean
description: touchpad can support a trackpoint
elan,clickpad:
type: boolean
description: touchpad is a clickpad (the entire surface is a button)
elan,middle-button:
type: boolean
description: touchpad has a physical middle button
elan,x_traces:
$ref: /schemas/types.yaml#/definitions/uint32
description: number of antennas on the x axis
elan,y_traces:
$ref: /schemas/types.yaml#/definitions/uint32
description: number of antennas on the y axis
touchscreen-size-x: true
touchscreen-size-y: true
touchscreen-x-mm: true
touchscreen-y-mm: true
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchpad@15 {
compatible = "elan,ekth3000";
reg = <0x15>;
interrupt-parent = <&gpio4>;
interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
};
Documentation/devicetree/bindings/input/elan_i2c.txt deleted 100644 → 0
View file @ 624ad333
Elantech I2C Touchpad
Required properties:
- compatible: must be "elan,ekth3000".
- reg: I2C address of the chip.
- interrupts: interrupt to which the chip is connected (see interrupt
binding[0]).
Optional properties:
- wakeup-source: touchpad can be used as a wakeup source.
- pinctrl-names: should be "default" (see pinctrl binding [1]).
- pinctrl-0: a phandle pointing to the pin settings for the device (see
pinctrl binding [1]).
- vcc-supply: a phandle for the regulator supplying 3.3V power.
- elan,trackpoint: touchpad can support a trackpoint (boolean)
- elan,clickpad: touchpad is a clickpad (the entire surface is a button)
- elan,middle-button: touchpad has a physical middle button
- elan,x_traces: number of antennas on the x axis
- elan,y_traces: number of antennas on the y axis
- some generic touchscreen properties [2]:
* touchscreen-size-x
* touchscreen-size-y
* touchscreen-x-mm
* touchscreen-y-mm
[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
[2]: Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
Example:
&i2c1 {
/* ... */
touchpad@15 {
compatible = "elan,ekth3000";
reg = <0x15>;
interrupt-parent = <&gpio4>;
interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
/* ... */
};
Documentation/devicetree/bindings/input/microchip,cap11xx.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/input/microchip,cap11xx.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Device tree bindings for Microchip CAP11xx based capacitive touch sensors
description: |
The Microchip CAP1xxx Family of RightTouchTM multiple-channel capacitive
touch controllers and LED drivers. The device communication via I2C only.
maintainers:
- Rob Herring <robh@kernel.org>
properties:
compatible:
enum:
- microchip,cap1106
- microchip,cap1126
- microchip,cap1188
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
interrupts:
maxItems: 1
description: |
Property describing the interrupt line the
device's ALERT#/CM_IRQ# pin is connected to.
The device only has one interrupt source.
autorepeat:
description: |
Enables the Linux input system's autorepeat feature on the input device.
linux,keycodes:
minItems: 6
maxItems: 6
description: |
Specifies an array of numeric keycode values to
be used for the channels. If this property is
omitted, KEY_A, KEY_B, etc are used as defaults.
The array must have exactly six entries.
microchip,sensor-gain:
$ref: /schemas/types.yaml#/definitions/uint32
default: 1
enum: [1, 2, 4, 8]
description: |
Defines the gain of the sensor circuitry. This
effectively controls the sensitivity, as a
smaller delta capacitance is required to
generate the same delta count values.
microchip,irq-active-high:
type: boolean
description: |
By default the interrupt pin is active low
open drain. This property allows using the active
high push-pull output.
patternProperties:
"^led@[0-7]$":
type: object
description: CAP11xx LEDs
$ref: /schemas/leds/common.yaml#
properties:
reg:
enum: [0, 1, 2, 3, 4, 5, 6, 7]
label: true
linux,default-trigger: true
default-state: true
required:
- reg
additionalProperties: false
allOf:
- $ref: input.yaml
- if:
properties:
compatible:
contains:
enum:
- microchip,cap1106
then:
patternProperties:
"^led@[0-7]$": false
required:
- compatible
- interrupts
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
cap1188@28 {
compatible = "microchip,cap1188";
interrupt-parent = <&gpio1>;
interrupts = <0 0>;
reg = <0x28>;
autorepeat;
microchip,sensor-gain = <2>;
linux,keycodes = <103>, /* KEY_UP */
<106>, /* KEY_RIGHT */
<108>, /* KEY_DOWN */
<105>, /* KEY_LEFT */
<109>, /* KEY_PAGEDOWN */
<104>; /* KEY_PAGEUP */
#address-cells = <1>;
#size-cells = <0>;
led@0 {
label = "cap11xx:green:usr0";
reg = <0>;
};
led@1 {
label = "cap11xx:green:usr1";
reg = <1>;
};
led@2 {
label = "cap11xx:green:alive";
reg = <2>;
linux,default-trigger = "heartbeat";
};
};
};
Documentation/devicetree/bindings/input/touchscreen/silead,gsl1680.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/silead,gsl1680.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Silead GSL1680 Touchscreen Controller Device Tree Bindings
maintainers:
- Dmitry Torokhov <dmitry.torokhov@gmail.com>
allOf:
- $ref: touchscreen.yaml#
properties:
compatible:
enum:
- silead,gsl1680
- silead,gsl1688
- silead,gsl3670
- silead,gsl3675
- silead,gsl3692
reg:
maxItems: 1
interrupts:
maxItems: 1
power-gpios:
maxItems: 1
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description: >
File basename for board specific firmware
silead,max-fingers:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 5
description: >
Maximum number of fingers the touchscreen can detect
silead,home-button:
type: boolean
description: >
Does the device have a capacitive home-button build into the
touchscreen?
avdd-supply:
description: >
Regulator phandle for controller AVDD
vddio-supply:
description: >
Regulator phandle for controller VDDIO
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- power-gpios
- touchscreen-size-x
- touchscreen-size-y
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@40 {
compatible = "silead,gsl1680";
reg = <0x40>;
interrupt-parent = <&pio>;
interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>;
power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
touchscreen-inverted-x;
touchscreen-swapped-x-y;
silead,max-fingers = <5>;
};
};
...
Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt deleted 100644 → 0
View file @ 624ad333
* GSL 1680 touchscreen controller
Required properties:
- compatible : Must be one of the following, depending on the model:
"silead,gsl1680"
"silead,gsl1688"
"silead,gsl3670"
"silead,gsl3675"
"silead,gsl3692"
- reg : I2C slave address of the chip (0x40)
- interrupts : interrupt specification for the gsl1680 interrupt
- power-gpios : Specification for the pin connected to the gsl1680's
shutdown input. This needs to be driven high to take the
gsl1680 out of its low power state
- touchscreen-size-x : See touchscreen.txt
- touchscreen-size-y : See touchscreen.txt
Optional properties:
- firmware-name : File basename (string) for board specific firmware
- touchscreen-inverted-x : See touchscreen.txt
- touchscreen-inverted-y : See touchscreen.txt
- touchscreen-swapped-x-y : See touchscreen.txt
- silead,max-fingers : maximum number of fingers the touchscreen can detect
- silead,home-button : Boolean, set to true on devices which have a
capacitive home-button build into the touchscreen
- vddio-supply : regulator phandle for controller VDDIO
- avdd-supply : regulator phandle for controller AVDD
Example:
i2c@00000000 {
gsl1680: touchscreen@40 {
compatible = "silead,gsl1680";
reg = <0x40>;
interrupt-parent = <&pio>;
interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>;
power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
touchscreen-inverted-x;
touchscreen-swapped-x-y;
silead,max-fingers = <5>;
};
};
Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MSI controller
maintainers:
- Marc Zyngier <maz@kernel.org>
description: |
An MSI controller signals interrupts to a CPU when a write is made
to an MMIO address by some master. An MSI controller may feature a
number of doorbells.
properties:
"#msi-cells":
description: |
The number of cells in an msi-specifier, required if not zero.
Typically this will encode information related to sideband data,
and will not encode doorbells or payloads as these can be
configured dynamically.
The meaning of the msi-specifier is defined by the device tree
binding of the specific MSI controller.
enum: [0, 1]
msi-controller:
description:
Identifies the node as an MSI controller.
$ref: /schemas/types.yaml#/definitions/flag
msi-ranges:
description:
A list of <phandle intspec span> tuples, where "phandle" is the
parent interrupt controller, "intspec" is the starting/base
interrupt specifier and "span" is the size of the
range. Multiple ranges can be provided.
$ref: /schemas/types.yaml#/definitions/phandle-array
dependencies:
"#msi-cells": [ msi-controller ]
additionalProperties: true
Documentation/devicetree/bindings/leds/register-bit-led.txt deleted 100644 → 0
View file @ 624ad333
Device Tree Bindings for Register Bit LEDs
Register bit leds are used with syscon multifunctional devices
where single bits in a certain register can turn on/off a
single LED. The register bit LEDs appear as children to the
syscon device, with the proper compatible string. For the
syscon bindings see:
Documentation/devicetree/bindings/mfd/syscon.yaml
Each LED is represented as a sub-node of the syscon device. Each
node's name represents the name of the corresponding LED.
LED sub-node properties:
Required properties:
- compatible : must be "register-bit-led"
- offset : register offset to the register controlling this LED
- mask : bit mask for the bit controlling this LED in the register
typically 0x01, 0x02, 0x04 ...
Optional properties:
- label : (optional)
see Documentation/devicetree/bindings/leds/common.txt
- linux,default-trigger : (optional)
see Documentation/devicetree/bindings/leds/common.txt
- default-state: (optional) The initial state of the LED
see Documentation/devicetree/bindings/leds/common.txt
Example:
syscon: syscon@10000000 {
compatible = "arm,realview-pb1176-syscon", "syscon";
reg = <0x10000000 0x1000>;
led@8.0 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@8.1 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led@8.2 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led@8.3 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
led@8.4 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
led@8.5 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
led@8.6 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
led@8.7 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
};
Documentation/devicetree/bindings/leds/register-bit-led.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/register-bit-led.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Device Tree Bindings for Register Bit LEDs
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |+
Register bit leds are used with syscon multifunctional devices where single
bits in a certain register can turn on/off a single LED. The register bit LEDs
appear as children to the syscon device, with the proper compatible string.
For the syscon bindings see:
Documentation/devicetree/bindings/mfd/syscon.yaml
allOf:
- $ref: /schemas/leds/common.yaml#
properties:
$nodename:
description:
The unit-address is in the form of @<reg addr>,<bit offset>
pattern: '^led@[0-9a-f]+,[0-9a-f]{1,2}$'
compatible:
const: register-bit-led
reg:
description:
The register address and size
maxItems: 1
mask:
description:
bit mask for the bit controlling this LED in the register
$ref: /schemas/types.yaml#/definitions/uint32
enum:
[ 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x100, 0x200, 0x400, 0x800,
0x1000, 0x2000, 0x4000, 0x8000, 0x10000, 0x20000, 0x40000, 0x80000,
0x100000, 0x200000, 0x400000, 0x800000, 0x1000000, 0x2000000, 0x4000000,
0x8000000, 0x10000000, 0x20000000, 0x40000000, 0x80000000 ]
offset:
description:
register offset to the register controlling this LED
$ref: /schemas/types.yaml#/definitions/uint32
deprecated: true
required:
- compatible
- mask
- reg
unevaluatedProperties: false
examples:
- |
syscon@10000000 {
compatible = "arm,realview-pb1176-syscon", "syscon";
reg = <0x10000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10000000 0x1000>;
led@8,0 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@8,1 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
default-state = "off";
};
led@8,2 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
default-state = "off";
};
};
...
Documentation/devicetree/bindings/mailbox/mtk-gce.txt
View file @ dcd68326
......@@ -40,8 +40,8 @@ Optional properties for a client mutex node:
defined in 'dt-bindings/gce/<chip>-gce.h'.
Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h',
'dt-binding/gce/mt8183-gce.h', 'dt-binding/gce/mt8192-gce.h',
'dt-binding/gce/mt8195-gce.h' or 'dt-bindings/gce/mt6779-gce.h'.
'dt-bindings/gce/mt8183-gce.h', 'dt-bindings/gce/mt8192-gce.h',
'dt-bindings/gce/mt8195-gce.h' or 'dt-bindings/gce/mt6779-gce.h'.
Such as sub-system ids, thread priority, event ids.
Example:
......
Documentation/devicetree/bindings/media/i2c/ov5640.txt deleted 100644 → 0
View file @ 624ad333
* Omnivision OV5640 MIPI CSI-2 / parallel sensor
Required Properties:
- compatible: should be "ovti,ov5640"
- clocks: reference to the xclk input clock.
- clock-names: should be "xclk".
- DOVDD-supply: Digital I/O voltage supply, 1.8 volts
- AVDD-supply: Analog voltage supply, 2.8 volts
- DVDD-supply: Digital core voltage supply, 1.5 volts
Optional Properties:
- reset-gpios: reference to the GPIO connected to the reset pin, if any.
This is an active low signal to the OV5640.
- powerdown-gpios: reference to the GPIO connected to the powerdown pin,
if any. This is an active high signal to the OV5640.
- rotation: as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt,
valid values are 0 (sensor mounted upright) and 180 (sensor
mounted upside down).
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
OV5640 can be connected to a MIPI CSI-2 bus or a parallel bus endpoint.
Endpoint node required properties for CSI-2 connection are:
- remote-endpoint: a phandle to the bus receiver's endpoint node.
- clock-lanes: should be set to <0> (clock lane on hardware lane 0)
- data-lanes: should be set to <1> or <1 2> (one or two CSI-2 lanes supported)
Endpoint node required properties for parallel connection are:
- remote-endpoint: a phandle to the bus receiver's endpoint node.
- bus-width: shall be set to <8> for 8 bits parallel bus
or <10> for 10 bits parallel bus
- data-shift: shall be set to <2> for 8 bits parallel bus
(lines 9:2 are used) or <0> for 10 bits parallel bus
- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock
signal.
Examples:
&i2c1 {
ov5640: camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x3c>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
AVDD-supply = <&vgen3_reg>; /* 2.8v */
DVDD-supply = <&vgen2_reg>; /* 1.5v */
powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
rotation = <180>;
port {
/* MIPI CSI-2 bus endpoint */
ov5640_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_from_ov5640>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&i2c1 {
ov5640: camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x3c>;
clocks = <&clk_ext_camera>;
clock-names = "xclk";
port {
/* Parallel bus endpoint */
ov5640_to_parallel: endpoint {
remote-endpoint = <&parallel_from_ov5640>;
bus-width = <8>;
data-shift = <2>; /* lines 9:2 are used */
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <1>;
};
};
};
};
Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/ovti,ov5640.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: OmniVision OV5640 Image Sensor Device Tree Bindings
maintainers:
- Steve Longerbeam <slongerbeam@gmail.com>
allOf:
- $ref: /schemas/media/video-interface-devices.yaml#
properties:
compatible:
const: ovti,ov5640
reg:
maxItems: 1
clocks:
description: XCLK Input Clock
clock-names:
const: xclk
AVDD-supply:
description: Analog voltage supply, 2.8 volts
DVDD-supply:
description: Digital core voltage supply, 1.5 volts
DOVDD-supply:
description: Digital I/O voltage supply, 1.8 volts
powerdown-gpios:
maxItems: 1
description: >
Reference to the GPIO connected to the powerdown pin, if any.
reset-gpios:
maxItems: 1
description: >
Reference to the GPIO connected to the reset pin, if any.
rotation:
enum:
- 0
- 180
port:
description: Digital Output Port
$ref: /schemas/graph.yaml#/$defs/port-base
additionalProperties: false
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
clock-lanes:
const: 0
data-lanes:
minItems: 1
maxItems: 2
items:
enum: [1, 2]
bus-width:
enum: [8, 10]
data-shift:
enum: [0, 2]
required:
- compatible
- reg
- clocks
- clock-names
- AVDD-supply
- DVDD-supply
- DOVDD-supply
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x3c>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
AVDD-supply = <&vgen3_reg>; /* 2.8v */
DVDD-supply = <&vgen2_reg>; /* 1.5v */
powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
rotation = <180>;
port {
/* MIPI CSI-2 bus endpoint */
ov5640_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_from_ov5640>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x3c>;
clocks = <&clk_ext_camera>;
clock-names = "xclk";
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
AVDD-supply = <&vgen3_reg>; /* 2.8v */
DVDD-supply = <&vgen2_reg>; /* 1.5v */
port {
/* Parallel bus endpoint */
ov5640_to_parallel: endpoint {
remote-endpoint = <&parallel_from_ov5640>;
bus-width = <8>;
data-shift = <2>; /* lines 9:2 are used */
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <1>;
};
};
};
};
...
Documentation/devicetree/bindings/media/ti,cal.yaml
View file @ dcd68326
......@@ -154,7 +154,9 @@ examples:
camera-sensor@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
AVDD-supply = <&reg_2p8v>;
DOVDD-supply = <&reg_1p8v>;
DVDD-supply = <&reg_1p5v>;
clocks = <&clk_ov5640_fixed>;
clock-names = "xclk";
......
Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt deleted 100644 → 0
View file @ 624ad333
Freescale DDR memory controller
Properties:
- compatible : Should include "fsl,chip-memory-controller" where
chip is the processor (bsc9132, mpc8572 etc.), or
"fsl,qoriq-memory-controller".
- reg : Address and size of DDR controller registers
- interrupts : Error interrupt of DDR controller
- little-endian : Specifies little-endian access to registers
If omitted, big-endian will be used.
Example 1:
memory-controller@2000 {
compatible = "fsl,bsc9132-memory-controller";
reg = <0x2000 0x1000>;
interrupts = <16 2 1 8>;
};
Example 2:
ddr1: memory-controller@8000 {
compatible = "fsl,qoriq-memory-controller-v4.7",
"fsl,qoriq-memory-controller";
reg = <0x8000 0x1000>;
interrupts = <16 2 1 23>;
};
Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ddr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale DDR memory controller
maintainers:
- Borislav Petkov <bp@alien8.de>
- York Sun <york.sun@nxp.com>
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
oneOf:
- items:
- enum:
- fsl,qoriq-memory-controller-v4.4
- fsl,qoriq-memory-controller-v4.5
- fsl,qoriq-memory-controller-v4.7
- fsl,qoriq-memory-controller-v5.0
- const: fsl,qoriq-memory-controller
- enum:
- fsl,bsc9132-memory-controller
- fsl,8540-memory-controller
- fsl,8541-memory-controller
- fsl,8544-memory-controller
- fsl,8548-memory-controller
- fsl,8555-memory-controller
- fsl,8568-memory-controller
- fsl,mpc8536-memory-controller
- fsl,mpc8540-memory-controller
- fsl,mpc8541-memory-controller
- fsl,mpc8544-memory-controller
- fsl,mpc8548-memory-controller
- fsl,mpc8555-memory-controller
- fsl,mpc8560-memory-controller
- fsl,mpc8568-memory-controller
- fsl,mpc8569-memory-controller
- fsl,mpc8572-memory-controller
- fsl,mpc8349-memory-controller
- fsl,p1020-memory-controller
- fsl,p1021-memory-controller
- fsl,p2020-memory-controller
- fsl,qoriq-memory-controller
interrupts:
maxItems: 1
little-endian:
description:
Specifies little-endian access to registers. If omitted, big-endian will
be used.
type: boolean
reg:
maxItems: 1
required:
- compatible
- interrupts
- reg
additionalProperties: false
examples:
- |
memory-controller@2000 {
compatible = "fsl,bsc9132-memory-controller";
reg = <0x2000 0x1000>;
interrupts = <16 2 1 8>;
};
- |
memory-controller@8000 {
compatible = "fsl,qoriq-memory-controller-v4.7",
"fsl,qoriq-memory-controller";
reg = <0x8000 0x1000>;
interrupts = <16 2 1 23>;
};
Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/mediatek,mt7621-memc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MT7621 SDRAM controller
maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
properties:
compatible:
const: mediatek,mt7621-memc
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
memory-controller@5000 {
compatible = "mediatek,mt7621-memc";
reg = <0x5000 0x1000>;
};
Documentation/devicetree/bindings/mfd/aspeed-lpc.txt deleted 100644 → 0
View file @ 624ad333
======================================================================
Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
======================================================================
The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
primary use case of the Aspeed LPC controller is as a slave on the bus
(typically in a Baseboard Management Controller SoC), but under certain
conditions it can also take the role of bus master.
The LPC controller is represented as a multi-function device to account for the
mix of functionality, which includes, but is not limited to:
* An IPMI Block Transfer[2] Controller
* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
physical properties of some LPC pins, configuration of serial IRQs, and
APB-to-LPC bridging amonst other functions.
* An LPC Host Interface Controller: Manages functions exposed to the host such
as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
management and bus snoop configuration.
* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
hardware management protocols for handover between the host and baseboard
management controller.
Additionally the state of the LPC controller influences the pinmux
configuration, therefore the host portion of the controller is exposed as a
syscon as a means to arbitrate access.
[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
[3] https://en.wikipedia.org/wiki/Super_I/O
Required properties
===================
- compatible: One of:
"aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
"aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
"aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
- reg: contains the physical address and length values of the Aspeed
LPC memory region.
- #address-cells: <1>
- #size-cells: <1>
- ranges: Maps 0 to the physical address and length of the LPC memory
region
Example:
lpc: lpc@1e789000 {
compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
lpc_snoop: lpc-snoop@0 {
compatible = "aspeed,ast2600-lpc-snoop";
reg = <0x0 0x80>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
snoop-ports = <0x80>;
};
};
LPC Host Interface Controller
-------------------
The LPC Host Interface Controller manages functions exposed to the host such as
LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
management and bus snoop configuration.
Required properties:
- compatible: One of:
"aspeed,ast2400-lpc-ctrl";
"aspeed,ast2500-lpc-ctrl";
"aspeed,ast2600-lpc-ctrl";
- reg: contains offset/length values of the host interface controller
memory regions
- clocks: contains a phandle to the syscon node describing the clocks.
There should then be one cell representing the clock to use
Optional properties:
- memory-region: A phandle to a reserved_memory region to be used for the LPC
to AHB mapping
- flash: A phandle to the SPI flash controller containing the flash to
be exposed over the LPC to AHB mapping
Example:
lpc_ctrl: lpc-ctrl@80 {
compatible = "aspeed,ast2500-lpc-ctrl";
reg = <0x80 0x80>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
memory-region = <&flash_memory>;
flash = <&spi>;
};
LPC Host Controller
-------------------
The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
between the host and the baseboard management controller. The registers exist
in the "host" portion of the Aspeed LPC controller, which must be the parent of
the LPC host controller node.
Required properties:
- compatible: One of:
"aspeed,ast2400-lhc";
"aspeed,ast2500-lhc";
"aspeed,ast2600-lhc";
- reg: contains offset/length values of the LHC memory regions. In the
AST2400 and AST2500 there are two regions.
Example:
lhc: lhc@a0 {
compatible = "aspeed,ast2500-lhc";
reg = <0xa0 0x24 0xc8 0x8>;
};
LPC reset control
-----------------
The UARTs present in the ASPEED SoC can have their resets tied to the reset
state of the LPC bus. Some systems may chose to modify this configuration.
Required properties:
- compatible: One of:
"aspeed,ast2600-lpc-reset";
"aspeed,ast2500-lpc-reset";
"aspeed,ast2400-lpc-reset";
- reg: offset and length of the IP in the LHC memory region
- #reset-controller indicates the number of reset cells expected
Example:
lpc_reset: reset-controller@98 {
compatible = "aspeed,ast2500-lpc-reset";
reg = <0x98 0x4>;
#reset-cells = <1>;
};
Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# # Copyright (c) 2021 Aspeed Tehchnology Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed Low Pin Count (LPC) Bus Controller
maintainers:
- Andrew Jeffery <andrew@aj.id.au>
- Chia-Wei Wang <chiawei_wang@aspeedtech.com>
description:
The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
primary use case of the Aspeed LPC controller is as a slave on the bus
(typically in a Baseboard Management Controller SoC), but under certain
conditions it can also take the role of bus master.
The LPC controller is represented as a multi-function device to account for the
mix of functionality, which includes, but is not limited to
* An IPMI Block Transfer[2] Controller
* An LPC Host Interface Controller manages functions exposed to the host such
as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
management and bus snoop configuration.
* A set of SuperIO[3] scratch registers enableing implementation of e.g. custom
hardware management protocols for handover between the host and baseboard
management controller.
Additionally the state of the LPC controller influences the pinmux
configuration, therefore the host portion of the controller is exposed as a
syscon as a means to arbitrate access.
properties:
compatible:
items:
- enum:
- aspeed,ast2400-lpc-v2
- aspeed,ast2500-lpc-v2
- aspeed,ast2600-lpc-v2
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^lpc-ctrl@[0-9a-f]+$":
type: object
additionalProperties: false
description: |
The LPC Host Interface Controller manages functions exposed to the host such as
LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
and bus snoop configuration.
properties:
compatible:
items:
- enum:
- aspeed,ast2400-lpc-ctrl
- aspeed,ast2500-lpc-ctrl
- aspeed,ast2600-lpc-ctrl
reg:
maxItems: 1
clocks:
maxItems: 1
memory-region:
maxItems: 1
description: handle to memory reservation for the LPC to AHB mapping region
flash:
$ref: /schemas/types.yaml#/definitions/phandle
description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping
required:
- compatible
- clocks
"^reset-controller@[0-9a-f]+$":
type: object
additionalProperties: false
description:
The UARTs present in the ASPEED SoC can have their resets tied to the reset
state of the LPC bus. Some systems may chose to modify this configuration
properties:
compatible:
items:
- enum:
- aspeed,ast2400-lpc-reset
- aspeed,ast2500-lpc-reset
- aspeed,ast2600-lpc-reset
reg:
maxItems: 1
'#reset-cells':
const: 1
required:
- compatible
- '#reset-cells'
"^lpc-snoop@[0-9a-f]+$":
type: object
additionalProperties: false
description:
The LPC snoop interface allows the BMC to listen on and record the data
bytes written by the Host to the targeted LPC I/O pots.
properties:
compatible:
items:
- enum:
- aspeed,ast2400-lpc-snoop
- aspeed,ast2500-lpc-snoop
- aspeed,ast2600-lpc-snoop
reg:
maxItems: 1
interrupts:
maxItems: 1
snoop-ports:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: The LPC I/O ports to snoop
required:
- compatible
- interrupts
- snoop-ports
"^uart-routing@[0-9a-f]+$":
$ref: /schemas/soc/aspeed/uart-routing.yaml#
description: The UART routing control under LPC register space
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties:
type: object
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/ast2600-clock.h>
lpc: lpc@1e789000 {
compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
lpc_ctrl: lpc-ctrl@80 {
compatible = "aspeed,ast2600-lpc-ctrl";
reg = <0x80 0x80>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
memory-region = <&flash_memory>;
flash = <&spi>;
};
lpc_reset: reset-controller@98 {
compatible = "aspeed,ast2600-lpc-reset";
reg = <0x98 0x4>;
#reset-cells = <1>;
};
lpc_snoop: lpc-snoop@90 {
compatible = "aspeed,ast2600-lpc-snoop";
reg = <0x90 0x8>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
snoop-ports = <0x80>;
};
};
Documentation/devicetree/bindings/mips/ralink.txt deleted 100644 → 0
View file @ 624ad333
Ralink MIPS SoC device tree bindings
1. SoCs
Each device tree must specify a compatible value for the Ralink SoC
it uses in the compatible property of the root node. The compatible
value must be one of the following values:
ralink,rt2880-soc
ralink,rt3050-soc
ralink,rt3052-soc
ralink,rt3350-soc
ralink,rt3352-soc
ralink,rt3883-soc
ralink,rt5350-soc
ralink,mt7620a-soc
ralink,mt7620n-soc
ralink,mt7628a-soc
ralink,mt7688a-soc
2. Boards
GARDENA smart Gateway (MT7688)
This board is based on the MediaTek MT7688 and equipped with 128 MiB
of DDR and 8 MiB of flash (SPI NOR) and additional 128MiB SPI NAND
storage.
------------------------------
Required root node properties:
- compatible = "gardena,smart-gateway-mt7688", "ralink,mt7688a-soc",
"ralink,mt7628a-soc";
Documentation/devicetree/bindings/mips/ralink.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/ralink.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ralink SoC based Platforms Device Tree Bindings
maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description: |
Boards with a Ralink SoC shall have the following properties.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Boards with Ralink RT2880 SoC
items:
- enum:
- ralink,rt2880-eval-board
- const: ralink,rt2880-soc
- description: Boards with Ralink RT3050 SoC
items:
- const: ralink,rt3050-soc
- description: Boards with Ralink RT3052 SoC
items:
- enum:
- ralink,rt3052-eval-board
- const: ralink,rt3052-soc
- description: Boards with Ralink RT3350 SoC
items:
- const: ralink,rt3350-soc
- description: Boards with Ralink RT3352 SoC
items:
- const: ralink,rt3352-soc
- description: Boards with Ralink RT3383 SoC
items:
- enum:
- ralink,rt3883-eval-board
- const: ralink,rt3383-soc
- description: Boards with Ralink RT5350 SoC
items:
- const: ralink,rt5350-soc
- description: Boards with Mediatek/Ralink MT7620A SoC
items:
- enum:
- ralink,mt7620a-eval-board
- const: ralink,mt7620a-soc
- description: Boards with Mediatek/Ralink MT7620N SoC
items:
- const: ralink,mt7620n-soc
- description: Boards with Mediatek/Ralink MT7628A SoC
items:
- enum:
- onion,omega2+
- vocore,vocore2
- const: ralink,mt7628a-soc
- description: Boards with Mediatek/Ralink MT7688A SoC
items:
- enum:
- gardena,smart-gateway-mt7688
- onion,omega2+
- const: ralink,mt7628a-soc
- description: Boards with Mediatek/Ralink MT7621 SoC
items:
- enum:
- gnubee,gb-pc1
- gnubee,gb-pc2
- const: mediatek,mt7621-soc
additionalProperties: true
...
Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
View file @ dcd68326
......@@ -15,7 +15,7 @@ properties:
oneOf:
- const: allwinner,sun8i-a83t-emac
- const: allwinner,sun8i-h3-emac
- const: allwinner,sun8i-r40-emac
- const: allwinner,sun8i-r40-gmac
- const: allwinner,sun8i-v3s-emac
- const: allwinner,sun50i-a64-emac
- items:
......@@ -93,7 +93,7 @@ allOf:
compatible:
contains:
enum:
- allwinner,sun8i-r40-emac
- allwinner,sun8i-r40-gmac
then:
properties:
......
Documentation/devicetree/bindings/net/broadcom-bluetooth.yaml
View file @ dcd68326
......@@ -50,16 +50,29 @@ properties:
by interrupts and "host-wakeup" interrupt-names
clocks:
minItems: 1
maxItems: 2
description: 1 or 2 clocks as defined in clock-names below,
in that order
clock-names:
description: Names of the 1 to 2 supplied clocks
items:
oneOf:
- const: extclk
deprecated: true
description: Deprecated in favor of txco
- const: txco
description: >
external reference clock (not a standalone crystal)
- const: lpo
- const: extclk
description: >
external low power 32.768 kHz clock
- items:
- const: txco
- const: lpo
vbat-supply:
description: phandle to regulator supply for VBAT
......
Documentation/devicetree/bindings/net/marvell-bluetooth.txt deleted 100644 → 0
View file @ 624ad333
Marvell Bluetooth Chips
-----------------------
This documents the binding structure and common properties for serial
attached Marvell Bluetooth devices. The following chips are included in
this binding:
* Marvell 88W8897 Bluetooth devices
Required properties:
- compatible: should be:
"mrvl,88w8897"
Optional properties:
None so far
Example:
&serial0 {
compatible = "ns16550a";
...
bluetooth {
compatible = "mrvl,88w8897";
};
};
Documentation/devicetree/bindings/net/marvell-bluetooth.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/marvell-bluetooth.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Marvell Bluetooth chips
description: |
This documents the binding structure and common properties for serial
attached Marvell Bluetooth devices.
maintainers:
- Rob Herring <robh@kernel.org>
properties:
compatible:
const: mrvl,88w8897
required:
- compatible
additionalProperties: false
examples:
- |
serial {
bluetooth {
compatible = "mrvl,88w8897";
};
};
Documentation/devicetree/bindings/net/nfc/marvell,nci.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/marvell,nci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell International Ltd. NCI NFC controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
enum:
- marvell,nfc-i2c
- marvell,nfc-spi
- marvell,nfc-uart
hci-muxed:
type: boolean
description: |
Specifies that the chip is muxing NCI over HCI frames
interrupts:
maxItems: 1
reg:
maxItems: 1
reset-n-io:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
maxItems: 1
description: |
Output GPIO pin used to reset the chip (active low)
i2c-int-falling:
type: boolean
description: |
For I2C type of connection. Specifies that the chip read event shall be
trigged on falling edge.
i2c-int-rising:
type: boolean
description: |
For I2C type of connection. Specifies that the chip read event shall be
trigged on rising edge.
break-control:
type: boolean
description: |
For UART type of connection. Specifies that the chip needs specific break
management.
flow-control:
type: boolean
description: |
For UART type of connection. Specifies that the chip is using RTS/CTS.
spi-cpha: true
spi-cpol: true
spi-max-frequency: true
required:
- compatible
allOf:
- if:
properties:
compatible:
contains:
const: marvell,nfc-i2c
then:
properties:
break-control: false
flow-control: false
spi-cpha: false
spi-cpol: false
spi-max-frequency: false
required:
- reg
- if:
properties:
compatible:
contains:
const: marvell,nfc-spi
then:
properties:
break-control: false
flow-control: false
i2c-int-falling: false
i2c-int-rising: false
required:
- reg
- if:
properties:
compatible:
contains:
const: marvell,nfc-uart
then:
properties:
i2c-int-falling: false
i2c-int-rising: false
interrupts: false
spi-cpha: false
spi-cpol: false
spi-max-frequency: false
reg: false
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
nfc@8 {
compatible = "marvell,nfc-i2c";
reg = <0x8>;
interrupt-parent = <&gpio3>;
interrupts = <21 IRQ_TYPE_EDGE_RISING>;
i2c-int-rising;
reset-n-io = <&gpio3 19 GPIO_ACTIVE_HIGH>;
};
};
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
nfc@0 {
compatible = "marvell,nfc-spi";
reg = <0>;
spi-max-frequency = <3000000>;
spi-cpha;
spi-cpol;
interrupt-parent = <&gpio1>;
interrupts = <17 IRQ_TYPE_EDGE_RISING>;
reset-n-io = <&gpio3 19 GPIO_ACTIVE_HIGH>;
};
};
- |
#include <dt-bindings/gpio/gpio.h>
uart {
nfc {
compatible = "marvell,nfc-uart";
reset-n-io = <&gpio3 16 GPIO_ACTIVE_HIGH>;
hci-muxed;
flow-control;
};
};
Documentation/devicetree/bindings/net/nfc/nfcmrvl.txt deleted 100644 → 0
View file @ 624ad333
* Marvell International Ltd. NCI NFC Controller
Required properties:
- compatible: Should be:
- "marvell,nfc-uart" or "mrvl,nfc-uart" for UART devices
- "marvell,nfc-i2c" for I2C devices
- "marvell,nfc-spi" for SPI devices
Optional SoC specific properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
- reset-n-io: Output GPIO pin used to reset the chip (active low).
- hci-muxed: Specifies that the chip is muxing NCI over HCI frames.
Optional UART-based chip specific properties:
- flow-control: Specifies that the chip is using RTS/CTS.
- break-control: Specifies that the chip needs specific break management.
Optional I2C-based chip specific properties:
- i2c-int-falling: Specifies that the chip read event shall be trigged on
falling edge.
- i2c-int-rising: Specifies that the chip read event shall be trigged on
rising edge.
Example (for ARM-based BeagleBoard Black with 88W8887 on UART5):
&uart5 {
nfcmrvluart: nfcmrvluart@5 {
compatible = "marvell,nfc-uart";
reset-n-io = <&gpio3 16 0>;
hci-muxed;
flow-control;
}
};
Example (for ARM-based BeagleBoard Black with 88W8887 on I2C1):
&i2c1 {
clock-frequency = <400000>;
nfcmrvli2c0: i2c@1 {
compatible = "marvell,nfc-i2c";
reg = <0x8>;
/* I2C INT configuration */
interrupt-parent = <&gpio3>;
interrupts = <21 0>;
/* I2C INT trigger configuration */
i2c-int-rising;
/* Reset IO */
reset-n-io = <&gpio3 19 0>;
};
};
Example (for ARM-based BeagleBoard Black on SPI0):
&spi0 {
mrvlnfcspi0: spi@0 {
compatible = "marvell,nfc-spi";
reg = <0>;
/* SPI Bus configuration */
spi-max-frequency = <3000000>;
spi-cpha;
spi-cpol;
/* SPI INT configuration */
interrupt-parent = <&gpio1>;
interrupts = <17 0>;
/* Reset IO */
reset-n-io = <&gpio3 19 0>;
};
};
Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/nxp,nci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP Semiconductors NCI NFC controller
maintainers:
- Charles Gorand <charles.gorand@effinnov.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
oneOf:
- const: nxp,nxp-nci-i2c
- items:
- const: nxp,pn547
- const: nxp,nxp-nci-i2c
enable-gpios:
description: Output GPIO pin used for enabling/disabling the controller
firmware-gpios:
description: Output GPIO pin used to enter firmware download mode
interrupts:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- enable-gpios
- interrupts
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
nfc@29 {
compatible = "nxp,nxp-nci-i2c";
reg = <0x29>;
interrupt-parent = <&gpio1>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
};
};
Documentation/devicetree/bindings/net/nfc/nxp,pn532.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/nxp,pn532.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP Semiconductors PN532 NFC controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
oneOf:
- const: nxp,pn532
- description: Deprecated bindings
enum:
- nxp,pn532-i2c
- nxp,pn533-i2c
deprecated: true
interrupts:
description: Required if connected via I2C
maxItems: 1
reg:
description: Required if connected via I2C
maxItems: 1
required:
- compatible
dependencies:
interrupts: [ 'reg' ]
additionalProperties: false
examples:
# PN532 on I2C bus
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
nfc@24 {
compatible = "nxp,pn532";
reg = <0x24>;
interrupt-parent = <&gpio1>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
};
};
# PN532 connected via UART
- |
serial@49042000 {
reg = <0x49042000 0x400>;
nfc {
compatible = "nxp,pn532";
};
};
Documentation/devicetree/bindings/net/nfc/nxp,pn544.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/nxp,pn544.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP Semiconductors PN544 NFC Controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
const: nxp,pn544-i2c
reg:
maxItems: 1
interrupts:
maxItems: 1
enable-gpios:
description: Output GPIO pin used for enabling/disabling the PN544
maxItems: 1
firmware-gpios:
description: Output GPIO pin used to enter firmware download mode
maxItems: 1
required:
- compatible
- reg
- interrupts
- enable-gpios
- firmware-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
nfc@28 {
compatible = "nxp,pn544-i2c";
reg = <0x28>;
interrupt-parent = <&gpio1>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
firmware-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
};
};
Documentation/devicetree/bindings/net/nfc/nxp-nci.txt deleted 100644 → 0
View file @ 624ad333
* NXP Semiconductors NXP NCI NFC Controllers
Required properties:
- compatible: Should be "nxp,nxp-nci-i2c".
- clock-frequency: I²C work frequency.
- reg: address on the bus
- interrupts: GPIO interrupt to which the chip is connected
- enable-gpios: Output GPIO pin used for enabling/disabling the chip
Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
- firmware-gpios: Output GPIO pin used to enter firmware download mode
Example (for ARM-based BeagleBone with NPC100 NFC controller on I2C2):
&i2c2 {
npc100: npc100@29 {
compatible = "nxp,nxp-nci-i2c";
reg = <0x29>;
clock-frequency = <100000>;
interrupt-parent = <&gpio1>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
};
};
Documentation/devicetree/bindings/net/nfc/pn532.txt deleted 100644 → 0
View file @ 624ad333
* NXP Semiconductors PN532 NFC Controller
Required properties:
- compatible: Should be
- "nxp,pn532" Place a node with this inside the devicetree node of the bus
where the NFC chip is connected to.
Currently the kernel has phy bindings for uart and i2c.
- "nxp,pn532-i2c" (DEPRECATED) only works for the i2c binding.
- "nxp,pn533-i2c" (DEPRECATED) only works for the i2c binding.
Required properties if connected on i2c:
- clock-frequency: I²C work frequency.
- reg: for the I²C bus address. This is fixed at 0x24 for the PN532.
- interrupts: GPIO interrupt to which the chip is connected
Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
Example (for ARM-based BeagleBone with PN532 on I2C2):
&i2c2 {
pn532: nfc@24 {
compatible = "nxp,pn532";
reg = <0x24>;
clock-frequency = <400000>;
interrupt-parent = <&gpio1>;
interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
};
};
Example (for PN532 connected via uart):
uart4: serial@49042000 {
compatible = "ti,omap3-uart";
pn532: nfc {
compatible = "nxp,pn532";
};
};
Documentation/devicetree/bindings/net/nfc/pn544.txt deleted 100644 → 0
View file @ 624ad333
* NXP Semiconductors PN544 NFC Controller
Required properties:
- compatible: Should be "nxp,pn544-i2c".
- clock-frequency: I²C work frequency.
- reg: address on the bus
- interrupts: GPIO interrupt to which the chip is connected
- enable-gpios: Output GPIO pin used for enabling/disabling the PN544
- firmware-gpios: Output GPIO pin used to enter firmware download mode
Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
Example (for ARM-based BeagleBone with PN544 on I2C2):
&i2c2 {
pn544: pn544@28 {
compatible = "nxp,pn544-i2c";
reg = <0x28>;
clock-frequency = <400000>;
interrupt-parent = <&gpio1>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
firmware-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
};
};
Documentation/devicetree/bindings/net/nfc/st,st-nci.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/st,st-nci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics ST NCI NFC controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
enum:
- st,st21nfcb-i2c
- st,st21nfcb-spi
- st,st21nfcc-i2c
reset-gpios:
description: Output GPIO pin used for resetting the controller
ese-present:
type: boolean
description: |
Specifies that an ese is physically connected to the controller
interrupts:
maxItems: 1
reg:
maxItems: 1
spi-max-frequency: true
uicc-present:
type: boolean
description: |
Specifies that the uicc swp signal can be physically connected to the
controller
required:
- compatible
- interrupts
- reg
- reset-gpios
if:
properties:
compatible:
contains:
enum:
- st,st21nfcb-i2c
- st,st21nfcc-i2c
then:
properties:
spi-max-frequency: false
else:
required:
- spi-max-frequency
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
nfc@8 {
compatible = "st,st21nfcb-i2c";
reg = <0x08>;
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
ese-present;
uicc-present;
};
};
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
nfc@0 {
compatible = "st,st21nfcb-spi";
reg = <0>;
spi-max-frequency = <4000000>;
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_EDGE_RISING>;
reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
ese-present;
uicc-present;
};
};
Documentation/devicetree/bindings/net/nfc/st,st21nfca.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/st,st21nfca.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics SAS ST21NFCA NFC controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
const: st,st21nfca-i2c
enable-gpios:
description: Output GPIO pin used for enabling/disabling the controller
ese-present:
type: boolean
description: |
Specifies that an ese is physically connected to the controller
interrupts:
maxItems: 1
reg:
maxItems: 1
uicc-present:
type: boolean
description: |
Specifies that the uicc swp signal can be physically connected to the
controller
required:
- compatible
- enable-gpios
- interrupts
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
nfc@1 {
compatible = "st,st21nfca-i2c";
reg = <0x1>;
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
ese-present;
uicc-present;
};
};
Documentation/devicetree/bindings/net/nfc/st,st95hf.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/st,st95hf.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics ST95HF NFC controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
const: st,st95hf
enable-gpio:
description: Output GPIO pin used for enabling/disabling the controller
interrupts:
maxItems: 1
reg:
maxItems: 1
st95hfvin-supply:
description: ST95HF transceiver's Vin regulator supply
spi-max-frequency: true
required:
- compatible
- enable-gpio
- interrupts
- reg
- spi-max-frequency
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
nfc@0{
compatible = "st,st95hf";
reg = <0>;
spi-max-frequency = <1000000>;
enable-gpio = <&pio4 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&pio0>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
};
};
Documentation/devicetree/bindings/net/nfc/st-nci-i2c.txt deleted 100644 → 0
View file @ 624ad333
* STMicroelectronics SAS. ST NCI NFC Controller
Required properties:
- compatible: Should be "st,st21nfcb-i2c" or "st,st21nfcc-i2c".
- clock-frequency: I²C work frequency.
- reg: address on the bus
- interrupts: GPIO interrupt to which the chip is connected
- reset-gpios: Output GPIO pin used to reset the ST21NFCB
Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
- ese-present: Specifies that an ese is physically connected to the nfc
controller.
- uicc-present: Specifies that the uicc swp signal can be physically
connected to the nfc controller.
Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2):
&i2c2 {
st21nfcb: st21nfcb@8 {
compatible = "st,st21nfcb-i2c";
reg = <0x08>;
clock-frequency = <400000>;
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
ese-present;
uicc-present;
};
};
Documentation/devicetree/bindings/net/nfc/st-nci-spi.txt deleted 100644 → 0
View file @ 624ad333
* STMicroelectronics SAS. ST NCI NFC Controller
Required properties:
- compatible: Should be "st,st21nfcb-spi"
- spi-max-frequency: Maximum SPI frequency (<= 4000000).
- interrupts: GPIO interrupt to which the chip is connected
- reset-gpios: Output GPIO pin used to reset the ST21NFCB
Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
- ese-present: Specifies that an ese is physically connected to the nfc
controller.
- uicc-present: Specifies that the uicc swp signal can be physically
connected to the nfc controller.
Example (for ARM-based BeagleBoard xM with ST21NFCB on SPI4):
&mcspi4 {
st21nfcb: st21nfcb@0 {
compatible = "st,st21nfcb-spi";
clock-frequency = <4000000>;
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_EDGE_RISING>;
reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
ese-present;
uicc-present;
};
};
Documentation/devicetree/bindings/net/nfc/st21nfca.txt deleted 100644 → 0
View file @ 624ad333
* STMicroelectronics SAS. ST21NFCA NFC Controller
Required properties:
- compatible: Should be "st,st21nfca-i2c".
- clock-frequency: I²C work frequency.
- reg: address on the bus
- enable-gpios: Output GPIO pin used for enabling/disabling the ST21NFCA
Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
- ese-present: Specifies that an ese is physically connected to the nfc
controller.
- uicc-present: Specifies that the uicc swp signal can be physically
connected to the nfc controller.
Example (for ARM-based BeagleBoard xM with ST21NFCA on I2C2):
&i2c2 {
st21nfca: st21nfca@1 {
compatible = "st,st21nfca-i2c";
reg = <0x01>;
clock-frequency = <400000>;
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
ese-present;
uicc-present;
};
};
Documentation/devicetree/bindings/net/nfc/st95hf.txt deleted 100644 → 0
View file @ 624ad333
* STMicroelectronics : NFC Transceiver ST95HF
ST NFC Transceiver is required to attach with SPI bus.
ST95HF node should be defined in DT as SPI slave device of SPI
master with which ST95HF transceiver is physically connected.
The properties defined below are required to be the part of DT
to include ST95HF transceiver into the platform.
Required properties:
===================
- reg: Address of SPI slave "ST95HF transceiver" on SPI master bus.
- compatible: should be "st,st95hf" for ST95HF NFC transceiver
- spi-max-frequency: Max. operating SPI frequency for ST95HF
transceiver.
- enable-gpio: GPIO line to enable ST95HF transceiver.
- interrupts : Standard way to define ST95HF transceiver's out
interrupt.
Optional property:
=================
- st95hfvin-supply : This is an optional property. It contains a
phandle to ST95HF transceiver's regulator supply node in DT.
Example:
=======
spi@9840000 {
reg = <0x9840000 0x110>;
#address-cells = <1>;
#size-cells = <0>;
cs-gpios = <&pio0 4>;
st95hf@0{
reg = <0>;
compatible = "st,st95hf";
spi-max-frequency = <1000000>;
enable-gpio = <&pio4 0>;
interrupt-parent = <&pio0>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
};
};
Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/ti,trf7970a.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments TRF7970A RFID/NFC/15693 Transceiver
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Mark Greer <mgreer@animalcreek.com>
properties:
compatible:
const: ti,trf7970a
autosuspend-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Specify autosuspend delay in milliseconds.
clock-frequency:
description: |
Set to specify that the input frequency to the trf7970a is 13560000Hz or
27120000Hz
en2-rf-quirk:
type: boolean
description: |
Specify that the trf7970a being used has the "EN2 RF" erratum
interrupts:
maxItems: 1
irq-status-read-quirk:
type: boolean
description: |
Specify that the trf7970a being used has the "IRQ Status Read" erratum
reg:
maxItems: 1
spi-max-frequency: true
ti,enable-gpios:
minItems: 1
maxItems: 2
description: |
One or two GPIO entries used for 'EN' and 'EN2' pins on the TRF7970A. EN2
is optional.
vdd-io-supply:
description: |
Regulator specifying voltage for VDD-IO
vin-supply:
description: |
Regulator for supply voltage to VIN pin
required:
- compatible
- interrupts
- reg
- spi-max-frequency
- ti,enable-gpios
- vin-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
nfc@0 {
compatible = "ti,trf7970a";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&trf7970a_default>;
spi-max-frequency = <2000000>;
interrupt-parent = <&gpio2>;
interrupts = <14 0>;
ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>,
<&gpio2 5 GPIO_ACTIVE_HIGH>;
vin-supply = <&ldo3_reg>;
vdd-io-supply = <&ldo2_reg>;
autosuspend-delay = <30000>;
irq-status-read-quirk;
en2-rf-quirk;
clock-frequency = <27120000>;
};
};
Documentation/devicetree/bindings/net/nfc/trf7970a.txt deleted 100644 → 0
View file @ 624ad333
* Texas Instruments TRF7970A RFID/NFC/15693 Transceiver
Required properties:
- compatible: Should be "ti,trf7970a".
- spi-max-frequency: Maximum SPI frequency (<= 2000000).
- interrupts: A single interrupt specifier.
- ti,enable-gpios: One or two GPIO entries used for 'EN' and 'EN2' pins on the
TRF7970A. EN2 is optional.
- vin-supply: Regulator for supply voltage to VIN pin
Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
- autosuspend-delay: Specify autosuspend delay in milliseconds.
- irq-status-read-quirk: Specify that the trf7970a being used has the
"IRQ Status Read" erratum.
- en2-rf-quirk: Specify that the trf7970a being used has the "EN2 RF"
erratum.
- vdd-io-supply: Regulator specifying voltage for vdd-io
- clock-frequency: Set to specify that the input frequency to the trf7970a is 13560000Hz or 27120000Hz
Example (for ARM-based BeagleBone with TRF7970A on SPI1):
&spi1 {
nfc@0 {
compatible = "ti,trf7970a";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&trf7970a_default>;
spi-max-frequency = <2000000>;
interrupt-parent = <&gpio2>;
interrupts = <14 0>;
ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>,
<&gpio2 5 GPIO_ACTIVE_HIGH>;
vin-supply = <&ldo3_reg>;
vdd-io-supply = <&ldo2_reg>;
autosuspend-delay = <30000>;
irq-status-read-quirk;
en2-rf-quirk;
clock-frequency = <27120000>;
};
};
Documentation/devicetree/bindings/net/qcom,ipa.yaml
View file @ dcd68326
......@@ -64,7 +64,8 @@ properties:
- const: gsi
iommus:
maxItems: 1
minItems: 1
maxItems: 2
clocks:
maxItems: 1
......
Documentation/devicetree/bindings/net/realtek-bluetooth.yaml
View file @ dcd68326
......@@ -34,6 +34,8 @@ properties:
maxItems: 1
description: GPIO specifier, used to wakeup the host processor
max-speed: true
required:
- compatible
......
Documentation/devicetree/bindings/net/snps,dwmac.yaml
View file @ dcd68326
......@@ -50,7 +50,7 @@ properties:
- allwinner,sun7i-a20-gmac
- allwinner,sun8i-a83t-emac
- allwinner,sun8i-h3-emac
- allwinner,sun8i-r40-emac
- allwinner,sun8i-r40-gmac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
- loongson,ls2k-dwmac
......@@ -318,7 +318,7 @@ allOf:
- allwinner,sun7i-a20-gmac
- allwinner,sun8i-a83t-emac
- allwinner,sun8i-h3-emac
- allwinner,sun8i-r40-emac
- allwinner,sun8i-r40-gmac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
- ingenic,jz4775-mac
......@@ -366,7 +366,7 @@ allOf:
- allwinner,sun7i-a20-gmac
- allwinner,sun8i-a83t-emac
- allwinner,sun8i-h3-emac
- allwinner,sun8i-r40-emac
- allwinner,sun8i-r40-gmac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
- loongson,ls2k-dwmac
......
Documentation/devicetree/bindings/net/ti,bluetooth.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ti,bluetooth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments Bluetooth Chips
maintainers:
- David Lechner <david@lechnology.com>
description: |
This documents the binding structure and common properties for serial
attached TI Bluetooth devices. The following chips are included in this
binding:
* TI CC256x Bluetooth devices
* TI WiLink 7/8 (wl12xx/wl18xx) Shared Transport BT/FM/GPS devices
TI WiLink devices have a UART interface for providing Bluetooth, FM radio,
and GPS over what's called "shared transport". The shared transport is
standard BT HCI protocol with additional channels for the other functions.
TI WiLink devices also have a separate WiFi interface as described in
wireless/ti,wlcore.yaml.
This bindings follows the UART slave device binding in ../serial/serial.yaml.
properties:
compatible:
enum:
- ti,cc2560
- ti,wl1271-st
- ti,wl1273-st
- ti,wl1281-st
- ti,wl1283-st
- ti,wl1285-st
- ti,wl1801-st
- ti,wl1805-st
- ti,wl1807-st
- ti,wl1831-st
- ti,wl1835-st
- ti,wl1837-st
enable-gpios:
maxItems: 1
vio-supply:
description: Vio input supply (1.8V)
vbat-supply:
description: Vbat input supply (2.9-4.8V)
clocks:
maxItems: 1
clock-names:
items:
- const: ext_clock
max-speed:
default: 3000000
nvmem-cells:
maxItems: 1
description:
Nvmem data cell that contains a 6 byte BD address with the most
significant byte first (big-endian).
nvmem-cell-names:
items:
- const: bd-address
required:
- compatible
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
serial {
bluetooth {
compatible = "ti,wl1835-st";
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
clocks = <&clk32k_wl18xx>;
clock-names = "ext_clock";
nvmem-cells = <&bd_address>;
nvmem-cell-names = "bd-address";
};
};
Documentation/devicetree/bindings/net/ti-bluetooth.txt deleted 100644 → 0
View file @ 624ad333
Texas Instruments Bluetooth Chips
---------------------------------
This documents the binding structure and common properties for serial
attached TI Bluetooth devices. The following chips are included in this
binding:
* TI CC256x Bluetooth devices
* TI WiLink 7/8 (wl12xx/wl18xx) Shared Transport BT/FM/GPS devices
TI WiLink devices have a UART interface for providing Bluetooth, FM radio,
and GPS over what's called "shared transport". The shared transport is
standard BT HCI protocol with additional channels for the other functions.
TI WiLink devices also have a separate WiFi interface as described in
wireless/ti,wlcore.txt.
This bindings follows the UART slave device binding in ../serial/serial.yaml.
Required properties:
- compatible: should be one of the following:
"ti,cc2560"
"ti,wl1271-st"
"ti,wl1273-st"
"ti,wl1281-st"
"ti,wl1283-st"
"ti,wl1285-st"
"ti,wl1801-st"
"ti,wl1805-st"
"ti,wl1807-st"
"ti,wl1831-st"
"ti,wl1835-st"
"ti,wl1837-st"
Optional properties:
- enable-gpios : GPIO signal controlling enabling of BT. Active high.
- vio-supply : Vio input supply (1.8V)
- vbat-supply : Vbat input supply (2.9-4.8V)
- clocks : Must contain an entry, for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entry:
"ext_clock" (External clock provided to the TI combo chip).
- nvmem-cells: phandle to nvmem data cell that contains a 6 byte BD address
with the most significant byte first (big-endian).
- nvmem-cell-names: "bd-address" (required when nvmem-cells is specified)
Example:
&serial0 {
compatible = "ns16550a";
...
bluetooth {
compatible = "ti,wl1835-st";
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
clocks = <&clk32k_wl18xx>;
clock-names = "ext_clock";
nvmem-cells = <&bd_address>;
nvmem-cell-names = "bd-address";
};
};
Documentation/devicetree/bindings/net/wireless/esp,esp8089.txt deleted 100644 → 0
View file @ 624ad333
Espressif ESP8089 wireless SDIO devices
This node provides properties for controlling the ESP8089 wireless device.
The node is expected to be specified as a child node to the SDIO controller
that connects the device to the system.
Required properties:
- compatible : Should be "esp,esp8089".
Optional properties:
- esp,crystal-26M-en: Integer value for the crystal_26M_en firmware parameter
Example:
&mmc1 {
#address-cells = <1>;
#size-cells = <0>;
vmmc-supply = <&reg_dldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
esp8089: sdio_wifi@1 {
compatible = "esp,esp8089";
reg = <1>;
esp,crystal-26M-en = <2>;
};
};
Documentation/devicetree/bindings/net/wireless/esp,esp8089.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/wireless/esp,esp8089.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Espressif ESP8089 Device Tree Bindings
maintainers:
- Hans de Goede <hdegoede@redhat.com>
properties:
compatible:
const: esp,esp8089
reg:
maxItems: 1
esp,crystal-26M-en:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
Value for the crystal_26M_en firmware parameter
required:
- compatible
- reg
additionalProperties: false
examples:
- |
mmc {
#address-cells = <1>;
#size-cells = <0>;
wifi@1 {
compatible = "esp,esp8089";
reg = <1>;
esp,crystal-26M-en = <2>;
};
};
...
Documentation/devicetree/bindings/net/wireless/ti,wlcore,spi.txt deleted 100644 → 0
View file @ 624ad333
* Texas Instruments wl12xx/wl18xx wireless lan controller
The wl12xx/wl18xx chips can be connected via SPI or via SDIO. This
document describes the binding for the SPI connected chip.
Required properties:
- compatible : Should be one of the following:
* "ti,wl1271"
* "ti,wl1273"
* "ti,wl1281"
* "ti,wl1283"
* "ti,wl1801"
* "ti,wl1805"
* "ti,wl1807"
* "ti,wl1831"
* "ti,wl1835"
* "ti,wl1837"
- reg : Chip select address of device
- spi-max-frequency : Maximum SPI clocking speed of device in Hz
- interrupts : Should contain parameters for 1 interrupt line.
- vwlan-supply : Point the node of the regulator that powers/enable the
wl12xx/wl18xx chip
Optional properties:
- ref-clock-frequency : Reference clock frequency (should be set for wl12xx)
- clock-xtal : boolean, clock is generated from XTAL
- Please consult Documentation/devicetree/bindings/spi/spi-bus.txt
for optional SPI connection related properties,
Examples:
For wl12xx family:
&spi1 {
wlcore: wlcore@1 {
compatible = "ti,wl1271";
reg = <1>;
spi-max-frequency = <48000000>;
interrupt-parent = <&gpio3>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
vwlan-supply = <&vwlan_fixed>;
clock-xtal;
ref-clock-frequency = <38400000>;
};
};
For wl18xx family:
&spi0 {
wlcore: wlcore@0 {
compatible = "ti,wl1835";
reg = <0>;
spi-max-frequency = <48000000>;
interrupt-parent = <&gpio0>;
interrupts = <27 IRQ_TYPE_EDGE_RISING>;
vwlan-supply = <&vwlan_fixed>;
};
};
Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt deleted 100644 → 0
View file @ 624ad333
TI Wilink 6/7/8 (wl12xx/wl18xx) SDIO devices
This node provides properties for controlling the wilink wireless device. The
node is expected to be specified as a child node to the SDIO controller that
connects the device to the system.
Required properties:
- compatible: should be one of the following:
* "ti,wl1271"
* "ti,wl1273"
* "ti,wl1281"
* "ti,wl1283"
* "ti,wl1285"
* "ti,wl1801"
* "ti,wl1805"
* "ti,wl1807"
* "ti,wl1831"
* "ti,wl1835"
* "ti,wl1837"
- interrupts : specifies attributes for the out-of-band interrupt.
Optional properties:
- ref-clock-frequency : ref clock frequency in Hz
- tcxo-clock-frequency : tcxo clock frequency in Hz
Note: the *-clock-frequency properties assume internal clocks. In case of external
clock, new bindings (for parsing the clock nodes) have to be added.
Example:
&mmc3 {
vmmc-supply = <&wlan_en_reg>;
bus-width = <4>;
cap-power-off-card;
keep-power-in-suspend;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio0>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
};
};
Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml 0 → 100644
View file @ dcd68326
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/wireless/ti,wlcore.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments Wilink 6/7/8 (wl12xx/wl18xx) Wireless LAN Controller
maintainers:
- Tony Lindgren <tony@atomide.com>
description:
The wl12xx/wl18xx chips can be connected via SPI or via SDIO.
Note that the *-clock-frequency properties assume internal clocks. In case
of external clocks, new bindings (for parsing the clock nodes) have to be
added.
properties:
compatible:
enum:
- ti,wl1271
- ti,wl1273
- ti,wl1281
- ti,wl1283
- ti,wl1285
- ti,wl1801
- ti,wl1805
- ti,wl1807
- ti,wl1831
- ti,wl1835
- ti,wl1837
reg:
maxItems: 1
description:
This is required when connected via SPI, and optional when connected via
SDIO.
spi-max-frequency: true
interrupts:
minItems: 1
maxItems: 2
interrupt-names:
items:
- const: irq
- const: wakeup
vwlan-supply:
description:
Points to the node of the regulator that powers/enable the wl12xx/wl18xx
chip. This is required when connected via SPI.
ref-clock-frequency:
description: Reference clock frequency.
tcxo-clock-frequency:
description: TCXO clock frequency.
clock-xtal:
$ref: /schemas/types.yaml#/definitions/flag
description: Indicates that the clock is generated from XTAL.
required:
- compatible
- interrupts
if:
properties:
compatible:
contains:
enum:
- ti,wl1271
- ti,wl1273
- ti,wl1281
- ti,wl1283
then:
required:
- ref-clock-frequency
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
// For wl12xx family:
spi1 {
#address-cells = <1>;
#size-cells = <0>;
wlcore1: wlcore@1 {
compatible = "ti,wl1271";
reg = <1>;
spi-max-frequency = <48000000>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
vwlan-supply = <&vwlan_fixed>;
clock-xtal;
ref-clock-frequency = <38400000>;
};
};
// For wl18xx family:
spi2 {
#address-cells = <1>;
#size-cells = <0>;
wlcore2: wlcore@0 {
compatible = "ti,wl1835";
reg = <0>;
spi-max-frequency = <48000000>;
interrupts = <27 IRQ_TYPE_EDGE_RISING>;
vwlan-supply = <&vwlan_fixed>;
};
};
// SDIO example:
mmc3 {
vmmc-supply = <&wlan_en_reg>;
bus-width = <4>;
cap-power-off-card;
keep-power-in-suspend;
#address-cells = <1>;
#size-cells = <0>;
wlcore3: wlcore@2 {
compatible = "ti,wl1835";
reg = <2>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
};
};
Documentation/devicetree/bindings/numa.txt
View file @ dcd68326
......@@ -103,7 +103,51 @@ Example:
};
==============================================================================
4 - Example dts
4 - Empty memory nodes
==============================================================================
Empty memory nodes, which no memory resides in, are allowed. There are no
device nodes for these empty memory nodes. However, the NUMA node IDs and
distance maps are still valid and memory may be added into them through
hotplug afterwards.
Example:
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
numa-node-id = <0>;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
numa-node-id = <1>;
};
/* Empty memory node 2 and 3 */
distance-map {
compatible = "numa-distance-map-v1";
distance-matrix = <0 0 10>,
<0 1 20>,
<0 2 40>,
<0 3 20>,
<1 0 20>,
<1 1 10>,
<1 2 20>,
<1 3 40>,
<2 0 40>,
<2 1 20>,
<2 2 10>,
<2 3 20>,
<3 0 20>,
<3 1 40>,
<3 2 20>,
<3 3 10>;
};
==============================================================================
5 - Example dts
==============================================================================
Dual socket system consists of 2 boards connected through ccn bus and
......
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Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
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......@@ -88,6 +88,7 @@ required:
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
- if:
properties:
compatible:
......
Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
View file @ dcd68326
......@@ -11,6 +11,7 @@ maintainers:
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
View file @ dcd68326
......@@ -19,6 +19,7 @@ properties:
- renesas,r8a774b1-pcie-ep # RZ/G2N
- renesas,r8a774c0-pcie-ep # RZ/G2E
- renesas,r8a774e1-pcie-ep # RZ/G2H
- renesas,r8a7795-pcie-ep # R-Car H3
- const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2
reg:
......
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View file @ dcd68326
......@@ -31,9 +31,7 @@ properties:
- sifive,bullet0
- sifive,e5
- sifive,e7
- sifive,e51
- sifive,e71
- sifive,u54-mc
- sifive,u74-mc
- sifive,u54
- sifive,u74
......@@ -41,6 +39,12 @@ properties:
- sifive,u7
- canaan,k210
- const: riscv
- items:
- enum:
- sifive,e51
- sifive,u54-mc
- const: sifive,rocket0
- const: riscv
- const: riscv # Simulator only
description:
Identifies that the hart uses the RISC-V instruction set
......
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Documentation/devicetree/bindings/sram/sram.yaml
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......@@ -60,7 +60,7 @@ properties:
type: boolean
patternProperties:
"^([a-z]*-)?sram(-section)?@[a-f0-9]+$":
"^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$":
type: object
description:
Each child of the sram node specifies a region of reserved memory.
......
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scripts/dtc/dtc.h
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scripts/dtc/flattree.c
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scripts/dtc/libfdt/fdt.c
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scripts/dtc/libfdt/fdt_rw.c
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scripts/dtc/libfdt/fdt_strerror.c
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scripts/dtc/libfdt/libfdt.h
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scripts/dtc/livetree.c
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scripts/dtc/treesource.c
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scripts/dtc/util.h
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scripts/dtc/version_gen.h
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scripts/dtc/yamltree.c
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